CN113097131A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN113097131A CN113097131A CN202110330030.9A CN202110330030A CN113097131A CN 113097131 A CN113097131 A CN 113097131A CN 202110330030 A CN202110330030 A CN 202110330030A CN 113097131 A CN113097131 A CN 113097131A
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- 238000000034 method Methods 0.000 title claims abstract description 69
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 120
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000001039 wet etching Methods 0.000 claims abstract description 18
- 239000010410 layer Substances 0.000 claims description 113
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 50
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 42
- 239000000243 solution Substances 0.000 claims description 30
- 229920002120 photoresistant polymer Polymers 0.000 claims description 26
- 239000011241 protective layer Substances 0.000 claims description 26
- 239000011259 mixed solution Substances 0.000 claims description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid Substances OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 6
- 239000008367 deionised water Substances 0.000 claims description 5
- 229910021641 deionized water Inorganic materials 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 13
- 238000004140 cleaning Methods 0.000 description 42
- 239000012535 impurity Substances 0.000 description 8
- 239000007788 liquid Substances 0.000 description 7
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000001914 filtration Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 239000000908 ammonium hydroxide Substances 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000005034 decoration Methods 0.000 description 2
- URQUNWYOBNUYJQ-UHFFFAOYSA-N diazonaphthoquinone Chemical compound C1=CC=C2C(=O)C(=[N]=[N])C=CC2=C1 URQUNWYOBNUYJQ-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 2
- 229910052753 mercury Inorganic materials 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical group [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 2
- 229910021334 nickel silicide Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 238000002791 soaking Methods 0.000 description 2
- WBYWAXJHAXSJNI-VOTSOKGWSA-M .beta-Phenylacrylic acid Natural products [O-]C(=O)\C=C\C1=CC=CC=C1 WBYWAXJHAXSJNI-VOTSOKGWSA-M 0.000 description 1
- WBYWAXJHAXSJNI-SREVYHEPSA-N Cinnamic acid Chemical compound OC(=O)\C=C/C1=CC=CC=C1 WBYWAXJHAXSJNI-SREVYHEPSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 description 1
- 229910003818 SiH2Cl2 Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 229930016911 cinnamic acid Natural products 0.000 description 1
- 235000013985 cinnamic acid Nutrition 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 125000002147 dimethylamino group Chemical group [H]C([H])([H])N(*)C([H])([H])[H] 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- WBYWAXJHAXSJNI-UHFFFAOYSA-N methyl p-hydroxycinnamate Natural products OC(=O)C=CC1=CC=CC=C1 WBYWAXJHAXSJNI-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 239000008096 xylene Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
Abstract
The present application provides a method of manufacturing a semiconductor device, including: providing a substrate, forming a grid laminated on the substrate, and respectively forming a source electrode and a drain electrode in the substrate at two sides of the grid; forming a mask layer covering the grid and the substrate; and etching the mask layer by using a first wet etching process to form an opening in the mask layer, wherein the opening exposes the top of the source electrode, the drain electrode and/or the grid electrode. According to the manufacturing method of the semiconductor device, the contact hole area is opened by using the wet etching process, and no plasma participates in the etching process, so that the plasma induced damage effect is improved.
Description
Technical Field
The present disclosure relates to semiconductor technologies, and particularly to a semiconductor device and a method for manufacturing the same.
Background
In the conventional sab (salicide block) process, plasma is usually used to etch and open a contact region, and then a subsequent process is performed, but the etching using plasma damages a gate oxide layer to deteriorate various electrical properties of the gate oxide layer, such as fixed charge density, interface state density, flat band voltage, leakage current, etc., of the gate oxide layer, which may cause a failure of a semiconductor device in a severe case. Therefore, it is desirable to provide an etching process that improves the plasma-induced damage effect while etching open the contact hole region.
Disclosure of Invention
In order to solve the above technical problems, the present application provides a semiconductor device and a method of manufacturing the same, which improves a plasma induced damage effect by opening a contact hole region using a wet etching process.
The present application provides a method of manufacturing a semiconductor device, the method comprising the steps of: providing a substrate, forming a grid laminated on the substrate, and respectively forming a source electrode and a drain electrode in the substrate at two sides of the grid; forming a mask layer covering the grid and the substrate; and etching the mask layer by using a first wet etching process to form an opening in the mask layer, wherein the opening exposes the top of the source electrode, the drain electrode and/or the grid electrode.
According to the manufacturing method of the semiconductor device, the contact hole area is opened by using the wet etching process, and no plasma participates in the etching process, so that the plasma induced damage effect is improved.
Drawings
In order to more clearly illustrate the technical solution of the present application, the drawings needed to be used in the embodiments will be briefly described below, and obviously, the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.
Fig. 2 is a sub-flowchart of step S103 in fig. 1.
Fig. 3 to 4 are schematic cross-sectional views of a semiconductor device corresponding to the method of fig. 2.
Fig. 5 is a schematic cross-sectional view of a semiconductor device after removing a protection layer according to an embodiment of the present application.
Fig. 6 is a schematic cross-sectional view of a semiconductor device after forming a dielectric layer according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without inventive step, are within the scope of the present disclosure.
In the description of the present application, the terms "first", "second", etc. are used for distinguishing different objects and not for describing a particular order, and further, the terms "upper", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings only for convenience of description and simplification of description, but do not indicate or imply that the referred device or element must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present application.
Throughout the description of the present application, unless expressly stated or limited otherwise, the term "coupled" is to be construed broadly, e.g., as meaning fixedly attached, detachably attached, or integrally attached; they may be connected directly or indirectly through intervening media, or may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
For purposes of clarity, the various features in the various drawings of the present application are not drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
In the conventional sab (salicide block) process, a dry etching process is generally used to etch and open a contact hole (contact) region, and the dry etching process uses plasma to etch, although the plasma is electrically neutral as a whole, the distribution of positive ions and electrons in the plasma is not uniform, and the positive ions and electrons actually entering the substrate are not equal in quantity, so that a large amount of free charges are generated, and the free charges are generatedCharges are easily collected by the gate oxide layer and accumulated on the surface thereof, and a large amount of CF is used in the etching process4、HBr、SF6The high electronegativity gases with strong insulation property make the release of the free charges difficult, and the charging effect of the free charges on the surface of the grid oxide layer is increased, and after the charges are accumulated to a certain degree, F-N current can be generated to damage the grid oxide layer, namely, a plasma induced damage effect is generated. The plasma induced damage effect degrades various electrical properties of the gate oxide layer, such as fixed charge density, interface state density, flat band voltage, leakage current, etc., in the gate oxide layer, which may cause failure of the semiconductor device in severe cases. Therefore, the application provides an etching process which can improve the plasma induced damage effect while opening the contact hole region by etching.
Referring to fig. 1, fig. 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. As shown in fig. 1, the method comprises the steps of:
s101: providing a substrate, forming a grid laminated on the substrate, and respectively forming a source electrode and a drain electrode in the substrate at two sides of the grid.
S102: and forming a mask layer covering the grid and the substrate.
S103: and etching the mask layer by using a first wet etching process to form an opening in the mask layer, wherein the opening exposes the top of the source electrode, the drain electrode and/or the grid electrode.
Wherein the opening exposing the top of the source, the drain and/or the gate comprises: the opening exposes at least one of the source, the drain, and a top of the gate.
Wherein the material of the substrate can be a semiconductor material, such as silicon; the mask layer is a silicon dioxide layer.
The grid comprises a grid oxide layer and a grid main body layer which are stacked, the grid oxide layer is formed on the surface of the substrate, and the grid main body layer is formed on the top surface of the grid oxide layer. In some embodiments, the gate oxide layer is a silicon dioxide layer and the gate body layer is a polysilicon layer.
In some embodiments, the mask layer is formed by chemical vapor deposition, for example, using a furnace process, a vertical furnace is used, and TEOS (tetraethylorthosilicate) and carrier N are introduced into the furnace2TEOS is decomposed to generate silicon dioxide which is uniformly deposited to cover the grid and the substrate; for example, a vertical furnace tube is used to introduce SiH into the furnace tube2Cl2And N2O，SiH2Cl2And N2Reaction of O to form SiO2、N2And HCl, SiO produced2Uniformly depositing and covering the grid and the substrate; for example, a vertical furnace tube is used to introduce SiH into the furnace tube4And N2O，SiH4And N2Reaction of O to form SiO2SiO produced2And uniformly depositing and covering the grid and the substrate.
In other embodiments, the mask layer is formed by furnace tube atomic layer deposition, and Si [ N (CH) is introduced into the furnace tube3)2]3H and O3，Si[N(CH3)2]3H and O3And reacting to generate silicon dioxide, and uniformly depositing the generated silicon dioxide to cover the grid and the substrate.
According to the manufacturing method of the semiconductor device, the contact hole area is opened by using the wet etching process, no plasma participates in the etching process, no free charge is generated, and the grid oxide layer is not damaged, so that the plasma induced damage effect can be improved.
Referring to fig. 2 to 4 together, fig. 2 is a sub-flowchart of step S103 in fig. 1 according to an embodiment of the present disclosure, and fig. 3 to 4 are cross-sectional views of a semiconductor device corresponding to the method in fig. 2. As shown in fig. 2, the step S103 specifically includes the following steps:
s1031: as shown in fig. 3, a protection layer 60 covering the mask layer 50 is formed, wherein the protection layer 60 forms an opening in a region corresponding to the top of the source 30, the drain 40 and/or the gate 20, so that the mask layer 50 covering the top of the source 30, the drain 40 and/or the gate 20 is exposed from the protection layer 60.
S1032: as shown in fig. 4, the exposed mask layer 50 is etched and removed by using a first wet etching process to form an opening in the mask layer 50, where the opening exposes the top of the source 30, the drain 40 and/or the gate 20.
The material of the protection layer 60 is a high viscosity photoresist, and the high viscosity photoresist is used to ensure that the photoresist is not corroded and damaged in the etching process of the first wet etching process, so that the mask layer 50 covered by the protection layer 60 can be protected from being etched in the etching process of the first wet etching process. Wherein the viscosity of the photoresist is greater than or equal to 2.0 cP.
Steps S1031 to S1032 are further specifically described below with reference to fig. 3 to 4:
referring to fig. 3, fig. 3 is a schematic cross-sectional view of the semiconductor device after step S1031. As shown in fig. 3, a protection layer 60 covering the mask layer 50 is formed, wherein the protection layer 60 forms an opening in a region corresponding to the top of the source 30, the drain 40 and/or the gate 20, so that the mask layer 50 covering the top of the source 30, the drain 40 and/or the gate 20 is exposed from the protection layer 60, wherein the protection layer 60 is a photoresist layer.
Specifically, in some embodiments, a photoresist layer is coated on the substrate 10, and the photoresist layer covers the mask layer 50; a mask plate is arranged right above the photoresist layer, the mask plate comprises a base plate and a chromium layer which are arranged in a stacked mode, and the chromium layer is located on one side, close to the photoresist layer, of the mask plate and located above the substrate 10 except for the source electrode 30, the drain electrode 40 and/or the grid electrode 20; exposing the photoresist layer corresponding to the tops of the source electrode 30, the drain electrode 40 and/or the gate electrode 20 using a light source or a radiation source, for example, a mercury lamp or an electron beam, an ion beam, etc.; and dissolving and removing the exposed photoresist layer by using a developing solution, and forming an opening in the region of the photoresist layer corresponding to the top of the source electrode, the drain electrode and/or the grid electrode, so that the mask layer covering the top of the source electrode, the drain electrode and/or the grid electrode is exposed from the protective layer. Wherein the substrate material may be quartz; the developer may be TMAH (tetramethylammonium hydroxide); the photoresist may be a mixture of a DNQ (diazonaphthoquinone) -based compound and a phenol resin.
In some other embodiments, the method of forming the protection layer 60 specifically includes: coating a photoresist layer on the substrate 10, wherein the photoresist layer covers the mask layer 50 completely; a mask plate is arranged right above the photoresist layer, the mask plate comprises a substrate and a chromium layer which are arranged in a stacked mode, and the chromium layer is located on one side, close to the photoresist layer, of the mask plate and is located right above the source electrode 30, the drain electrode 40 and/or the grid electrode 20; exposing the photoresist layer corresponding to the region of the substrate 10 except the source electrode 30, the drain electrode 40 and/or the gate electrode 20 using a light source or a radiation source, for example, a mercury lamp or an electron beam, an ion beam, etc.; and dissolving and removing the unexposed photoresist layer by using a developing solution, and forming an opening in the region of the photoresist layer corresponding to the top of the source electrode, the drain electrode and/or the grid electrode, so that the mask layer covering the top of the source electrode, the drain electrode and/or the grid electrode is exposed from the protective layer. Wherein the substrate material may be quartz; the developer may be xylene; the photoresist may be a poly (cinnamic acid) compound.
Referring to fig. 4, fig. 4 is a schematic cross-sectional view of the semiconductor device after step S1032. As shown in fig. 4, the exposed mask layer 50 is removed by etching using a first wet etching process to form an opening in the mask layer 50, where the opening exposes the top of the source 30, the drain 40 and/or the gate 20. Wherein the removing the exposed mask layer 50 by etching using the first wet etching process includes: the exposed mask layer 50 is etched and removed using a hydrofluoric acid solution. Specifically, a wet groove type processing machine table is used for etching, and the wet groove type processing machine table comprises a first etching groove, a first circulating pipeline, a first filter, a first heater, a first cooler, a first temperature sensor and a processor. An outlet and an inlet of the first circulating pipeline are respectively connected with two sides of the first etching groove to form a closed flow path, a hydrofluoric acid solution is arranged in the closed flow path, and the hydrofluoric acid solution flows in the closed flow path at a constant speed, so that the concentration of the hydrofluoric acid solution in each area of the first etching groove is kept consistent in the etching process; the first filter is respectively connected with the outlet of the first circulating pipeline and the first etching groove, is positioned between the outlet of the first circulating pipeline and the first etching groove, and is used for filtering impurities in the hydrofluoric acid solution flowing out of the outlet of the first circulating pipeline and preventing the impurities from entering the first etching groove so as to avoid influencing the etching effect of the hydrofluoric acid solution in the first etching groove and avoid polluting a semiconductor device in the first etching groove; the first heater and the first cooler are respectively connected with the first etching groove and are respectively used for heating and cooling the first etching groove; the first temperature sensor is positioned in the first etching groove and used for detecting the temperature of the hydrofluoric acid solution in the first etching groove.
Soaking the semiconductor device in the first etching tank filled with the hydrofluoric acid solution, and setting the etching time T1And within a first preset etching temperature range, selectively etching the exposed mask layer 50 by the hydrofluoric acid solution to form an opening in the mask layer 50, wherein the opening exposes the top of the source electrode 30, the drain electrode 40 and/or the gate electrode 20.
In the process of etching the exposed mask layer 50, the first temperature sensor may detect the temperature of the hydrofluoric acid solution in the first etching groove in real time and feed back the detected temperature of the hydrofluoric acid solution in the first etching groove to the processor, and when the detected temperature of the hydrofluoric acid solution in the first etching groove is outside the first preset etching temperature range, the processor controls the first heater to heat the first etching groove or controls the first cooler to cool the first etching groove, so that the temperature of the hydrofluoric acid solution in the first etching groove detected by the first temperature sensor is within the first preset etching temperature range, and the stability of the etching temperature is maintained, thereby maintaining the stable etching efficiency.
The hydrofluoric acid solution is prepared by mixing hydrofluoric acid (40 wt%) and deionized water according to a volume ratio of 1: 90-1: 110; the first preset etching temperature range is 22-24 ℃; etching time T1Can be based on the etching rate V1And the dimension A of the exposed mask layer 50 in the direction perpendicular to the substrate 101Is calculated to obtain, wherein, T1＝A1/V1For example, the etching rate V1Is 2nm/min, the dimension A of the exposed mask layer 50 in the direction perpendicular to the substrate 10110nm, the etching time T1It is 5 min. Wherein a dimension A of the mask layer 50 in a direction perpendicular to the substrate 101Can be measured by a film thickness measuring instrument, such as an X-ray film thickness measuring instrument, an ellipsometer, a spectroscopic interference type film thickness measuring instrument, and the like; the etching rate V1It can be found through experiments that, specifically, the dimension a of the exposed mask layer 50 in the direction perpendicular to the substrate is measured by using the film thickness measuring instrumentx(ii) a The exposed mask layer 50 is etched by using the wet groove type processing machine, and the shorter etching time T is setsRemoving portions of the exposed masking layer 50; after etching, the dimension a of the exposed mask layer 50 in the direction perpendicular to the substrate 1 is measured by using the film thickness measuring instrumenty(ii) a According to V1＝(Ax-Ay)/TsCalculating to obtain the etching rate V1。
Referring to fig. 5, fig. 5 is a schematic cross-sectional view of the semiconductor device after the protective layer 60 is removed according to the embodiment of the present disclosure. After step S1032, the method further includes the step of: the protective layer 60 is etched away using a second wet etch process. The etching and removing the protective layer 60 by using the second wet etching process includes: and etching and removing the protective layer 60 by using a mixed solution of concentrated sulfuric acid and hydrogen peroxide. Wherein the protective layer 60 is a photoresist layer. Specifically, the wet groove type processing machine table is used for etching, and the wet groove type processing machine table further comprises a second etching groove, a second circulating pipeline, a second filter, a second heater, a second cooler, a second temperature sensor and a processor. The outlet and the inlet of the second circulating pipeline are respectively connected with two sides of the second etching tank to form a closed flow path, a mixed solution of sulfuric acid and hydrogen peroxide is filled in the closed flow path, and the mixed solution flows at a constant speed in the closed flow path, so that the concentration of the mixed solution in each area of the second etching tank is kept consistent in the etching process; the second filter is respectively connected with the outlet of the second circulating pipeline and the second etching groove, is positioned between the outlet of the second circulating pipeline and the second etching groove, and is used for filtering impurities in the mixed solution flowing out of the outlet of the second circulating pipeline and preventing the impurities from entering the second etching groove so as to avoid influencing the etching effect of the mixed solution in the second etching groove and avoid polluting a semiconductor device in the second etching groove; the second heater and the second cooler are respectively connected with the second etching groove and are respectively used for heating and cooling the second etching groove; the second temperature sensor is positioned in the second etching groove and used for detecting the temperature of the mixed solution in the second etching groove.
Soaking the semiconductor device in the second etching tank filled with the mixed solution, and setting the etching time T2And a second predetermined etching temperature range, the mixed solution selectively etches and removes the protective layer 60.
In the process of removing the protective layer 60 by etching, the second temperature sensor may detect the temperature of the mixed solution in the second etching tank in real time and feed back the detected temperature of the mixed solution in the second etching tank to the processor, and when the detected temperature of the mixed solution in the second etching tank is outside the second preset etching temperature range, the processor controls the second heater to heat the second etching tank or controls the second cooler to cool the second etching tank, so that the temperature of the mixed solution in the second etching tank detected by the second temperature sensor is within the second preset etching temperature range, and the stability of the etching temperature is maintained, thereby maintaining the stable etching efficiency.
Wherein the mixed solution is prepared by mixing concentrated sulfuric acid (98 wt%) and hydrogen peroxide (30 wt%) according to a volume ratio of 3: 1-5: 1; the second preset etching temperature range is 100-150 ℃; etching time T2Can be based on the etching rate V2A dimension A of the protective layer 60 in a direction perpendicular to the substrate 102Is calculated to obtain, wherein, T2＝A2/V2For example, the etching rate V2A dimension A of the protective layer 60 in a direction perpendicular to the substrate 10 of 2nm/min210nm, the etching time T2It is 5 min. Wherein a dimension A of the protective layer 60 in a direction perpendicular to the substrate 102Can be measured by a film thickness measuring instrument, such as an X-ray film thickness measuring instrument, an ellipsometer, a spectroscopic interference type film thickness measuring instrument, and the like; the etching rate V2It can be found through experiments that, specifically, the dimension A of the protective layer 60 along the direction perpendicular to the substrate 10 is measured by using the film thickness measuring instrumentm(ii) a The protective layer 60 is etched by using the wet groove type processing machine, and the shorter etching time T is setqSo that portions of the protective layer 60 are removed; after etching, the dimension A of the protective layer 60 in the direction perpendicular to the substrate 10 was measured using the film thickness measuring instrumentn(ii) a According to V2＝(Am-An)/TqCalculating to obtain the etching rate V2。
The etching process is carried out at a high temperature, for example, 100-150 ℃, and the hydrogen peroxide in the hydrogen peroxide is lost due to decomposition into water and hydrogen in the etching process, so that the etching rate of the mixed solution is reduced. The wet groove type processing machine table further comprises a hydrogen peroxide compensation device, the hydrogen peroxide compensation device can detect the concentration of hydrogen peroxide in the second etching groove in real time, when the concentration of the hydrogen peroxide in the second etching groove is lower than a preset hydrogen peroxide concentration range, the detected concentration of the hydrogen peroxide in the second etching groove is fed back to the processor, and the processor controls the hydrogen peroxide compensation device to add a certain amount of hydrogen peroxide into the second etching groove, so that the detected concentration of the hydrogen peroxide in the second etching groove is in the preset hydrogen peroxide concentration range, the concentration of the hydrogen peroxide in the second etching groove is kept stable, and the stability of the etching rate of the mixed solution can be kept.
In some embodiments, after the protective layer 60 is removed by etching using a mixed solution of concentrated sulfuric acid and hydrogen peroxide, the semiconductor device is also cleaned using a cleaning solution to remove impurities such as particles on the surface of the semiconductor device. Specifically, the wet groove type processing machine is used for etching, and further comprises a cleaning groove, a third circulating pipeline, a third filter, a third heater, a third cooler, a third temperature sensor and a processor. An outlet and an inlet of the third circulating pipeline are respectively connected with two sides of the cleaning tank to form a closed flow path, cleaning liquid is filled in the closed flow path, and the cleaning liquid flows in the closed flow path at a constant speed, so that the concentration of the cleaning liquid in each area of the cleaning tank is kept consistent in the etching process; the third filter is connected with the outlet of the third circulating pipeline and the cleaning tank respectively, is positioned between the outlet of the third circulating pipeline and the cleaning tank, and is used for filtering impurities in the cleaning liquid flowing out of the outlet of the third circulating pipeline and preventing the impurities from entering the cleaning tank so as to avoid influencing the etching effect of the cleaning liquid in the cleaning tank and avoid polluting the semiconductor devices in the cleaning tank; the third heater and the third cooler are respectively connected with the cleaning tank and are respectively used for heating and cooling the cleaning tank; the third temperature sensor is located in the cleaning tank and used for detecting the temperature of the cleaning liquid in the cleaning tank.
Immersing the semiconductor device in the cleaning tank filled with the cleaning solution for a cleaning time T3And presetting a cleaning temperature range, and removing impurities such as particles on the surface of the semiconductor device by using the cleaning liquid.
Wherein, in the process of cleaning the semiconductor device, the third temperature sensor can detect the temperature of the cleaning solution in the cleaning tank in real time and feed back the detected temperature of the cleaning solution in the cleaning tank to the processor, and when the detected temperature of the cleaning solution in the cleaning tank is out of the preset cleaning temperature range, the processor controls the third heater to heat the cleaning tank or controls the third cooler to cool the cleaning tank, so that the temperature of the cleaning solution in the cleaning tank detected by the third temperature sensor is within the preset cleaning temperature range, and a stable cleaning temperature is maintained, thereby maintaining stable cleaning efficiency.
The cleaning solution can be a mixed solution of ammonium hydroxide, hydrogen peroxide and deionized water, and the cleaning solution can be prepared from ammonium hydroxide (27 wt%), hydrogen peroxide (30 wt%) and deionized water according to a volume ratio of 1:1: 5-1: 2: 7; preferably, said washing time T3Is 10 minutes; the preset cleaning temperature range is 30-40 ℃.
Further, after the protective layer 60 is removed by etching using the mixed solution of concentrated sulfuric acid and hydrogen peroxide, the method further includes the steps of: and forming a dielectric layer covering the top of the source electrode, the drain electrode and/or the grid electrode, wherein the dielectric layer is made of silicide. Preferably, the silicide is nickel silicide. Specifically, referring to fig. 6, fig. 6 is a schematic cross-sectional view of the semiconductor device after forming a dielectric layer, as shown in fig. 6, in some embodiments, the material of the substrate 10 is silicon, the gate body layer is a polysilicon layer, the dielectric layer 70 is formed by a chemical vapor deposition method, for example, a NiPt layer is deposited on the surface of the source 30, the surface of the drain 40 and/or the top of the gate 20, and a nickel silicide is respectively formed by reacting the NiPt with the silicon on the surface of the source 30, the surface of the drain 40 and/or the top of the gate 20 through an RTP (rapid thermal processing) process.
To sum up, the semiconductor device manufacturing method provided by the embodiment of the present application uses a hydrofluoric acid solution to etch the mask layer 50, the hydrofluoric acid solution can react with the mask layer 50, the product generated by the reaction can be dissolved in an aqueous solution to be removed, so as to form an opening in the mask layer 50 to expose the top of the source, the drain and/or the gate, and the photoresist is etched by using a mixed solution of concentrated sulfuric acid and hydrogen peroxide, the mixed solution of concentrated sulfuric acid and hydrogen peroxide can react with the photoresist, the product generated by the reaction can also be dissolved in an aqueous solution to remove the photoresist, thereby improving the plasma induced damage effect while opening the contact hole region.
The foregoing is an implementation of the embodiments of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the embodiments of the present application, and these modifications and decorations are also regarded as the protection scope of the present application.
Claims (10)
1. A method of manufacturing a semiconductor device, the method comprising the steps of:
providing a substrate, forming a grid laminated on the substrate, and respectively forming a source electrode and a drain electrode in the substrate at two sides of the grid;
forming a mask layer covering the grid and the substrate; and
and etching the mask layer by using a first wet etching process to form an opening in the mask layer, wherein the opening exposes the top of the source electrode, the drain electrode and/or the grid electrode.
2. The method of claim 1, wherein the etching the mask layer using a first wet etch process to form an opening in the mask layer, the opening exposing a top of the source, the drain, and/or the gate, comprises:
forming a protective layer covering the mask layer, wherein an opening is formed in the protective layer in a region corresponding to the top of the source electrode, the drain electrode and/or the grid electrode, so that the mask layer covering the top of the source electrode, the drain electrode and/or the grid electrode is exposed from the protective layer;
and etching and removing the exposed mask layer by using a first wet etching process to form an opening in the mask layer, wherein the opening exposes the top of the source electrode, the drain electrode and/or the grid electrode.
3. The method of claim 2, wherein after the etching away the exposed mask layer using the first wet etching process to form an opening in the mask layer, the opening exposing a top of the source, the drain, and/or the gate, the method further comprises:
and etching and removing the protective layer by using a second wet etching process.
4. The method of claim 2, wherein the etching away the exposed mask layer using a first wet etching process to form an opening in the mask layer, the opening exposing a top of the source, the drain, and/or the gate comprises:
and etching and removing the exposed mask layer by using hydrofluoric acid solution to form an opening in the mask layer, wherein the opening exposes the top of the source electrode, the drain electrode and/or the grid electrode.
5. The method of claim 3, wherein the etching away the protective layer using a second wet etch process comprises:
and etching and removing the protective layer by using a mixed solution of concentrated sulfuric acid and hydrogen peroxide.
6. The method according to claim 4, wherein the hydrofluoric acid solution is a mixed solution of hydrofluoric acid and deionized water, and the volume ratio of the hydrofluoric acid to the deionized water is between 1:90 and 1: 110.
7. The method according to claim 5, wherein the volume ratio of concentrated sulfuric acid to hydrogen peroxide in the mixed solution is 3: 1-5: 1.
8. The method of claim 1, wherein the material of the mask layer is silicon dioxide.
9. The method of claim 2, wherein the protective layer is made of a high viscosity photoresist.
10. The method according to claim 5, wherein after the etching removal of the protective layer by using the mixed solution of concentrated sulfuric acid and hydrogen peroxide, the method further comprises:
and forming a dielectric layer covering the top of the source electrode, the drain electrode and/or the grid electrode, wherein the dielectric layer is made of silicide.
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