CN113096212B - Splitting verification method and system for TPT layout and memory - Google Patents
Splitting verification method and system for TPT layout and memory Download PDFInfo
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Abstract
The invention discloses a method, a system and a memory for verifying the splitting of a TPT layout, wherein the method comprises the following steps: step S1: constructing an abstract diagram according to the original layout; step S2: reconstructing the abstract image by adopting a vertex degree reconstruction method; step S3: if the delta (G) is less than or equal to 2, judging that the layout can be split, otherwise, executing a step S4, wherein the delta (G) is the maximum vertex degree of the reconstructed abstract diagram; step S4: performing color reduction treatment on the reconstructed abstract image; step S5: and sequentially judging the color numbers of the nodes after the color reduction treatment, if no node with the color number of 4 exists, judging that the layout can be split, otherwise, judging that the layout cannot be split. By adopting the technical scheme of the invention, the speed for verifying whether the TPT layout can be split can be improved.
Description
Technical Field
The invention relates to the field of verification of physical design rules of integrated circuits, in particular to a method, a system and a memory for verifying splitting of a TPT layout.
Background
Due to the limitations of many factors of lithography (new light sources, lithography lenses, photoresists), the minimum feature size that can be achieved with a single reticle has reached its limit. Following moore's law, Triple Patterning Technology (hereinafter referred to as TPT) is the most practical lithography process for a long time in the future in order to meet the requirements of smaller feature size and increasing performance of chips. With the continuous increase and the increasing complexity of the design scale, the requirements on the speed and the accuracy of completing the layout splitting of the EDA tool are higher and higher, and the research of a more efficient algorithm becomes necessary.
For layout splitting, from the mathematical perspective, the TPT layout splitting can be solved as the vertex coloring problem in the graph theory, and belongs to an NP-hard problem. The symbolic study of such problems is the well-known "four-color theorem", which is simple, in terms of coloring a planar map, two arbitrary countries with common boundaries can be different in color only by four colors, and any two graphs with a distance smaller than the minimum process dimension Xmin in a layout cannot be distributed on the same layout, which is equivalent to that adjacent countries cannot be labeled with the same color. Meanwhile, the requirements and the limitations of the layout during actual drawing are considered, and the abstract Graph (Graph) abstracted from the layout in the TPT layout splitting completely belongs to the range of the research object of the 'four-color theorem'.
In the TPT layout splitting process, an actual layout is converted into an abstract diagram, whether the layout can be reasonably split or not is verified by verifying whether the vertex coloring can be completed by using three colors or not, and the main used methods can be divided into three types, namely mathematical programming, a graph theory method and a heuristic algorithm. The mathematical programming comprises ILP, SDP and LP; the graph theory method comprises a maximum independent set MIS, a shortest path method and an FPT; and the heuristic algorithm belongs to an algorithm constructed based on intuition or experience, and finally realizes the full-play optimal solution by locally searching the optimal solution, so that the quality of the final solution is difficult to ensure, and the related application is less. At present, the most common algorithms for realizing Triple Pattern (hereinafter abbreviated as TP) splitting are ILP algorithm and SDP algorithm, wherein SDP has a relatively high speed in high-density layout. However, as the number of conflicts in the layout increases and the number of dividing lines to be inserted for solving the conflicts increases, the time for solving the algorithms increases sharply, and although the time consumption becomes linear by adjusting the complexity of the algorithms, the required storage and operation space becomes huge, which is equivalent to the reduction of time consumption in exchange for space consumption.
Disclosure of Invention
The invention aims to solve the technical problem that in the prior art, when the TPT layout can be verified to be split, the algorithm is complex and the solving time is long, and provides a method, a system and a memory for verifying the splitting of the TPT layout.
The embodiment of the invention provides a splitting verification method of a TPT layout, which comprises the following steps:
step S1: constructing an abstract diagram according to the original layout;
step S2: reconstructing the abstract image by adopting a vertex reconstruction method: according to the vertex degree of each node in the abstract graph and the sequence detected in the abstract graph, the node labels of the nodes are reset in sequence, and each node is colored into a color number equal to the node label;
step S3: if the delta (G) is less than or equal to 2, judging that the layout can be split, otherwise, executing a step S4, wherein the delta (G) is the maximum vertex degree of the reconstructed abstract diagram;
step S4: and (3) performing color reduction treatment on the reconstructed abstract image: sequentially starting from the node with the node label 2 until the node with the maximum node label, and adjusting the color number of each node to be the minimum value unequal to the color number of the adjacent node;
step S5: and sequentially judging the color numbers of the nodes after the color reduction treatment, if no node with the color number of 4 exists, judging that the layout can be split, otherwise, judging that the layout cannot be split.
In the embodiment of the present invention, the resetting of the node labels of the nodes according to the vertex degrees of the nodes in the abstract diagram and the detected sequence in the abstract diagram includes:
firstly, sorting according to the size of the vertex degree of each node in the abstract graph, and arranging the nodes with large vertex degrees in front;
and when the node degrees are equal in size, the node with the front detection sequence in the abstract graph is arranged in front.
In the embodiment of the invention, the abstract diagram is constructed according to the original layout, and the method comprises the following steps:
and marking the nodes of the abstract graph in sequence according to the sequence detected in the layout.
The embodiment of the invention also provides a splitting verification system of the TPT layout, which adopts the splitting verification method of the TPT layout when judging whether the TPT layout can be split.
The embodiment of the invention also provides a memory, wherein a computer program is stored in the memory, and when the computer program is run by a processor, the splitting verification method of the TPT layout is executed.
Compared with the prior art, the splitting verification method and the system for the TPT layout only need to search the vertex degrees of the relevant nodes in the abstract graph to complete the color reduction processing of the corresponding nodes, which is equivalent to completing the distribution of the graph on the photoetching layout while verifying whether the layout can be split, greatly quickening the operation speed and saving the time required by verifying the layout; in addition, in the graph vertex coloring problem, nodes with large edge degrees are often connected with more nodes, if the nodes are used as the final coloring nodes, the situation that the required color number is increased is more easily caused, and the quality of the final solution is difficult to guarantee.
Drawings
Fig. 1 is a flowchart of a splitting verification method of a TPT layout according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of an original layout model according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of an abstract diagram according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a reconstructed and colored abstract diagram according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of the reconstructed abstract diagram after color reduction processing according to the embodiment of the present invention.
FIG. 6 is a schematic diagram showing the distribution of the patterns on the original layout after the original layout is split on the three-layered photolithography mask.
Detailed Description
The invention provides a splitting verification method of a TPT layout.
When the TPT layout is split, the graphs with the space smaller than the minimum process dimension Xmin in the original layout are required to be split on three layers of different layouts to complete photoetching. In the process, the specific situation that the pattern itself is different from the pattern itself and the adjacent patterns are different from each other is not considered, including the number of the parts with the distance between the two same patterns being smaller than the minimum process size. Therefore, the invention represents the related situation of the layout by the simple graph studied in the graph theory. Such a simple graph refers to a simple graph studied in the "four-color guess" theorem, in which neither a ring nor a heavy edge exists, where the ring is an edge in which the start node and the end node are the same node, and is equivalent to the distance between the graph itself and itself being less than Xmin, and the heavy edge refers to the non-unique edge existing between the same two nodes, that is, the distance between multiple positions existing between the graph and itself being less than Xmin. In a simple graph, one node can completely represent the corresponding graph in the layout, and the edge between the nodes represents that the distance between the two corresponding graphs in the layout is less than Xmin.
The vertexes in the graph are colored, so that the colors of the adjacent vertexes are different, and after the integral dyeing of the graph is finally completed, whether the graph can be split or not is judged by judging whether the vertexes in the graph have color numbers of 4 or not.
Parameters χ (G) = min { k: dot k dyeable in graph G } is referred to as the dot color number for G, simply the color number. For any simple graph G, χ (G). ltoreq.Δ (G) + 1; where Δ (G) is the maximum vertex degree. The vertex degrees refer to the number of edges connected with the same node, and the maximum vertex degree is the maximum value of the vertex degrees of all the nodes in the graph. The TPT technique uses a triple lithography mask, so that if the color number χ (G) ≦ 3 of the graph G, which is equivalent to the maximum vertex angle Δ (G) ≦ 2 of the graph G, the original graph can be necessarily split.
Specifically, as shown in fig. 1, the split verification method for the TPT layout of the present invention includes steps S1-S5. The following description will be made separately.
Step S1: and constructing an abstract map according to the original layout.
And receiving an original layout, and scanning related conditions of the layout to construct an abstract Graph (Graph) G, wherein the abstract Graph G belongs to the simple Graph of the four-color theorem research. The original layout is shown in FIG. 2 in the drawing, and the abstract graph G constructed according to the layout situation in FIG. 2 is shown in FIG. 3. In fig. 3, each node represents a graph in the original layout, and is sequentially labeled as V1 and V2 … … V13 according to the sequence detected in the original layout, and the Edge between nodes indicates that the distance between the corresponding graphs is smaller than Xmin.
Step S2: and reconstructing the abstract image by adopting a vertex reconstruction method.
It should be noted that, in order to accelerate the algorithm and ensure the final decomposition quality, the abstract graph G is reconstructed using a vertex reconstruction method. And the vertex degree reconstruction method is to reset the node labels of the nodes in sequence according to the vertex degrees of the nodes in the abstract graph and the detected sequence in the abstract graph, and color each node into a color number equal to the node label. The rule for resetting the node labels of the nodes is as follows: firstly, sorting according to the size of the vertex degree of each node in the abstract graph, and arranging the nodes with large vertex degrees in front; and when the node degrees are equal in size, the node with the front detection sequence in the abstract graph is arranged in front.
The maximum value of the vertex degree in the initial abstract graph in fig. 3 is 4, the related nodes are V2, V3, V6, V9 and V11 according to the detected order, and the nodes are changed into V1, V2, V3, V4 and V5 in the newly constructed abstract graph. Then, the labels of the remaining nodes are sorted according to the method, and finally, the newly constructed abstract graph is colored to have the color numbers equal to the labels of the nodes, for example, the color number of the node V1 is 1, and the color number of the node V13 is 13, and finally, the abstract graph G reconstructed by using the vertex degree reconstruction method for the abstract graph G in fig. 3 is shown in fig. 4. In the link, all nodes are colored to be equal to the color numbers of the nodes, which is equivalent to splitting each graph in the original layout into an independent mask.
Step S3: if the delta (G) is less than or equal to 2, judging that the layout can be split, otherwise executing a step S4, wherein the delta (G) is the maximum top degree of the reconstructed abstract graph.
Step S4: and performing color reduction treatment on the reconstructed abstract image.
In this step, the specific rule of the color reduction processing is as follows: and sequentially starting from the node with the node label of 2 to the node with the maximum node label, and adjusting the color number of each node to be the minimum value unequal to the color number of the adjacent node. Specifically, as shown in the abstract diagram of fig. 4, since the node V1 has an initial color number of 1, V2 is adjacent to V1 and V6 from the node V2, and the color numbers corresponding to V1 and V6 are 1 and 6, respectively, the color number of V2 can only be the minimum value 2 different from 1 and 6, and no change is required. V3 is connected with V1, V2, V8 and V11, and the corresponding color numbers of the nodes are 1, 2, 8 and 11, so that the color number of the node V3 can only be 3. The node V4 is adjacent to V5, V7, V9 and V12, the corresponding color numbers of the nodes are 5, 7, 9 and 12, the minimum value different from the color numbers is 1, so the color number of the node V4 can be reduced to 1. The node V5 is adjacent to V4, V8, V9 and V13, the corresponding color numbers of the nodes are 1, 8, 9 and 13, the minimum value different from the color numbers is 2, so the color number of the node V4 can be reduced to 2. By analogy, after the color reduction of the node with the maximum node label is completed, the color number of the corresponding node after the color reduction is distributed as shown in fig. 5.
Step S5: and sequentially judging the color numbers of the nodes after the color reduction treatment, if no node with the color number of 4 exists, judging that the layout can be split, otherwise, judging that the layout cannot be split.
FIG. 6 shows the distribution of the patterns on the original layout after the original layout is split on the three-layer photolithography mask. As can be seen from fig. 6, for a layout without a color number greater than 4, that is, the maximum value of the color number is 3, the nodes of each color number may be respectively set in one layer of the three-layer photolithography masks (mask 1, mask2, mask 3), thereby completing the splitting.
The embodiment of the invention also provides a splitting verification system of the TPT layout, which adopts the splitting verification method of the TPT layout when judging whether the TPT layout can be split.
Further, in an embodiment of the present invention, a memory is further provided, where a computer program is stored in the memory, and when the computer program is executed by a processor, the splitting verification method for the TPT layout is executed.
In summary, by using the method and system for verifying splitting of the TPT layout, the color reduction processing of the corresponding node is completed only by searching the vertex degrees of the relevant nodes in the abstract map, which is equivalent to completing the distribution of the graph on the photoetching layout while verifying whether the layout can be split, thereby greatly accelerating the operation speed and saving the time required for verifying the layout; in addition, in the graph vertex coloring problem, nodes with large edge degrees are often connected with more nodes, if the nodes are used as the final coloring nodes, the situation that the required color number is increased is more easily caused, and the quality of the final solution is difficult to guarantee.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (5)
1. A splitting verification method for a TPT layout is characterized by comprising the following steps:
step S1: constructing an abstract diagram according to the original layout;
step S2: reconstructing the abstract image by adopting a vertex reconstruction method: according to the vertex degree of each node in the abstract graph and the sequence detected in the abstract graph, the node labels of the nodes are reset in sequence, and each node is colored into a color number equal to the node label;
step S3: if the delta (G) is less than or equal to 2, judging that the layout can be split, otherwise, executing a step S4, wherein the delta (G) is the maximum vertex degree of the reconstructed abstract diagram;
step S4: and (3) performing color reduction treatment on the reconstructed abstract image: sequentially starting from the node with the node label 2 until the node with the maximum node label, and adjusting the color number of each node to be the minimum value unequal to the color number of the adjacent node;
step S5: and sequentially judging the color numbers of the nodes after the color reduction treatment, if no node with the color number of 4 exists, judging that the layout can be split, otherwise, judging that the layout cannot be split.
2. The method for verifying the splitting of the TPT layout according to claim 1, wherein the step of resetting the node labels of the nodes according to the vertex degrees of the nodes in the abstract diagram and the detected sequence in the abstract diagram comprises:
firstly, sorting according to the vertex degree of each node in the abstract graph, and arranging the nodes with the large vertex degrees in front;
and when the node degrees are equal in size, the node with the front detection sequence in the abstract graph is arranged in front.
3. The method for verifying the splitting of the TPT layout according to claim 1, wherein the constructing of the abstract diagram according to the original layout comprises:
and marking the nodes of the abstract graph in sequence according to the sequence detected in the layout.
4. A splitting verification system of TPT layout is characterized in that when judging whether the TPT layout can be split or not, the splitting verification method of TPT layout according to any one of claims 1-3 is adopted.
5. A memory in which a computer program is stored which, when executed by a processor, performs a method of split verification of a TPT layout as claimed in any one of claims 1 to 3.
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| US9514266B2 (en) * | 2014-08-28 | 2016-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and system of determining colorability of a layout |
| US10395001B2 (en) * | 2015-11-25 | 2019-08-27 | Synopsys, Inc. | Multiple patterning layout decomposition considering complex coloring rules |
| US9996657B2 (en) * | 2016-07-28 | 2018-06-12 | Taiwan Semiconductor Manufacturing Company Limited | Systems and methods for generating a multiple patterning lithography compliant integrated circuit layout |
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| CN104346490A (en) * | 2013-08-09 | 2015-02-11 | 复旦大学 | Graph pattern decomposition method adopting triple patterning photoetching technology |
| US9026971B1 (en) * | 2014-01-07 | 2015-05-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-patterning conflict free integrated circuit design |
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| "A High-Performance Triple Patterning Layout Decomposer with Balanced Density";Bei Yu等;《2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)》;20131223;163-169 * |
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