CN113094319B - System and method for synchronously controlling one-way data transmission between two hosts - Google Patents
System and method for synchronously controlling one-way data transmission between two hosts Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
The invention discloses a system and a method for synchronously controlling one-way data transmission between two hosts, wherein the system comprises a first singlechip and a second singlechip, wherein the first singlechip is connected with a data receiving host through a USB interface and a USB line; the two singlechips are connected through a data transmission line; when the system is initialized, the two single-chip microcomputers are synchronously initialized through the reverse control signal line to determine the upper limit of the writing speed of data packet transmission, so that the data transmission host and the data receiving host can be ensured to be synchronous in transmission and reception while the complete unidirectional transmission of data is realized. On the basis of ensuring data synchronization, unidirectional data transmission capable of correcting errors is easier to realize between a data transmitter and a receiver.
Description
Technical Field
The invention belongs to the technical field of information security, relates to data unidirectional transmission, and particularly relates to unidirectional data transmission synchronization and data content error control between two hosts.
Background
With the continuous development of internet technology, computer networks play more and more important roles in various fields in people's social life, and the dependence of people on computer networks is increasingly deepened. The wide application of network technology enables information exchange and sharing among computers. However, in some specific application environments, the exchange and sharing of data over a network needs to comply with special regulations: for computer systems in a security domain at a certain level of privacy, one-way data transfer is an important part of computer network security. Secure unidirectional data transmission requires that data be transmitted without reverse signaling.
At present, unidirectional data transmission is mainly applied between two hosts, namely a sending end host and a receiving end host, and the unidirectional data transmission limiting condition ensures that the synchronization of data transmission and data content error control cannot be realized by a mechanism of sending-receiving-confirming during unidirectional data transmission, which causes the problems such as poor image display quality and the like; therefore, synchronization and error control of data transmission and reception sides in unidirectional data transmission are a crucial issue that hinders the development of unidirectional data transmission in the field of information security. The completely unidirectional data transmission channel does not allow a signal transmission channel or line from the data receiving side to the data sending side during data transmission. Generally, a speed synchronization mechanism between a data sending party and a data receiving party is needed for correct data transmission, a retransmission mechanism of a missing packet and an error packet is needed, such synchronization and error control are needed, a data receiving party feeds back a received data packet condition to the data sending party, and the sending party controls the sending speed or resends some data packets according to feedback information. However, the completely unidirectional data transmission channel does not allow a signal feedback channel or line from the data receiving side to the data transmitting side during data transmission. Thus, for each data transmission, the data sender cannot know whether the data receiver successfully receives the data, and cannot ensure whether the data in front is covered by the data in the back because the data is not read in time by the receiver. In addition, the data sender cannot know whether the data has errors in the transmission process and needs to be retransmitted.
The USB interface is a commonly deployed computer I/O interface. The one-way data transmission channel is realized by utilizing the USB interface, and the USB interface has the advantages of convenience and high cost performance. CN107517222A discloses a unidirectional transmission device and method based on USB interface, the unidirectional transmission device based on USB interface includes a first main control chip and a second main control chip with model number USB3380, the USB interface of the first main control chip is connected with the USB interface of the sending host, the USB interface of the second main control chip is connected with the USB interface of the receiving host, and the first main control chip and the second main control chip are bridged by PCI-Express interface. The first main control chip and the second main control chip are configured to be capable of transmitting data to the second main control chip only in a one-way mode, and the configuration of the environmental parameters of the first main control chip and the second main control chip comprises the setting of a register of a relevant working mode, the allocation and initialization of a sending and receiving buffer area, the initialization of a data receiving address and the establishment of a USB interface transceiving condition. According to the one-way transmission device based on the USB interface, the received USB commands are disassembled and analyzed one by one through the main control chip, all data information is blocked from flowing back, communication handshake is cut off from the bottommost layer, one-way transmission without feedback is formed, and physical isolation is achieved. However, if the data receiving speed of the receiving host is lower than that of the sending host, the above-indicated sending host and receiving host are difficult to realize the sending and receiving synchronization, so that the data loss is easily caused; meanwhile, the technology does not consider how to realize error correction when data transmission errors occur in the transmission process.
In summary, in the process of unidirectional data transmission, it is of great application significance to modify the original USB interface for bidirectional communication into a data transmission channel with synchronization and error control functions.
Disclosure of Invention
Aiming at the problems of poor synchronization effect of one-way data transmission between two hosts and easy error in data transmission in the prior art, the invention aims to provide a one-way data transmission synchronization control system between two hosts, which is realized based on a USB interface, and can meet the requirement of complete one-way transmission in the data transmission process between the two hosts and further solve the problems of data transmission synchronization and error control.
Another objective of the present invention is to provide a method for controlling synchronization of unidirectional data transmission between two hosts.
The invention provides a unidirectional data transmission synchronous control system between two hosts, which comprises: the first singlechip is connected with the data receiving host through a USB interface and a USB line, and the second singlechip is connected with the data sending host through a USB interface and a USB line;
the first single chip microcomputer is connected with the second single chip microcomputer through a data transmission line; the data transmission line at least comprises two lines which are used as reverse control signal lines during system initialization;
when the control system is initialized, the first single chip microcomputer sends a plurality of given data blocks to the second single chip microcomputer through a reverse control signal line, the second single chip microcomputer determines the maximum interval time for sending the data blocks by the first single chip microcomputer according to the received data blocks, and the maximum interval time is used as the upper limit of the data packet writing speed for sending the data packets to the first single chip microcomputer by the second single chip microcomputer;
in the data transmission process of the control system, the second single chip microcomputer sends the data packet received from the data sending host machine through the USB interface to the first single chip microcomputer according to the upper limit of the writing speed determined in the initialization process, and the first single chip microcomputer sends the received data packet to the data receiving host machine through the USB interface, so that the data sending and receiving synchronization between the data sending host machine and the data receiving host machine is ensured.
In the above one-way data transmission synchronous control system between the two hosts, the data sending host and the data receiving host are both computers in a broad sense.
In the system for synchronously controlling the one-way data transmission between the two hosts, the first singlechip configuration comprises a first central processing unit, a first USB interface, a first buffer area, a first group of data interfaces and a first internal bus; the second singlechip configuration comprises a second central processing unit, a second USB interface, a second buffer area, a data packet interval storage unit, a second group of data interfaces and a second internal bus; the first central processing unit and the second central processing unit are respectively used for controlling the initialization of the configuration of the first single chip microcomputer and the configuration of the second single chip microcomputer, determining the upper limit of the writing speed of the data packet and transmitting data; the first USB interface is connected with the data receiving host through a first USB line, and the second USB interface is connected with the data sending host through a second USB line; the first buffer area and the second buffer area are respectively used for storing data, the first buffer area stores a data block group for system initialization and a corresponding data block pointer, and the data block group consists of a plurality of data blocks with given sizes; the first group of data interfaces are connected with the second group of data interfaces through data transmission lines; the data packet interval storage unit is used for storing the upper limit of the writing speed of the data packet; a first central processing unit, a first USB interface, a first buffer area and a first group of data interfaces in the first singlechip are mutually subjected to signal or data transmission through a first internal bus; and a second central processing unit, a second USB interface, a second buffer area, a data packet interval storage unit and a second group of data interfaces in the second singlechip are in signal or data transmission through a second internal bus.
In the above one-way data transmission synchronous control system between two hosts, in order to increase the data transmission rate, the data transmission line is a high-speed data transmission line.
The invention further provides a method for synchronously controlling the unidirectional data transmission between the two hosts, which uses the provided control system to operate according to the following steps:
s1, synchronously initializing a first single chip microcomputer and a second single chip microcomputer, comprising the following steps:
s11, the first single chip microcomputer sets two lines CTL1 and CTL2 which are used as reverse control signal lines as signal output; the second singlechip sets two lines CTL1 and CTL2 as reverse control signal lines as signal inputs;
s12, the first single chip microcomputer sets a data interface connected with the CTL1 to be at a high level and sets a data interface connected with the CTL2 to be at a low level;
s13, the data receiving host reads a plurality of data blocks stored by the first singlechip; after the data receiving host reads one data block, the first single chip microcomputer moves the data block pointer to the next data block, and pulls the CTL2 to be at a high level and then immediately pulls the CTL2 to be at a low level;
s14, the second single chip microcomputer detects CTL1 and CTL2 level signals in real time, and when the CTL1 is satisfied with a continuous high level and a signal that the CTL2 jumps from a low level to a high level is obtained, time is recorded until the data receiving host reads a plurality of data blocks;
s15, the second single chip microcomputer calculates the interval between two adjacent recording times in the step S14, the obtained maximum time interval is used as the upper limit of the writing speed of the second single chip microcomputer for sending the data packet to the first single chip microcomputer, and the data packet is stored;
s16, the first single chip microcomputer sets a data interface connected with the data transmission line as an input pin, and the second single chip microcomputer sets the data interface connected with the data transmission line as an output pin;
s2, unidirectional data transmission is carried out by utilizing the first single chip microcomputer and the second single chip microcomputer
And (2) according to the upper limit of the writing speed of the data packet determined in the step (S1), the second single chip microcomputer transmits the data packet from the data sending host computer received through the second USB interface to the first single chip microcomputer, and the first single chip microcomputer further transmits the received data packet to the data receiving host computer through the first USB interface, so that the unidirectional transmission of the data packet is completed.
In the above method for controlling the synchronization of the unidirectional data transmission between the two hosts, in order to enable the data receiving host to correct errors occurring during the data transmission process, both the data sending host and the data receiving host may use error correction coding or continuously and repeatedly send multiple copies per data packet to solve the problem, which may be implemented by conventional means already disclosed in the art.
The system and the method for synchronously controlling the one-way data transmission between the two hosts have the following beneficial effects:
(1) The data transmission host and the data receiving host are respectively connected with the two singlechips through USB interfaces, and the two singlechips are connected through a data transmission line; when the system is initialized, the two single-chip microcomputers are synchronously initialized through the reverse control signal line to determine the upper limit of the writing speed of data packet transmission, so that the transmission and the receiving of the data transmission host and the data receiving host can be ensured to be synchronous while the complete unidirectional transmission of data is realized, and the reliability of unidirectional data transmission is improved.
(2) On the basis of realizing the one-way data transmission synchronization between the two hosts, the invention further combines a data error correction method (for example, error correction coding or data continuous retransmission and the like), can better realize the error control of the one-way transmission data between the two hosts, and further improves the reliability of the one-way data transmission.
(3) The invention is based on the USB interface to reform the synchronous control system with the functions of one-way data transmission synchronization and error control, has high transmission speed and high cost performance, is suitable for popularization and use in the field of network information security, and has very good market prospect.
Drawings
FIG. 1 is a diagram of a system for controlling synchronization of unidirectional data transmission between two hosts.
Detailed Description
The technical solutions of the embodiments of the present invention are clearly and completely described with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, belong to the present invention.
Example 1
The system for synchronously controlling one-way data transmission between two hosts provided by this embodiment, as shown in fig. 1, includes a first single chip connected to a data receiving host via a USB interface and a USB line, and a second single chip connected to a data sending host via a USB interface and a USB line.
In this embodiment, the data sending host and the data receiving host are both computers.
In this embodiment, the first single chip microcomputer and the second single chip microcomputer are CYUSB3014 chips of cypres. The first singlechip configuration comprises a first central processing unit (first CPU), a first USB interface, a first buffer area, a first group of data interfaces and a first internal bus; the second single chip microcomputer configuration comprises a second central processing unit (second CPU), a second USB interface, a second buffer area, a data packet interval storage unit, a second group of data interfaces and a second internal bus. The first central processing unit (first CPU) and the second central processing unit (second CPU) are respectively used for controlling the initialization of the configuration of the first single chip microcomputer and the configuration of the second single chip microcomputer, determining the upper limit of the writing speed of the data packet and transmitting data. The first USB interface is connected with the data receiving host through a first USB line, and the second USB interface is connected with the data sending host through a second USB line. The first buffer area and the second buffer area are respectively used for storing data, the first buffer area stores a data block group used for system initialization and a corresponding data block pointer, the data block group is composed of a plurality of data blocks with given sizes, and the data block pointer is used for tracking the next data block to be processed. The two sets of data interfaces are connected via a high-speed data transmission line. In this embodiment, the high-speed data transmission line includes 32 lines, two of the lines are used as reverse control signal lines CTL1 and CTL2 (the corresponding data interfaces in the first set of data interfaces and the second set of data interfaces are GPIO interfaces, and the remaining interfaces are HSPI interfaces) during system initialization, and the two lines are reused as a part of the high-speed data transmission line after system initialization. The data packet interval storage unit is used for storing the upper limit of the writing speed of the data packet. The first central processing unit, the first USB interface, the first buffer area and the first group of data interfaces in the first singlechip are mutually subjected to signal or data transmission through a first internal bus. And a second central processing unit, a second USB interface, a second buffer area, a data packet interval storage unit and a second group of data interfaces in the second singlechip are in signal or data transmission through a second internal bus.
The one-way data transmission synchronization control system between the two hosts can realize the transmission and receiving synchronization of feedback-free data transmission between the two hosts and simultaneously ensure the error-free data transmission, and comprises the following steps:
s1, a first single chip microcomputer and a second single chip microcomputer are initialized synchronously.
After the configuration parameters of the first single-chip microcomputer and the second single-chip microcomputer are initialized conventionally, in order to realize synchronous control of data transmission between the first single-chip microcomputer and the second single-chip microcomputer, the first single-chip microcomputer and the second single-chip microcomputer need to be initialized synchronously to obtain an upper limit of a writing speed of data packet transmission between the first single-chip microcomputer and the second single-chip microcomputer. The synchronous initialization operation of the first single-chip microcomputer and the second single-chip microcomputer comprises the following steps:
s11, a first CPU of a first single chip microcomputer sets two lines CTL1 and CTL2 which are used as reverse control signal lines as signal outputs; the second CPU of the second single chip sets two lines CTL1 and CTL2 as reverse control signal lines as signal inputs.
S12, a first CPU of the first singlechip sets a data interface connected with the CTL1 to be at a high level and sets a data interface connected with the CTL2 to be at a low level; the high level is "1" and the low level is "0".
S13, the data receiving host reads a plurality of data blocks of the data block group stored in the first buffer area of the first singlechip; after the data receiving host reads one data block each time, the first CPU of the first singlechip moves the data block pointer to the next data block, pulls the CTL2 to the high level and then immediately pulls the low level.
In this embodiment, the first singlechip is firstThe data block group of the buffer area comprisesnA continuous block of data of size 1k (here)n= 10). Continuous reading of data receiving hostnAnd (4) a data block. The data receiving host reads the data block group stored in the first buffer area of the first singlechipnA plurality of consecutive data blocks; the purpose of storing the data block in the first cache region of the first singlechip is to assist the synchronous initialization of the first singlechip and the second singlechip, the size and the content of the data block are not important points protected by the invention, and a person skilled in the art can set the data block by himself according to the requirement; similarly, how the data receiving host processes the received data blocks is not the key point of the protection of the present invention, and those skilled in the art can process the data blocks according to conventional means or set the data blocks by themselves according to requirements. After the data receiving host reads one data block, the first CPU of the first singlechip moves the data block pointer to the next data block, and pulls the CTL2 to be at a high level and then immediately pulls the CTL to be at a low level.
S14, a second CPU of the second single chip microcomputer detects CTL1 and CTL2 level signals in real time, and records time until the data receiving host finishes reading the data blocks in the data block group after the CTL1 continuously keeps high level and the CTL2 jumps from low level to high level signals.
In this embodiment, taking the data receiving host as an example to read the first data block, when the second CPU of the second chip detects that CTL1 is at a high level and CTL2 jumps from a low level to a high level, the time is recordedt 1 . The second CPU of the second singlechip continuously detects the level signals of CTL1 and CTL2 until the data receiving host finishes reading the data blocks in the data block group to obtainnTime of recordingt 1 , t 2 , …,t n 。
S15, a second CPU of the second single chip microcomputer calculates the interval between two adjacent recording times in the step S14, the obtained maximum time interval is used as the upper limit of the writing speed of the second single chip microcomputer for sending the data packet to the first single chip microcomputer, and the data packet is stored in a data packet interval storage unit;
in this embodiment, the second CPU of the second single chip microcomputer utilizest 1 , t 2 , …,t n Calculating the reading time interval of each adjacent data blockt k+1 -t k （k=1,…,n-1), taking the largest one as the interval time for sending the data packet, namely the upper limit of the writing speed for sending the data packet to the first singlechip by the second singlechip.
S16, the first single chip microcomputer sets a data interface connected with the data transmission line as an input pin, and the second single chip microcomputer sets the data interface connected with the data transmission line as an output pin.
And finally, the first singlechip sets the interfaces (GPIO + HSPI) connected with the CTL1, the CTL2 and all other data transmission lines as input pins. The second singlechip sets the interfaces (GPIO + HSPI) connected with the CTL1, the CTL2 and all other data transmission lines as output pins.
Therefore, synchronous initialization of the first single chip microcomputer and the second single chip microcomputer is completed, and a system data packet transmission mode is entered.
S2, unidirectional data transmission is carried out by utilizing the first single chip microcomputer and the second single chip microcomputer
And according to the upper limit of the writing speed of the data packet determined in the step S1, the second CPU of the second single chip transmits the data packet from the data sending host computer received through the second USB interface to the first single chip computer at a data transmission speed which does not exceed the upper limit of the writing speed of the data packet, and the first CPU of the first single chip computer further transmits the received data packet to the data receiving host computer through the first USB interface to finish the unidirectional transmission of the data packet.
In order to enable the data receiving host to correct errors occurring during data transmission, the data sending host and the data receiving host can both adopt the following two data error correction methods to control errors of data transmitted in one direction between the two hosts:
(1) The specific implementation manners of the data transmitting host and the data receiving host using the data error correction code to control the error of the unidirectional transmission data can be referred to the adaptive packet loss recovery method based on the error correction code, the computing device and the storage medium disclosed in CN110855400A, the data transmission device, the data transmitting and receiving apparatus and the data transmission system disclosed in CN101312387A, and the like.
(2) The data transmitting host continuously and repeatedly transmits a plurality of copies of the data to be transmitted (for example, repeatedly transmits each data packet three times) to correct the transmitted data and control the errors of the data transmitted in one direction.
It will be appreciated by those of ordinary skill in the art that the embodiments described herein are intended to assist the reader in understanding the principles of the invention and are to be construed as being without limitation to such specifically recited embodiments and examples. Those skilled in the art, having the benefit of this disclosure, may effect numerous modifications thereto and changes may be made without departing from the scope of the invention in its aspects.
Claims (8)
1. A one-way data transmission synchronization control system between two hosts is characterized by comprising: the first singlechip is connected with the data receiving host through a USB interface and a USB line, and the second singlechip is connected with the data sending host through a USB interface and a USB line;
the first single chip microcomputer is connected with the second single chip microcomputer through a data transmission line; the data transmission line at least comprises two lines which are used as reverse control signal lines during system initialization;
when the control system is initialized, the first single chip microcomputer sends a plurality of given data blocks to the second single chip microcomputer through a reverse control signal line, the second single chip microcomputer determines the maximum interval time for sending the data blocks by the first single chip microcomputer according to the received data blocks, and the maximum interval time is used as the upper limit of the data packet writing speed for sending the data packets to the first single chip microcomputer by the second single chip microcomputer;
in the data transmission process of the control system, the second single chip microcomputer sends the data packet received from the data sending host computer through the USB interface to the first single chip microcomputer according to the write-in speed upper limit determined in the initialization process, and the first single chip microcomputer sends the received data packet to the data receiving host computer through the USB interface, so that the data sending and receiving synchronization between the data sending host computer and the data receiving host computer is ensured.
2. A system for synchronously controlling data transmission between two hosts according to claim 1, wherein said data sending host and said data receiving host are both computers.
3. The system of claim 1, wherein the first single-chip microcomputer comprises a first central processing unit, a first USB interface, a first buffer, and a first set of data interfaces; the second singlechip configuration comprises a second central processing unit, a second USB interface, a second buffer area, a data packet interval storage unit and a second group of data interfaces; the first central processing unit and the second central processing unit are respectively used for controlling the initialization of the configuration of the first single chip microcomputer and the configuration of the second single chip microcomputer, determining the upper limit of the writing speed of the data packet and transmitting data; the first USB interface is connected with the data receiving host through a first USB line, and the second USB interface is connected with the data sending host through a second USB line; the first buffer area and the second buffer area are respectively used for storing data; the first group of data interfaces are connected with the second group of data interfaces through data transmission lines; the data packet interval storage unit is used for storing the upper limit of the writing speed of the data packet.
4. A system for controlling synchronization of data transmission between two hosts according to claim 3, wherein said first buffer stores data block groups for system initialization and corresponding data block pointers, the data block groups being composed of data blocks of a given size.
5. The system of claim 3, wherein the first central processing unit, the first USB interface, the first buffer area, and the first set of data interfaces of the first single chip transmit signals or data via a first internal bus; and a second central processing unit, a second USB interface, a second buffer area, a data packet interval storage unit and a second group of data interfaces in the second singlechip are in signal or data transmission through a second internal bus.
6. A synchronous control system for one-way data transmission between two hosts according to any of claims 1 to 5, characterized in that the data transmission line is a high speed data transmission line in order to increase the data transmission rate.
7. A method of controlling synchronisation of unidirectional data transmission between two hosts, characterised in that the control system provided in any one of claims 1 to 6 is arranged to operate in accordance with the following steps:
s1, synchronously initializing a first single chip microcomputer and a second single chip microcomputer, comprising the following steps:
s11, the first single chip microcomputer sets two lines CTL1 and CTL2 which are used as reverse control signal lines to be signal output; the second singlechip sets two lines CTL1 and CTL2 as reverse control signal lines as signal inputs;
s12, the first single chip microcomputer sets a data interface connected with the CTL1 to be at a high level and sets a data interface connected with the CTL2 to be at a low level;
s13, the data receiving host reads a plurality of data blocks stored by the first singlechip; after the data receiving host reads one data block, the first single chip microcomputer moves the data block pointer to the next data block, and pulls the CTL2 to be at a high level and then immediately pulls the CTL2 to be at a low level;
s14, the second single chip microcomputer detects CTL1 and CTL2 level signals in real time, and when the CTL1 is continuously at a high level and a signal that the CTL2 jumps from a low level to a high level is obtained, time is recorded until the data receiving host reads a plurality of data blocks;
s15, the second single chip microcomputer calculates the interval between two adjacent recording times in the step S14, and the obtained maximum time interval is used as the upper limit of the writing speed of the second single chip microcomputer for sending the data packet to the first single chip microcomputer and is stored;
s16, setting a data interface connected with the data transmission line as an input pin by the first single chip microcomputer, and setting a data interface connected with the data transmission line as an output pin by the second single chip microcomputer;
s2, unidirectional data transmission is carried out by utilizing the first single chip microcomputer and the second single chip microcomputer
And according to the upper limit of the writing speed of the data packet determined in the step S1, the second single chip microcomputer transmits the data packet which is received by the second USB interface and comes from the data sending host computer to the first single chip microcomputer, and the first single chip microcomputer further transmits the received data packet to the data receiving host computer through the first USB interface, so that the unidirectional transmission of the data packet is completed.
8. A method as claimed in claim 7, wherein the data transmitting host and the data receiving host both use error correction coding or multiple copies are transmitted in succession per data packet to control errors in the data transmitted between the data transmitting host and the data receiving host.
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