CN113093658A - Multi-axis servo system architecture design method based on EtherCAT - Google Patents
Multi-axis servo system architecture design method based on EtherCAT Download PDFInfo
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
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Abstract
The invention provides a design method of a multi-axis servo system architecture based on EtherCAT, which combines the EtherCAT technology and the multi-axis servo system, mounts each servo drive unit into the system in a serial cascade mode, packs a command containing information of each EtherCAT servo slave station into a frame of Ethernet data frame during communication by an EtherCAT master station PC, wherein the frame type is 0X88A4, the data frame is processed by a special EtherCTA communication chip ET1100 of the slave station in the transmission process and determines whether to write slave station data into the data frame or read related data from the data frame to an FPGA, the communication hardware is independent of servo control hardware, the data frame starts from the PC master station, is transmitted to the last EtherCAT slave station and then returns to the PC master station through an original path, and a communication period of the system is completed. The invention is suitable for occasions with high requirements on synchronous precision and control precision, such as precision machining, medical instruments and the like, is suitable for occasions requiring expandability, such as the automobile industry, the robot industry and the like, 100Base-TX cables are used for transmission among nodes, and the distance can reach 100 m.
Description
Technical Field
The invention belongs to the field of industrial automation control, and particularly relates to a design method of a multi-axis servo system architecture based on EtherCAT.
Background
Servo motors and stepping motors in industrial automation control are rotating hubs of mechanical devices, and are widely and actively applied to industries such as precision machining, automobile manufacturing, flow process and the like. On the one hand, in the initial stage of industrial field control, engineers generally adopt a point-to-point star system architecture, and the defects of complex wiring, low synchronization precision and poor expandability exist. On the other hand, field buses such as CAN and MVB at the present stage better solve the above defects, but the future rate bottleneck of the industrial field is greatly limited by the data transmission rate of several megabits in the system operation. In general, it is worth to discuss and study to solve the problem of scalability of the number of servo devices and the problem of data transmission rate in the field of industrial automation control.
Disclosure of Invention
In order to solve the above-mentioned problems, the present invention aims to provide a method for designing a multi-axis servo system architecture based on EtherCAT, the method uses a PC with a twincat (the Windows Control and Automation technology) operation core as a system master station, an interrupt is generated when an EtherCAT data frame sent by the master station reaches an ESC (EtherCAT Slave Controller) of a system Slave station, an FPGA (application layer microcontroller) reads data from the ESC after responding to the interrupt, the FPGA decodes the received data and transmits the decoded data to a Control program, the program generates a signal pulse to a servo drive unit to operate a motor, the FPGA writes feedback data into the ESC, and the system master station performs the operation of the next cycle after reading the feedback state.
The technical scheme adopted by the invention is as follows: a design method of a multi-axis servo system architecture based on EtherCAT comprises the following hardware: EtherCAT main website PC, EtherCAT slave station 1, EtherCAT slave station 2, EtherCAT slave station 3, servo drive unit 1, servo drive unit 2, servo drive unit 3, ethernet transmission. The EtherCAT master station PC comprises TwinCAT software and a Network Interface Card (NIC); the EtherCAT slave station 1 comprises an FPGA, an ET1100, a 25MHz clock source, an EEPROM, a PHY chip 1, a PHY chip 2, a transformer 1, a transformer 2, an RJ45(1) and an RJ45 (2); and the Network Interface Card (NIC) is sequentially connected with the EtherCAT slave station 1, the EtherCAT slave station 2 and the EtherCAT slave station 3 in series through an Ethernet transmission medium to complete master-slave data interaction. The data line, the address line and the control line of the FPGA in the EtherCAT slave station 1 are hung on the ET 1100. An interrupt signal line in the control line only allows the FPGA to effectively read, an AL event request register is read in an interrupt service program after the interrupt is responded, and corresponding processing is carried out according to the generated event; the address line allows the FPGA to perform write operation and allows the ET1100 to perform read operation; the data lines allow the FPGA and the ET1100 to perform bidirectional read operation and write operation; the FPGA accesses a register in the ET1100 in an address mode through writing operation on an address line, and the numerical FPGA of the register finishes reading or rewriting data through reading operation and writing operation on a data line.
A design method of a multi-axis servo system architecture based on EtherCAT is characterized in that a master station software analyzes an XML (Slave station equipment description) file, a Slave station ESC (EtherCAT Slave Controller) register is set, ESM (EtherCAT state machine) is operated for periodic communication, and the Slave station software communication flow is as follows:
first, EtherCAT initializes the slave 1 circuitry hardware. EtherCAT initializes an FPGA (application layer microcontroller) in the slave 1, and initializes an ET1100 (slave communication dedicated chip) register.
In the second step, EtherCAT is initialized from station 1ESM (EtherCAT state machine) communication. The FPGA in the EtherCAT slave station 1 inquires a state control register of the EtherCAT master station PC through an address line, a data line and a control line which are connected with the ET1100, reads a related configuration register and starts or stops related communication services of the slave station.
And thirdly, inquiring the PC working mode of the EtherCAT main station. There are three PC operation modes of the EtherCAT master station, which are FREE RUN, SM (synchronous Manager) and DC (Distributed Clock) modes. The FPGA in the EtherCAT slave station 1 inquires the working mode of the EtherCAT master station PC through an address line, a data line and a control line which are connected with the ET1100, and if the working mode is the FREE RUN mode, the fourth step is carried out; if the SM mode is adopted, the fifth step is carried out; and if the mode is the DC mode, the sixth step is carried out.
Fourth, FREE RUN mode. In the FREE RUN mode, the EtherCAT slave station 1 periodically inquires and processes a Process Data (PDO) event; the Process Data (PDO) communication is handled similarly to the loop in the normal C program, i.e. the EtherCAT master PC will access and operate the EtherCAT slave 1 every cycle. And returning to the third step after the execution is finished.
Fifth, SM (Sync Manager) mode. In the SM mode, an FPGA in an EtherCAT slave station 1 judges whether an ET1100 is interrupted by a Process Data Interface (PDI) through an interruption signal IRQ of the ET1100, if so, the FPGA clears a flag bit in the ET1100 through an address line and a data line, and the FPGA enters a PDI (process data interface) interruption service program; if not, continue waiting. And returning to the third step after the execution is finished.
Sixth, DC (Distributed Clock) mode. In DC mode, SYNC (distributed clock synchronization signal) is mapped to IRQ signal to trigger an interrupt, when the synchronization pin is used as LATCH input pin. The FPGA in the EtherCAT slave station 1 judges whether the ET1100 has SYNC interruption or not through the SYNC signal in the ET1100, if so, the FPGA clears the flag bit in the ET1100 through an address line and a data line, and the FPGA enters a SYNC interruption service program; if not, continue waiting. And returning to the third step after the execution is finished.
Compared with the prior art, the invention has the advantages that:
(1) compared with a point-to-point architecture and other serial architectures, the invention has the advantages of more mountable servo driving units and better expansibility. The EtherCAT master station is used as a communication root node, a plurality of EtherCAT slave stations can be connected in series, and the maximum total number of devices in the whole network is 65535 theoretically. The EtherCAT slave station is used as a communication sub-node, and each servo driving unit connected with the EtherCAT slave station can be hung with a plurality of motors.
(2) Compared with other low data volume protocol architectures, the invention can realize the hundred-megabyte transmission requirement, has shorter communication period and larger transmission data volume. The physical layer implementation of the EtherCAT protocol is based on the traditional ethernet, and the increase of the data throughput of the traditional ethernet promotes the increase of the transmittable data volume of the EtherCAT protocol.
(3) Compared with a method that a serial microprocessor is adopted in an application layer, the method has the advantages that the processing speed is higher, and the possibility that the system communication period is influenced is lower. The system communication period needs to be larger than the round trip time of the data frame of the master station on one hand and the processing time of a microprocessor of an application layer of the slave station on the other hand. The FPGA adopts parallel processing, so that the running time of the EtherCAT protocol in the aspect of application layer slave stations and the running time in the aspect of servo driving can be shorter, and the performance is better.
Drawings
FIG. 1 is a flow chart of the design method of the architecture of a multi-axis servo system based on EtherCAT in the invention;
FIG. 2 is a diagram of the FPGA and ET1100 data interface;
fig. 3 is a schematic diagram of an EtherCAT message embedded in an ethernet data frame;
fig. 4 is a system structure block diagram utilized by the method for designing the architecture of the multi-axis servo system based on EtherCAT of the present invention.
The reference numbers in the figures mean: the system comprises an EtherCAT master station PC 1, an EtherCAT slave station 12 as 2, an EtherCAT slave station 2 as 4, an EtherCAT slave station 3 as 3, a servo drive unit 1 as 5, a servo drive unit 2 as 6, a servo drive unit 3 as 7, Ethernet transmission as 8, TwinCAT software as 9, a Network Interface Card (NIC) as 10, an FPGA as 11, an ET1100 as 12, a 25MHz clock source as 13, an EEPROM as 14, a PHY chip 1 as 15, a PHY chip 2 as 16, a transformer 1 as 17, a transformer 2 as 18, an RJ45 as 19 (1) as well as an RJ45(2) as 20.
Detailed Description
The invention is further described with reference to the following figures and detailed description.
As shown in fig. 4, the hardware of the multi-axis servo system architecture design method based on EtherCAT of the present invention includes: the system comprises an EtherCAT master station PC 1, an EtherCAT slave station 1_2, an EtherCAT slave station 2_3, an EtherCAT slave station 3_4, a servo drive unit 1_5, a servo drive unit 2_6, a servo drive unit 3_7 and an Ethernet transmission 8. The EtherCAT master station PC 1 comprises TwinCAT software 9 and a Network Interface Card (NIC) 10; the EtherCAT slave station 1_2 comprises an FPGA11, an ET 110012, a 25MHz clock source 13, an EEPROM 14, a PHY chip 1_15, a PHY chip 2_16, a transformer 1_17, a transformer 2_18, an RJ45(1)19 and an RJ45(2) 20; and the Network Interface Card (NIC)10 is sequentially connected with the EtherCAT slave station 1_2, the EtherCAT slave station 2_3 and the EtherCAT slave station 3_4 in series through an Ethernet transmission medium to complete master-slave data interaction. The data line, the address line and the control line of the FPGA11 in the EtherCAT slave station 1_2 are hung on ET 110012. An interrupt signal line in the control line only allows the FPGA11 to effectively read, an AL event request register is read in an interrupt service program after the interrupt is responded, and corresponding processing is carried out according to the generated event; the address line allows the FPGA11 to write and allows the ET 110012 to read; the data lines allow the FPGA11 and the ET 110012 to perform bidirectional read operation and write operation; the FPGA11 accesses the register in the ET 110012 in the form of address through the write operation to the address line, and the FPGA11 of the numerical value of the register completes the reading or rewriting of the data through the read operation and the write operation to the data line.
A design method of a multi-axis servo system architecture based on EtherCAT is characterized in that a master station software analyzes an XML (Slave station equipment description) file, a Slave station ESC (EtherCAT Slave Controller) register is set, ESM (EtherCAT state machine) is operated for periodic communication, and the Slave station software communication flow is as follows:
in the first step, EtherCAT initializes the slave 1_2 circuitry hardware. EtherCAT initializes an FPGA (application layer microcontroller) 11 in the slave station 1_2, and initializes an ET1100 (slave station communication dedicated chip) 12 register.
In the second step, EtherCAT is initialized from station 1ESM (EtherCAT state machine) 2. The FPGA11 in the EtherCAT slave station 1_2 queries a state control register of the EtherCAT master station PC 1 through an address line, a data line and a control line which are connected with the ET 110012, reads a related configuration register and starts or stops related communication services of the slave station.
And thirdly, inquiring the working mode of the EtherCAT main station PC 1. There are three working modes of the EtherCAT master station PC 1, which are a FREE RUN mode, an SM (synchronous Manager) mode, and a DC (Distributed Clock) mode. The FPGA11 in the EtherCAT slave station 1_2 inquires the working mode of the EtherCAT master station PC 1 through an address line, a data line and a control line which are connected with ET 110012, and if the working mode is a FREE RUN mode, the fourth step is carried out; if the SM mode is adopted, the fifth step is carried out; and if the mode is the DC mode, the sixth step is carried out.
Fourth, FREE RUN mode. In a FREE RUN mode, the EtherCAT slave station 1_2 periodically inquires and processes a Process Data (PDO) event; the Process Data (PDO) communication is handled similarly to the loop in the normal C program, i.e. the EtherCAT master station PC 1 accesses and operates the EtherCAT slave station 1_2 every cycle. And returning to the third step after the execution is finished.
Fifth, SM (Sync Manager) mode. In the SM mode, the FPGA11 in the EtherCAT slave station 1_2 can determine whether the ET 110012 has a Process Data Interface (PDI) interrupt through an interrupt signal IRQ of the ET 110012, if so, the FPGA11 clears a flag bit in the ET 110012 through an address line and a data line, and the FPGA11 enters a PDI (process data interface) interrupt service program; if not, continue waiting. And returning to the third step after the execution is finished.
Sixth, DC (Distributed Clock) mode. In DC mode, SYNC (distributed clock synchronization signal) is mapped to IRQ signal to trigger an interrupt, when the synchronization pin is used as LATCH input pin. The FPGA11 in the EtherCAT slave station 1_2 judges whether the ET 110012 has SYNC interruption or not through the SYNC signal in the ET 110012, if so, the FPGA11 clears the flag bit in the ET 110012 through an address line and a data line, and the FPGA11 enters a SYNC interruption service program; if not, continue waiting. And returning to the third step after the execution is finished.
A design method of a multi-axis servo system architecture based on EtherCAT comprises the following steps: the system comprises an EtherCAT master station PC 1, an EtherCAT slave station 1_2, an EtherCAT slave station 2_3, an EtherCAT slave station 3_4, a servo drive unit 1_5, a servo drive unit 2_6, a servo drive unit 3_7 and an Ethernet transmission 8. The EtherCAT master station PC 1 comprises TwinCAT software 9 and a Network Interface Card (NIC) 10; the EtherCAT slave station 1_2 comprises an FPGA11, an ET 110012, a 25MHz clock source 13, an EEPROM 14, a PHY chip 1_15, a PHY chip 2_16, a transformer 1_17, a transformer 2_18, an RJ45(1)19 and an RJ45(2) 20; and the Network Interface Card (NIC)10 is sequentially connected with the EtherCAT slave station 1_2, the EtherCAT slave station 2_3 and the EtherCAT slave station 3_4 in series through an Ethernet transmission medium to complete master-slave data interaction. The data lines, address lines and control lines of the FPGA11 (application layer microcontroller) in the EtherCAT slave station 1_2 are hung on an ET1100 (slave station communication dedicated chip) 12. An interrupt signal line in the control line only allows the FPGA11 to perform effective reading operation, an AL (Application Layer) event request register is read in an interrupt service program after the interrupt is responded, and corresponding processing is performed according to an occurred event; the address line allows the FPGA11 to write and allows the ET 110012 to read; the data lines allow the FPGA11 and the ET 110012 to perform bidirectional read operation and write operation; the FPGA11 accesses the register in the ET 110012 in the form of address through the write operation to the address line, and the FPGA11 of the numerical value of the register completes the reading or rewriting of the data through the read operation and the write operation to the data line.
The communication mode of the EtherCAT master station PC 1 and the EtherCAT slave station 1_2 is Ethernet transmission 8, and the communication medium can adopt 100Base-TX standard Ethernet cable or optical cable.
The frame type used by the ethernet transport 8 is 0X88a4, and data is transported in bundled frames. In each period, commands and data sent by the master station to all the slave stations, status data returned by each slave station to the master station and the like are concentrated in one frame of message.
The communication modes of the EtherCAT slave station 1_2 and the EtherCAT slave station 2_3, and the EtherCAT slave station 2_3 and the therCAT slave station 3_4 are Ethernet transmission, and the communication medium can adopt a 100Base-TX standard Ethernet cable or an optical cable.
The servo drive unit 1_5 and the EtherCAT are hung together from the FPGA11 in the slave station 1_ 2. The servo driving unit 1_5 and the FPGA11 can be connected according to a conventional servo motor connection method, and the FPGA11 can read the state of the servo driving unit 1_5 and control the motion of a motor connected with the servo driving unit 1_ 5.
The EtherCAT master station PC 1 comprises TwinCAT (the Windows Control and Automation technology) software 9 and a Network Interface Card (NIC) 10.
twinCAT (the Windows Control and Automation technology) software 9 is industrial Control configuration software, and can realize the master station function and the human-computer interaction interface in the EtherCAT system.
When the EtherCAT master station PC 1 runs the EtherCAT protocol, the bottom operating system is required to be a real-time system. The common Windows is not a real-time system, and when the system works as a PLC, a control software TwinCAT running core, namely 9TwinCAT software, must be installed.
The TwinCAT software 9 is developed by german corporation, and is divided into two versions, Windows CE and Windows Standard, and the Windows Standard version is generally used when the PC is used as an EtherCAT master station.
The twinCAT software 9 is secondarily developed and expanded on the basis of CodesSys (Controller Development System, PLC software programming tool), is based on PLCopen international organization specification and supports various functional blocks provided by a CoDesSys software toolkit.
The Network Interface Card (NIC)10 is not required to be specially customized, and may be a standard ethernet card, and is responsible for ethernet communication control and transceiving.
The EtherCAT slave station 1_2 comprises an FPGA11, a 12ET1100, a 1325 MHz clock source, a 14EEPROM, a 15PHY chip 1, a 16PHY chip 2, a 17 transformer 1, an 18 transformer 2, a 19RJ45(1) and a 20RJ45 (2).
The FPGA (application layer microcontroller) 11 is responsible for processing EtherCAT communication with the ET1100 (slave station communication dedicated chip) 12 and completing control tasks of an application layer.
The ET1100 (Slave station communication dedicated chip) 12 assumes the role of an ESC (EtherCAT Slave Controller ), is responsible for processing EtherCAT data frames in a communication link, and realizes data exchange between the EtherCTA master station PC 1 and the local application layer of the EtherCTA Slave station 1_2 by using a dual-port storage area.
The connection lines of an FPGA (application layer microcontroller) 11 and an ET1100 (slave station communication special chip) 12 comprise 8-bit or 16-bit data lines, 16-bit address lines, 9 control lines and state lines.
The FPGA11 judges the current state of the ET 110012 according to the control line and the state line and performs appointed read-write operation; the FPGA11 operates the register space of the first 4KB (0X000:0X0FFF) space and the process data storage space of the 0X1000:0XFFF address space through address lines; the FPGA11 writes the value of the specific operation through the data line.
ET 110012 supports the application layers of the row specification CiA 402 and SERCOS protocol in the CANopen protocol from the station control chip, referred to as CoE and SoE, respectively, both defining the communication interface standard between the control system and the power driven system.
The control of the FPGA11 on the servo driving unit 1_5 depends on a servo driving CANopen application layer protocol command read by the FPGA11 from the ET 110012, and the FPGA11 selects to read the motor state or control the motor motion according to the motion command.
The EtherCAT master station 1_2 completes configuration and data communication of slave stations through read/write operations of registers of a control chip of the ET 110012 slave stations, wherein the configuration and the data communication comprise digital quantity input/output, a mailbox, a distributed clock and the like.
ET 110012 has 4 physical communication ports, only two of which are used here, and the ports are connected to PHY chip (1)15 and PHY chip (2)16 through MII interface (standard ethernet physical layer interface) and output clock signals to PHY (ethernet physical layer) devices.
ET 110012 has 4 physical communication ports, each of which can transmit and receive ethernet data frames, and the transmission order of the data frames inside ESC (EtherCAT Slave Controller) is fixed. Generally, data enters 12ET1100 from a physical communication port 0, then data transmission is sequentially forwarded according to the port sequence of 0-3-1-2-0, and if 11ET1100 detects that one port has no external connection, the data is automatically looped back and forwarded to the next port.
The 25MHz clock source 13 uses a quartz crystal. When ET 110012 and 25MHz clock source 13 are connected, OSC _ IN and OSC _ OUT are connected to two ends of 25MHz clock source 13 external crystal, CLK25OUT1/2 output of ET 110012 is used as clock input of PHY chip.
The EEPROM 14 is used to store information about a device required for the ET1100 (slave communication dedicated chip) 12. The EEPROM 14 uses word addresses, and the word addresses 0 to 63 are essential basic contents, including an ESC (ethernet Slave Controller) register configuration area, a product presentation area, hardware latency, mailbox configuration in a boot state, and standard mailbox communication SM (Sync Manager) channel configuration.
The interface used by PHY chips 1_15 and 2_16 is an MII interface (standard ethernet physical layer interface), and the chip model is KS 8721. The 12ET1100 chip only supports PHY (Ethernet physical layer) devices of an MII interface, and Beckhoff provides some devices which meet and do not meet requirements in order to meet the required conditions of the ET1100, wherein the specific model can be seen as an official network.
Transformers 1_17 and 2_18 use common ethernet data transformers, here H1102. Transformer 1_17 and transformer 2_18 ensure that the ethernet chip meets the requirements of IEEE802.3 standard, and RJ45 socket is connected to communicate with the outside world.
RJ45(1)19 and RJ45(2)20 use common RJ45 connectors.
Claims (3)
1. A design method of a multi-axis servo system architecture based on EtherCAT is characterized in that hardware of the method comprises the following steps: the Ethernet control system comprises an EtherCAT main station PC (1), EtherCAT slave stations 1(2), EtherCAT slave stations 2(3), EtherCAT slave stations 3(4), servo drive units 1(5), servo drive units 2(6), servo drive units 3(7) and Ethernet transmission (8), wherein the EtherCAT main station PC (1) comprises TwinCAT software (9) and Network Interface Cards (NICs) (10); the EtherCAT slave station 1(2) comprises an FPGA (11), an ET1100(12), a 25MHz clock source (13), an EEPROM (14), a PHY chip 1(15), a PHY chip 2(16), a transformer 1(17), a transformer 2(18), RJ45(1) (19) and RJ45(2) (20); and the Network Interface Card (NIC) (10) is sequentially connected with the EtherCAT slave station 1(2), the EtherCAT slave station 2(3) and the EtherCAT slave station 3(4) in series through an Ethernet transmission medium to complete master-slave data interaction.
2. The EtherCAT-based multi-axis servo system architecture design method according to claim 1, characterized in that: the data line, the address line and the control line of an FPGA (Application Layer microcontroller) (11) in an EtherCAT slave station 1(2) are hung on an ET1100 (slave station communication special chip) (12), an interrupt signal line in the control line only allows the FPGA (11) to carry out effective reading operation, an AL (Application Layer) event request register is read in an interrupt service program after the interrupt is responded, and corresponding processing is carried out according to the generated event; the address line allows the FPGA (11) to perform write operation and allows the ET1100(12) to perform read operation; the data line allows the FPGA (11) and the ET1100(12) to carry out bidirectional read operation and write operation; the FPGA (11) accesses the register in the ET1100(12) in the form of address through writing operation on the address line, and the FPGA (11) of the numerical value of the register completes reading or rewriting of data through reading operation and writing operation on the data line.
3. The EtherCAT-based multi-axis servo system architecture design method according to claim 1, characterized in that: the master station software analyzes an XML (Slave station equipment description) file, sets a Slave station ESC (EtherCAT Slave Controller) register, runs an ESM (EtherCAT state machine), and then periodically communicates, and the Slave station software communication flow is as follows:
firstly, initializing circuit hardware of a slave station 1(2), initializing an FPGA (application layer microcontroller) (11) in the slave station 1(2) and initializing an ET1100 (slave station communication special chip) (12) register;
secondly, the EtherCAT slave station 1(2) is initialized by ESM (EtherCAT state machine) communication, an FPGA (11) in the EtherCAT slave station 1(2) inquires a state control register of the EtherCAT master station PC (1) through an address line, a data line and a control line which are connected with the ET1100(12), reads a related configuration register, and starts or stops related communication service of the slave station;
thirdly, inquiring the working mode of the EtherCAT master station PC (1), wherein the working modes of the EtherCAT master station PC (1) are three, namely a FREE RUN (FREE running) mode, an SM (synchronous Manager) mode and a DC (Distributed Clock) mode, an FPGA (11) in the EtherCAT slave station 1(2) inquires the working mode of the EtherCAT master station PC (1) through an address line, a data line and a control line which are connected with an ET1100(12), and if the working mode is the FREE RUN mode, performing the fourth step; if the SM mode is adopted, the fifth step is carried out; if the mode is the DC mode, the sixth step is carried out;
step four, a FREE RUN mode, in which EtherCAT periodically queries and processes Process Data (PDO) events from station 1 (2); the processing of Process Data (PDO) communication is similar to the cycle in the common C program, namely the EtherCAT master station PC (1) can access and operate the EtherCAT slave station 1(2) in each period, and the third step is returned after the execution is finished;
fifthly, in an SM (synchronous Manager) mode, in the SM mode, an FPGA (11) in an EtherCAT slave station 1(2) judges whether a Process Data Interface (PDI) of the ET1100(12) is interrupted or not through an interrupt signal IRQ of the ET1100(12), if so, the FPGA (11) clears a flag bit in the ET1100(12) through an address line and a data line, and the FPGA (11) enters a PDI (process data interface) interrupt service program; if not, continuing to wait, and returning to the third step after the execution is finished;
sixthly, in a DC (Distributed Clock) mode, in the DC mode, SYNC (Distributed Clock synchronous signal) is mapped to IRQ signal to trigger interruption, at the moment, a synchronous pin is used as an LATCH input pin, an EtherCAT slave station 1(2) can judge whether the ET1100(12) has SYNC interruption or not through the SYNC signal in the ET1100(12), if yes, the FPGA (11) clears a flag bit in the ET1100(12) through an address line and a data line, and the FPGA (11) enters a SYNC interruption service program; if not, continuing to wait, and returning to the third step after the execution is finished.
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Cited By (9)
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| CN114006950A (en) * | 2021-09-26 | 2022-02-01 | 北京零壹空间电子有限公司 | On-arrow communication method, system, computer device and storage medium |
| CN114089662A (en) * | 2021-11-17 | 2022-02-25 | 湖南力行动力科技有限公司 | Implementation method of novel high-performance electronic shaft transmission control system |
| CN114257469A (en) * | 2021-12-22 | 2022-03-29 | 深圳市英威腾电气股份有限公司 | Communication method, device and medium of EtherCAT main station |
| CN114500154A (en) * | 2022-01-26 | 2022-05-13 | 成都中天自动化控制技术有限公司 | Real-time synchronization method for master station and slave station of Ethercat bus |
| CN115051888A (en) * | 2022-06-14 | 2022-09-13 | 南京晓庄学院 | EtherCat master station control system based on AM335X |
| CN115091471A (en) * | 2022-08-26 | 2022-09-23 | 法奥意威(苏州)机器人系统有限公司 | Mechanical arm safety control method and device based on EtherCAT |
| CN115347985A (en) * | 2022-08-22 | 2022-11-15 | 欧瑞传动电气股份有限公司 | EtherCAT modular multi-axis servo driver and internal communication method |
| CN116540639A (en) * | 2023-07-07 | 2023-08-04 | 江苏集萃苏科思科技有限公司 | Multi-axis real-time motion control system |
| CN117434907A (en) * | 2023-12-18 | 2024-01-23 | 广东科伺智能科技有限公司 | Method and equipment for controlling number of servo drivers based on CoDeSys controller |
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Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114006950A (en) * | 2021-09-26 | 2022-02-01 | 北京零壹空间电子有限公司 | On-arrow communication method, system, computer device and storage medium |
| CN114006950B (en) * | 2021-09-26 | 2023-10-20 | 北京零壹空间电子有限公司 | Communication method, system, computer device and storage medium on arrow |
| CN114089662A (en) * | 2021-11-17 | 2022-02-25 | 湖南力行动力科技有限公司 | Implementation method of novel high-performance electronic shaft transmission control system |
| CN114257469A (en) * | 2021-12-22 | 2022-03-29 | 深圳市英威腾电气股份有限公司 | Communication method, device and medium of EtherCAT main station |
| CN114500154A (en) * | 2022-01-26 | 2022-05-13 | 成都中天自动化控制技术有限公司 | Real-time synchronization method for master station and slave station of Ethercat bus |
| CN114500154B (en) * | 2022-01-26 | 2024-02-27 | 成都中天自动化控制技术有限公司 | Ethercat bus master station and slave station real-time synchronization method |
| CN115051888B (en) * | 2022-06-14 | 2024-01-26 | 南京晓庄学院 | EtherCat master station control system based on AM335X |
| CN115051888A (en) * | 2022-06-14 | 2022-09-13 | 南京晓庄学院 | EtherCat master station control system based on AM335X |
| CN115347985A (en) * | 2022-08-22 | 2022-11-15 | 欧瑞传动电气股份有限公司 | EtherCAT modular multi-axis servo driver and internal communication method |
| CN115347985B (en) * | 2022-08-22 | 2023-10-13 | 欧瑞传动电气股份有限公司 | EtherCAT modularized multi-axis servo driver and internal communication method |
| CN115091471A (en) * | 2022-08-26 | 2022-09-23 | 法奥意威(苏州)机器人系统有限公司 | Mechanical arm safety control method and device based on EtherCAT |
| CN115091471B (en) * | 2022-08-26 | 2022-11-15 | 法奥意威(苏州)机器人系统有限公司 | Mechanical arm safety control method and device based on EtherCAT |
| CN116540639A (en) * | 2023-07-07 | 2023-08-04 | 江苏集萃苏科思科技有限公司 | Multi-axis real-time motion control system |
| CN116540639B (en) * | 2023-07-07 | 2023-09-19 | 江苏集萃苏科思科技有限公司 | Multi-axis real-time motion control system |
| CN117434907A (en) * | 2023-12-18 | 2024-01-23 | 广东科伺智能科技有限公司 | Method and equipment for controlling number of servo drivers based on CoDeSys controller |
| CN117434907B (en) * | 2023-12-18 | 2024-03-22 | 广东科伺智能科技有限公司 | Method and equipment for controlling number of servo drivers based on CoDeSys controller |
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