CN113078912A - Parallel generation device of syndrome in synchronous byte decoder based on lookup table - Google Patents

Parallel generation device of syndrome in synchronous byte decoder based on lookup table Download PDF

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CN113078912A
CN113078912A CN202110337604.5A CN202110337604A CN113078912A CN 113078912 A CN113078912 A CN 113078912A CN 202110337604 A CN202110337604 A CN 202110337604A CN 113078912 A CN113078912 A CN 113078912A
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syndrome
register
bit
input
lookup table
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刘昌银
张鹏
杜建和
陈远知
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Communication University of China
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Abstract

The invention relates to a parallel generation device of syndrome in MPEG-2 synchronous byte decoder based on lookup table, which is suitable for ITU-T J.83 recommended digital multi-program system B and is characterized in that the device mainly comprises a block of 1504 bit memories and 15 registers R0～R14128 two-input AND gates and 128 two-input XOR gates. The syndrome generating device provided by the invention inputs 188 bytes of received data in a 16-bit parallel mode and outputs 1 byte syndrome in an 8-bit parallel mode, can effectively reduce the logic resource requirement while improving the processing speed by 16 times, and has the advantages of high running speed, low logic resource consumption and the like.

Description

Parallel generation device of syndrome in synchronous byte decoder based on lookup table
Technical Field
The invention relates to the field of cable digital television, in particular to a parallel generation technology of an MPEG-2 synchronous byte decoder syndrome based on a lookup table in a digital multi-program system B recommended by ITU-T J.83.
Background
The MPEG-2 transport packet is 188 bytes long and consists of a 1 byte "sync" field, a 3 byte "header" field, and a 184 byte "payload" field. For ease of description, we refer collectively to the 3-byte "header" field and the 184-byte "payload" field as 187-byte information.
ITU-T j.83 recommends a digital multi-program system for cable distribution of 4 television, voice and data services, one of which is digital multi-program system B. The system removes the 'synchronization' field on the basis of the MPEG-2 transmission packet format, and adds a 1-byte 'checksum' field after the 'payload' field to form a code word, and the length of the code word still keeps 188 bytes. The checksum is calculated from a FIR parity check linear block code over 187 bytes of information and is used for synchronization and error detection to provide enhanced packet partitioning and error detection capabilities independent of the FEC layer. If the transmitting end transmits the code words in a serial mode, the Most Significant Bit (MSB) of the byte is transmitted first, and the Least Significant Bit (LSB) is transmitted last. The receiving end uses the syndrome generating apparatus to determine whether the received data is a valid codeword.
The digital multi-program system B presents a circuit model of the syndrome generating apparatus of the MPEG-2 sync byte decoder as shown in fig. 1. The circuit model is composed of two functional blocks, namely an Infinite Impulse Response (IIR) filter and a Finite Impulse Response (FIR) filter, and comprises 1512 registers and 8 two-input exclusive-or gates. In this device, all registers are initialized to '0'. The device serially inputs 188 bytes of received data and serially outputs 1 byte syndrome after 1504 clock cycles.
The syndrome generating device provided by the digital multi-program system B uses 1512 registers and 8 two-input exclusive-OR gates, consumes more logic resources, takes 1504 clock cycles to calculate a syndrome once, and has low operation speed.
Disclosure of Invention
Aiming at the defects of high consumption of logic resources and low operation speed of a syndrome generation scheme provided by an ITU-T J.83 digital multi-program system B, the invention provides a scheme for generating syndromes in parallel based on a lookup table, and provides a corresponding circuit model to reduce the logic resource requirement and improve the processing speed.
As shown in FIG. 3, the syndrome parallel generation device in the MPEG-2 synchronous byte decoder based on the lookup table mainly comprises a block of 1504 bit memories and 15 registers R0～R14128 two-input AND gates and 128 two-input XOR gates. The memory stores the lookup table of the combined filter coefficient, the address of the lookup table corresponds to the index j of the lookup table, and a 16-bit data bus is adopted to output e1481-16j～e1496-16jWherein j is more than or equal to 0<94. Register R0～R6For storing coefficients e of the joint filter, respectively1497-16j～e1503-16j. Register R7～R14Are respectively used for storing d1496～d1503And intermediate operation results thereof. 128 two-input AND gates and 128 two-input XOR gates for calculating d1496～d1503. The apparatus inputs 188 bytes of received data in a 16-bit parallel manner and outputs 1 byte syndrome in an 8-bit parallel manner. The calculation of the syndrome is completed in 5 steps: (1) initializing j to 0, register R0～R14Are all initialized to 0, wherein the register R0～R6Is equivalent to being initialized to e1497～e1503(ii) a (2) Bit a of the input data segment vector16j～a16j+15Memory output e1481-16j～e1496-16jRegister R0～R6Output e1497-16j～e1503-16jThey output e in common1481-16j～e1503-16j；(3)e1481-16j～e1503-16jThe successive 16 bits form 8 different vectors, 128 two-input AND gates and 128 two-input XOR gates perform vector multiplication, and the products are accumulated into a register R7～R14Performing the following steps; (4) e.g. of the type1481-16j～e1487-16jIs saved to register R0～R6Performing the following steps; (5) j is increased by 1 if j<94, jumping to the step (2); otherwise, register R7～R14The content in (1) is d1496～d1503And finishing the calculation of the syndrome.
The syndrome generating device based on the lookup table provided by the invention inputs the received data in parallel and outputs the syndromes in parallel, and can effectively reduce the logic resource requirement while greatly improving the processing speed at the cost of increasing a small amount of memories.
The advantages and spirit of the present invention can be further understood by the following detailed description and accompanying drawings.
Drawings
FIG. 1 is a circuit model of an MPEG-2 Sync byte decoder generating syndromes;
FIG. 2 is a polynomial model of the generation of syndromes by an MPEG-2 Sync byte decoder;
FIG. 3 is a circuit model for parallel syndrome generation by a look-up table based MPEG-2 Sync byte decoder;
fig. 4 shows the specific contents of the look-up table made from some of the coefficients of the joint filter.
Detailed Description
The invention is further described with reference to the following figures and specific examples, which are not intended to be limiting.
In fig. 1, the received data sequence and the output sequence are respectively marked aiAnd diTheir values are '0' or '1', where 0. ltoreq. i<1504，d1496～d1503A 1-byte syndrome is constructed.
The corresponding polynomial model of FIG. 1 is shown in FIG. 2, with inputs and outputs being
Figure BDA0002998127680000021
Figure BDA0002998127680000031
When 0 is more than or equal to i<1504, coefficient a in the above equationiAnd diA in FIG. 1iAnd diAre identical. In FIG. 2, the IIR filter performs a division operation on the generator polynomial g (x), and the FIR filter performs a division operation on the polynomial [1+ x ]1497b(x)]Wherein g (x) is 1+ x5+x6+x8，b(x)＝1+x+x3+x7. The IIR filter and the FIR filter constitute a joint filter having a characteristic polynomial of
Figure BDA0002998127680000032
The coefficient of the joint filter is eiWhen i is more than or equal to 0 and less than or equal to 1496, eiWhen i is 0 or 1<0 or i>At 1496, e i0. It is obvious that the joint filter is a FIR filter whose input and output satisfy the following relationship
d(x)＝a(x)e(x) (4)
Substituting the formulas (1) to (3) into the above formula to obtain 8 bits of the syndrome
Figure BDA0002998127680000033
According to the formula (3), when i<At 0 time, e i0. Therefore, the formula (5) can be rewritten as
Figure BDA0002998127680000034
In the above formula, the equal sign has 1504 terms on the right, and 1504 ÷ 16 ═ 94. Since 1504 is an integer multiple of 16, the received data sequence may be divided into equal length segments of 16 bits each, which form a data segment vector a16j+15 a16j+14 … a16j]Wherein j is more than or equal to 0<94. Successive 16 bits of the coefficients of the joint filter may constitute a column vector, and thus equation (6) may be rewritten in the form of multiplication of vectors
Figure BDA0002998127680000041
Wherein, the upper labelTRepresenting a vector transposition. In the above equation, the row vectors in each equation are identical and are all data segment vectors, and the 8 column vectors are slightly different: the column vector in the adjacent equation is only 1 bit different, and the column vector in the following equation is updated with 1 bit at the lowest bit after the column vector in the above equation is shifted left by one bit. Thus, each column vector in equation (7) may be considered to be taken from the column vector [ e ]1481-16j e1482-16j … e1503-16j]TOf 16 consecutive bits.
Based on the above analysis, we can obtainA circuit model of a syndrome parallel generation apparatus in a look-up table based MPEG-2 sync byte decoder is shown in fig. 3. The apparatus inputs 188 bytes of received data in a 16-bit parallel manner and outputs 1 byte syndrome in an 8-bit parallel manner. The device mainly comprises a 1504 bit memory and 15 registers R0～R14128 two-input AND gates and 128 two-input XOR gates. The lookup table is made of partial coefficients of the joint filter, and the range of the index j is more than or equal to 0 and less than or equal to j<94, each entry containing 16 coefficients, e corresponding to the most significant bit to the least significant bit1481-16j～e1496-16jThe specific content expressed in hexadecimal is shown in fig. 4. The memory stores a lookup table composed of the coefficients of the combined filter, the address of the lookup table corresponds to the index j of the lookup table, and a 16-bit data bus is adopted to output e1481-16j～e1496-16j. Register R0～R6For storing coefficients e of the joint filter, respectively1497-16j～e1503-16jWherein when j is 0, e is known from the formula (3)1497～e1503Are all 0. Thus, register R0～R6Needs to be initialized to all zeros. Register R7～R14Are respectively used for storing d1496～d1503And their intermediate operation results, they also need to be initialized to all zeros. 128 two-input AND gates and 128 two-input XOR gates for calculating d1496～d1503128 two-input AND gates for performing element multiplication of vector multiplication in equation (7), 128 two-input XOR gates for performing element modulo-2 addition of vector multiplication in equation (7) and accumulating the product into register R7～R14In (1).
Aiming at a digital multi-program system B recommended by ITU-T J.83, the invention provides a parallel generation method of syndromes in an MPEG-2 synchronous byte decoder based on a lookup table, and the steps of calculating the primary syndromes are as follows:
(1) initializing j to 0, register R0～R14Are all initialized to 0, wherein the register R0～R6Is equivalent to being initialized to e1497～e1503；
(2) Bit a of the input data segment vector16j～a16j+15Memory output e1481-16j～e1496-16jRegister R0～R6Output e1497-16j～e1503-16jThey output e in common1481-16j～e1503-16j；
(3)e1481-16j～e1503-16jThe successive 16 bits form 8 different vectors, 128 two-input AND gates and 128 two-input XOR gates perform vector multiplication, and the products are accumulated into a register R7～R14Performing the following steps;
(4)e1481-16j～e1487-16jis saved to register R0～R6Performing the following steps;
(5) j is increased by 1 if j<94, jumping to the step (2); otherwise, register R7～R14The content in (1) is d1496～d1503And finishing the calculation of the syndrome.
If the syndrome bit d1496～d1503Equal to '0', '1', '0', '1', and '1', respectively, that is combined into one byte equal to the hexadecimal number 0x47, the received data is considered a valid codeword; otherwise, the received data is considered to be erroneous.
The present invention requires 1504 bit memories, 15 registers, 128 two-input and gates and 128 two-input xor gates, which produce syndrome results over 94 clock cycles. Compared with the syndrome generating device provided by the ITU-T J.83 digital multi-program system B, the processing speed of the invention is improved by 16 times, although 128 two-input AND gates and 120 two-input XOR gates are used, the consumption of the register is less than 1 percent of that of the former, and in general, very little logic resource is consumed. The disadvantage of the present invention is that a block of 1504 bits memory is required. In summary, compared with the syndrome generating device provided by ITU-T J.83 digital multi-program system B, the invention has the advantages of high running speed, low logic resource consumption and the like.
While the present invention has been described in detail and by way of examples and embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention.

Claims (3)

1. A parallel generation device of syndrome in synchronous byte decoder based on lookup table is suitable for digital multi-program system B recommended by ITU-T J.83, and is characterized by that 188 bytes of received data are input in 16-bit parallel mode, 1 byte syndrome is output in 8-bit parallel mode, and the received data sequence aiDivided into equal length segments of 16 bits each, which form a data segment vector a16j+15 a16j+14 … a16j]Wherein, 0 is less than or equal to i<1504，0≤j<94, 8 bits of the syndrome are d1496～d1503The coefficient of the joint filter is eiWhen i is more than or equal to 0 and less than or equal to 1496, eiWhen i is 0 or 1<0 or i>At 1496, ei0, the lookup table is made of partial coefficients of the joint filter, and the index j is in the range of 0 ≦ j<94, each entry containing 16 coefficients, e corresponding to the most significant bit to the least significant bit1481-16j～e1496-16jCharacterised in that the device comprises the following components:
a 1504 bit memory for storing a lookup table composed of combined filter coefficients, whose address corresponds to the index j of the lookup table, and outputting e by using a 16-bit data bus1481-16j～e1496-16j；
15 registers R0～R14Register R0～R6For storing coefficients e of the joint filter, respectively1497-16j～e1503-16jWherein, when j is 0, e1497～e1503Are all 0, register R7～R14Are respectively used for storing d1496～d1503And intermediate operation results thereof;
128 two-input AND gates and 128 two-input XOR gates for calculating d1496～d1503128 two-input AND gates for performing element multiplication of vector multiplication, 128 two-input XOR gates for performing element modulo-2 addition of vector multiplication and accumulating the product into register R7～R14In (1).
2. A parallel generation method of syndrome in synchronous byte decoder based on lookup table is suitable for digital multi-program system B recommended by ITU-T J.83, the device inputs 188 bytes of received data in 16-bit parallel mode, outputs 1 byte syndrome in 8-bit parallel mode, and receives data sequence aiDivided into equal length segments of 16 bits each, which form a data segment vector a16j+15 a16j+14 … a16j]Wherein, 0 is less than or equal to i<1504，0≤j<94, 8 bits of the syndrome are d1496～d1503The coefficient of the joint filter is eiWhen i is more than or equal to 0 and less than or equal to 1496, eiWhen i is 0 or 1<0 or i>At 1496, ei0, the lookup table is made of partial coefficients of the joint filter, and the index j is in the range of 0 ≦ j<94, each entry containing 16 coefficients, e corresponding to the most significant bit to the least significant bit1481-16j～e1496-16jThe generation method is characterized in that the generation method comprises the following steps of calculating a first-order syndrome:
(1) initializing j to 0, register R0～R14Are all initialized to 0, wherein the register R0～R6Is equivalent to being initialized to e1497～e1503；
(2) Bit a of the input data segment vector16j～a16j+15Memory output e1481-16j～e1496-16jRegister R0～R6Output e1497-16j～e1503-16jThey output e in common1481-16j～e1503-16j；
(3)e1481-16j～e1503-16jThe successive 16 bits form 8 different vectors, 128 two-input AND gates and 128 two-input XOR gates perform vector multiplication, and the products are accumulated into a register R7～R14Performing the following steps;
(4)e1481-16j～e1487-16jis saved to register R0～R6Performing the following steps;
(5) j is increased by 1 if j<94, jumping to the step (2);otherwise, register R7～R14The content in (1) is d1496～d1503And finishing the calculation of the syndrome.
3. The method of claim 2, wherein the 8 bits d of the syndrome are calculated1496～d1503The following vector multiplication is followed:
Figure FDA0002998127670000021
Figure FDA0002998127670000022
Figure FDA0002998127670000023
Figure FDA0002998127670000024
Figure FDA0002998127670000025
Figure FDA0002998127670000026
Figure FDA0002998127670000027
Figure FDA0002998127670000028
wherein, the upper labelTRepresenting a vector transposition.
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