CN113078834B - Inverter based on digital delta-sigma and PID double-loop control and design method - Google Patents

Inverter based on digital delta-sigma and PID double-loop control and design method Download PDF

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CN113078834B
CN113078834B CN202110322972.2A CN202110322972A CN113078834B CN 113078834 B CN113078834 B CN 113078834B CN 202110322972 A CN202110322972 A CN 202110322972A CN 113078834 B CN113078834 B CN 113078834B
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sigma
inverter
pid
loop control
delta
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CN113078834A (en
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张宇
鲁博
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Huazhong University of Science and Technology
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H02M1/126—Arrangements for reducing harmonics from ac input or output using passive filters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration

Abstract

The invention discloses an inverter based on digital delta-sigma and PID double-loop control and a design method, belonging to the field of switching power supply, wherein the inverter comprises: the PID outer ring control module is used for sampling and decoding a voltage signal at a voltage sampling end on the output side of the inverter circuit and performing digital PID regulation; and the digital delta-sigma inner loop control module performs delta-sigma type AD sampling on the midpoint voltage signal of the bridge arm to obtain a single-bit data stream, performs filtering decoding when the data stream reaches M bits, performs filtering decoding on the latest M-bit data every time one bit is added to obtain a data point, integrates and quantizes the difference value between the signal output by the PID outer loop control module and the data point, and drives the inverter circuit to convert the direct current signal into an alternating current voltage signal. The filtering algorithm is simplified to reduce time delay, the delta-sigma type ADC noise shaping function ensures the accuracy of the sampled data in a medium-low frequency band, and the problems of low sampling speed, large time delay and low precision of the conventional digital delta-sigma control are solved. The double-loop control effectively improves the control precision and the response speed of the system.

Description

Inverter based on digital delta-sigma and PID double-loop control and design method
Technical Field
The invention belongs to the field of switching power supplies, and particularly relates to an inverter based on digital delta-sigma and PID double-loop control and a design method.
Background
High-precision alternating current power supplies have important applications in the fields of precision manufacturing, precision measurement and medical treatment. Among them, it is difficult to achieve high accuracy due to dead zone errors of the switching power supply, errors generated by the output filter, and the like. The delta-sigma modulation of the analog type in the audio field can effectively inhibit dead zones to realize a high-precision alternating-current power supply, but the analog type control is easy to be interfered when the power is high to influence the precision, and the portability is poor, so that certain design difficulty exists.
Digital delta-sigma modulation has high sampling requirements, requires high speed to acquire errors such as dead zones, requires low time delay to improve the stability of a loop and enable the loop to operate at a high switching frequency to ensure bandwidth, and requires high precision to control the accuracy of data acquisition of the loop. The existing sampling scheme usually adopts an error compensation mode or reduces the waveform precision requirement, the sampling conditioning circuit is complex in design and low in precision, the sampling isolation requirement is particularly considered, and the existing sampling scheme also has power level limitation. In addition, the error caused by the pure digital delta-sigma control on the filter is not effectively inhibited.
Disclosure of Invention
Aiming at the defects and improvement requirements of the prior art, the invention provides an inverter based on digital delta-sigma and PID double-loop control and a design method thereof, aiming at improving the sampling rate by using a delta-sigma type sampling ADC, simplifying a filtering and decoding algorithm to reduce time delay and integrally filtering high-frequency range errors, ensuring the accuracy of sampling data in required middle and low frequency ranges based on the noise shaping characteristics of the ADC, solving the problems of low speed, large time delay, low precision and insufficient bandwidth of a sampling scheme in the existing digital delta-sigma control and ensuring the high performance of the digital inner loop control.
To achieve the above object, according to an aspect of the present invention, there is provided an inverter based on digital delta-sigma and PID dual loop control, comprising: an inverter circuit; the PID outer ring control module is connected with the voltage sampling end on the output side of the inverter circuit and is used for outputting a voltage signal output by the inverter circuit after digital PID regulation; and the digital delta-sigma inner loop control module is connected with the bridge arm midpoint of the inverter circuit and the output end of the PID outer loop control module, and is used for performing delta-sigma type AD sampling on a voltage signal of the bridge arm midpoint to obtain a single-bit data stream, performing filter decoding on the M-bit data stream to obtain a data point when the bit number of the data stream reaches M bits, performing filter decoding on the latest obtained M-bit data stream to obtain a corresponding data point when a data stream is obtained, wherein M is the bit number of the data stream required by decoding, and integrating and quantizing the difference value between a signal output by the PID outer loop control module and the data point to convert the signal into a driving signal for output so as to drive the inverter circuit to convert a direct current signal into an alternating current voltage signal.
Furthermore, the digital delta-sigma inner loop control module comprises a first isolation sampling unit, a first filtering decoding unit, an integrator and a quantization comparator which are connected in sequence; the first isolation sampling unit is used for carrying out delta-sigma type AD sampling on the voltage signal at the midpoint of the bridge arm to obtain a single-bit data stream; the first filtering and decoding unit is used for filtering and decoding the data stream to obtain each data point; the integrator is used for integrating the difference value; the quantization comparator is used for comparing an integration result output by the integrator with a reference voltage and converting the comparison result into the driving signal to be output.
Furthermore, the first filtering and decoding unit utilizes a sinc3 filtering and decoding function to filter and decode the data stream, and the number of bits of the data stream used in the filtering process is between 1 and 50.
Furthermore, the digital delta-sigma inner loop control module further comprises an RC filter, and the middle point of the bridge arm is connected to the ground through the RC filter; the first isolation sampling unit is used for carrying out delta-sigma type AD sampling on the voltage signal of the middle point of the bridge arm after RC filtering.
Furthermore, the quantization comparator is a single-bit quantization comparator or a multi-bit quantization comparator, and the comparison link has hysteresis characteristics.
Furthermore, the inverter circuit is a half-bridge inverter circuit, a full-bridge inverter circuit or a multi-level inverter circuit, the output end of the inverter circuit is connected with the LC filter, and the voltage sampling end is the output end of the LC filter.
Furthermore, the PID outer loop control module comprises a second isolation sampling unit, a second filtering decoding unit and a PID control unit which are connected in sequence; the second isolation sampling unit and the second filtering decoding unit are respectively used for carrying out AD sampling and filtering decoding on the voltage signal output by the inverter circuit in sequence; and the PID control unit is used for carrying out digital PID adjustment on the difference value between the decoding result of the second filtering and decoding unit and a preset sinusoidal signal and then outputting the difference value.
Furthermore, the digital delta-sigma inner loop control module is a first-order control module or a high-order control module.
According to another aspect of the present invention, there is provided a method of designing an inverter as described above, including: s1, replacing an injection noise source in the digital delta-sigma inner loop control model with a variable gain lambda which changes within the range of 0 to + ∞, and establishing a transfer function of the inverter based on the replaced model; s2, calculating a characteristic equation corresponding to the transfer function, and calculating and drawing a root track of the characteristic equation according to the change of variable gain lambda in the characteristic equation; and S3, adjusting the proportional parameter, the integral parameter and the differential parameter in the PID outer loop control model until only one asymmetric root track in the root tracks of the characteristic equation passes through the virtual axis once along the direction of reducing the variable gain lambda.
Further, the characteristic equation is:
Figure BDA0002992122680000031
wherein L is inductance value of filter inductor in the inverter, C is capacitance value of filter capacitor in the inverter, r is comprehensive damping in the inverter, K is equivalent gain of the inverter and integrator, and T is1For time delay of integral quantization and inversion links, T2For the time delay of the feedback path, kfbFor the gain of the feedback path, kp、ki、kdThe proportional parameter, the integral parameter and the differential parameter are respectively.
Generally, by the above technical solution conceived by the present invention, the following beneficial effects can be obtained:
(1) for digital delta-sigma inner loop control, a delta-sigma isolated ADC and a mathematical analysis simplified filtering decoding algorithm are utilized, and one multi-bit data after filtering decoding is output after one single-bit data is sampled, so that the bandwidth of available data after decoding is increased, the anti-aliasing capability of the available data is improved, and the time delay of an inner loop sampling circuit is reduced to the lowest; the accuracy of the sampled data in the middle and low frequency bands required by the inverter is ensured by utilizing the noise shaping function of the ADC; in order to solve the data error caused by simplifying the filtering decoding algorithm, an integral link is arranged after filtering decoding to filter the error of the sampled data in a high-frequency band, so that the accuracy of the sampled data in the high-frequency band is ensured, and the problems of low sampling speed, large time delay and low sampling precision in the conventional digital delta-sigma control are solved;
(2) the digital delta-sigma inner ring can suppress errors such as dead zones with high performance, and the dead zones have equivalent resistance characteristics in the inverter, so that the resonance problem of a filter of the delta-sigma inner ring is more serious, therefore, on the basis of digital delta-sigma inner ring control, PID outer ring control is added to improve system damping, the error suppression capability of the system is further improved, the resonance influence of the filter is effectively suppressed, the influence of load current disturbance on the accuracy of the inverter is reduced, and the accuracy and the stability of the inverter are improved;
(3) the complexity of a simplified filtering and decoding algorithm, such as the filtering queue length using a sinc3 filtering and decoding function, is reduced from the traditional length of more than 100 to less than 10, so that the time delay is greatly reduced, the response speed is improved, the switching frequency is improved, the waveform quality of an inverter is improved, and a high-precision inverter power supply is realized;
(4) the method is used for analyzing and designing the stability problem of the digital double-loop control system, and provides a judgment basis and a design process, so that the feasibility of the high-precision digital delta-sigma and PID double-loop controlled inverter is ensured.
Drawings
FIG. 1A is a control block diagram of delta-sigma;
FIG. 1B is an input and error Bode plot for delta-sigma;
FIG. 1C is a schematic diagram of noise shaping at delta-sigma for an error equivalent to white noise;
fig. 2 is a schematic control block diagram of an inverter based on digital delta-sigma and PID dual-loop control according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a circuit structure corresponding to the control block diagram shown in FIG. 2;
FIG. 4A is a comparison of delta-sigma + PID control and prior art PWM + PID control input transfer function Bode plot;
FIG. 4B is a comparison of delta-sigma + PID control and prior art PWM + PID control output current transfer function Bode plot;
FIG. 4C is a comparison of the delta-sigma + PID control with the prior art PWM + PID control error transfer function Bode plot;
FIG. 5 is a waveform diagram of an experiment of an inverter based on delta-sigma and PID control according to an embodiment of the present invention;
fig. 6 is a waveform diagram of an experiment of an inverter based on delta-sigma and PID control when a load is suddenly applied according to an embodiment of the present invention.
The same reference numbers will be used throughout the drawings to refer to the same or like elements or structures, wherein:
1 is an inverter circuit, 2 is a PID outer loop control module, 21 is a second isolation sampling unit, 22 is a second filtering decoding unit, 23 is a PID control unit, 3 is a digital delta-sigma inner loop control module, 31 is a first isolation sampling unit, 32 is a first filtering decoding unit, 33 is an integrator, and 34 is a quantization comparator.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
In the present application, the terms "first," "second," and the like (if any) in the description and the drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
Fig. 2 is a schematic control block diagram of an inverter based on digital delta-sigma and PID (proportional-Integral-Differential, PID) dual-loop control according to an embodiment of the present invention. Referring to fig. 2, the inverter based on digital delta-sigma and PID dual-loop control in the present embodiment will be described in detail with reference to fig. 1A to 6.
The inverter based on digital delta-sigma and PID double-loop control comprises an inverter circuit 1, a PID outer loop control module 2 and a digital delta-sigma inner loop control module 3. And the PID outer ring control module 2 is connected with a voltage sampling end at the output side of the inverter circuit 1 and is used for outputting a voltage signal at the voltage sampling end at the output side of the inverter circuit 1 after digital PID regulation. The digital delta-sigma inner loop control module 3 is connected with a bridge arm midpoint of the inverter circuit 1 and an output end of the PID outer loop control module 2, and is used for performing delta-sigma type AD sampling on a voltage signal at the bridge arm midpoint to obtain a single-bit data stream, performing filter decoding on the M-bit data stream to obtain a data point when the number of bits of the data stream reaches M bits, and then performing filter decoding on the latest obtained M-bit data stream to obtain a corresponding data point when each data stream is obtained, wherein M is the number of bits of the data stream required for decoding, in this embodiment, M is set to a smaller value for increasing the response speed, for example, the range of M is set between 1 and 50; further, the digital delta-sigma inner loop control module 3 is further configured to integrate and quantize a difference between a signal output by the PID outer loop control module 2 and a data point to convert the difference into a driving signal for output, so as to drive the inverter circuit 1 to convert the direct current signal into an alternating current voltage signal.
The control block diagram for delta-sigma is shown in fig. 1A. Because the sampling frequency of the delta-sigma type ADC is very high, for example, the sampling rate is 20Mb/s when an AD7405 sampling chip is adopted, and the low-pass filter is designed to have anti-aliasing characteristics, the accuracy of the transfer function representation by using an analog formula is enough, and the analysis is more definite. In the control block diagram of fig. 1A, the integrator gain can be set to a large value to ensure good noise shaping. The delay element is used for controlling the output change rate of the delta-sigma, namely controlling the switching frequency in the inverter circuit 1. In physical terms, the input x (n) can be approximately regarded as a constant value in a plurality of regulation and control periods, the input value is subtracted from the quantized output value, the subtraction result is integrated by the integrator, the value after integration is guaranteed to fluctuate in a small range, and the pulse equivalent of the input to the output can be realized. From a mathematical point of view, in the control block diagram shown in fig. 1A, the transfer function of the input signal x (n) is:
Figure BDA0002992122680000071
the transfer function of the error signal e (n) is:
Figure BDA0002992122680000072
for analyzing the characteristics, the transfer function of the input signal and the error signal is plotted, wherein the delay T is set1＝2us、T26us, and the integral gain K105The delay limits the switching frequency up to 67.5kHz, and the bode diagram of this structure is shown in fig. 1B. Referring to fig. 1B, it can be seen that the transfer function of the input signal exhibits a low-pass characteristic, i.e., the input signal is attenuated little after delta-sigma modulation, and the error transfer function exhibits a high-pass filtering property, i.e., low-band errors are suppressed, which is referred to as noise shaping, as shown in fig. 1C.
Therefore, errors such as dead zones of the switching power supply can be effectively inhibited by using a noise shaping principle through delta-sigma inner loop control; however, the delta-sigma control does not consider the filter effect, and the system damping is smaller, so that the system damping is improved through PID control, the error is further inhibited, meanwhile, the influence of the filter is effectively inhibited, the error caused by load current disturbance is inhibited, better transient performance and steady-state precision can be obtained, and the digital control enables the adjustment to be more flexible.
The inverter circuit 1 is a half-bridge inverter circuit, a full-bridge inverter circuit or a multi-level inverter circuit, the output end of the inverter circuit is connected with an LC filter, the output end of the LC filter is a voltage sampling end on the output side of the inverter circuit 1, and the input end of the PID outer ring control module 2 is connected with the output end of the LC filter. Taking inverter circuit 1 as a voltage-type half-bridge inverter circuit as an example, referring to fig. 2, the half-bridge inverter circuit is composed of two switching tubes and a primary side dc voltage-stabilizing capacitor C2And C3The inversion function is realized by alternately controlling the on-off of the two switching tubes.
The PID outer loop control module 2 comprises a second isolated sampling unit 21, a second filtering decoding unit 22 and a PID control unit 23 which are connected in sequence. The second isolation sampling unit 21 is configured to perform AD sampling on a voltage signal at the voltage sampling end on the output side of the inverter circuit 1. The second filtering and decoding unit 22 is configured to filter and decode the sampling result of the second isolated sampling unit 21. The PID control unit 23 is configured to perform digital PID adjustment on the difference between the decoding result of the second filtering and decoding unit 22 and the preset sinusoidal signal, and output the difference, and transmit the output result to the digital delta-sigma inner loop control module 3. The PID control unit 23 is a digital sine wave in an FPGA chip or a DSP chip, and PID control and communication are realized by using the FPGA or the DSP.
Taking the PID outer ring control module 2 formed by the second isolation sampling unit 21 as the AD7405 isolation sampling chip and the PID control unit 23 as the FPGA control as an example, the control process is as follows: the AD7405 samples output voltage from the output side of the LC filter, utilizes the FPGA to adjust PID control parameters, realizes PID control, and inputs the PID control to an integrator in the digital delta-sigma inner loop control module 3, thereby introducing the output filter into feedback control.
The digital delta-sigma inner loop control module 3 comprises a first isolation sampling unit 31, a first filtering decoding unit 32, an integrator 33 and a quantization comparator 34 which are connected in sequence.
The first isolation sampling unit 31 selects, for example, a sampling chip AD7405 with an integrated isolation function, and is configured to perform delta-sigma type AD sampling on the voltage signal at the midpoint of the bridge arm to obtain a single-bit data stream. Further, the digital delta-sigma inner loop control module 3 further includes an RC filter, the RC filter is, for example, a first-order RC filter, the bridge arm midpoint is connected to the ground through the RC filter, and the first isolation sampling unit 31 performs delta-sigma type AD sampling on the voltage signal at the bridge arm midpoint after the RC filtering.
The first isolation sampling unit 31 is a delta-sigma type ADC, a magnetic isolation module can be integrated in the first isolation sampling unit, or an external isolation chip is connected to transmit data, the first isolation sampling unit can sample at a high speed and convert the data into a single-bit data stream corresponding to a sampling rate.
The first filtering and decoding unit 32 is configured to filter and decode the data stream sampled by the first isolation sampling unit 31 to obtain each available data point. The first filtering and decoding unit 32 is different from the conventional scheme that a one-bit data stream output by a delta-sigma type ADC is compressed in time and waits, and then a multi-bit data is popped up at a low speed, but the one-bit data is input into an overall filtering queue, so that a filtered and decoded multi-bit data can be output every time a single-bit data is input into the queue. Specifically, when the data stream sampled by the first isolation sampling unit 31 reaches M bits, the first filtering and decoding unit 32 performs filtering and decoding on the M-bit data stream to obtain an available data point, and then each sampling of the first isolation sampling unit 31 obtains a data stream, and the first filtering and decoding unit 32 performs filtering and decoding on the M-bit data stream obtained latest to obtain a corresponding available data point.
According to the embodiment of the present invention, the first filtering and decoding unit 32 performs filtering and decoding on the data stream by using a sinc3 filtering and decoding function, wherein the number of bits of the data stream used in the filtering process is between 1 and 50, and the number of bits of the data stream used in the filtering process is, for example, 15, 10, etc. Because the integrator 33 is arranged in the digital delta-sigma inner ring control module 3, the integration has the capability of filtering high-frequency noise, the design of decoding and filtering after single-bit data is very simple, and the method is different from the method that the traditional filtering mode of a delta-sigma type ADC requires more than 100 single-bit data to filter out and obtain one piece of data, the length of the data in the integral filtering queue is smaller and between 1 and 50, and the data is not filtered when 1 is used, so that the time delay is greatly reduced, the response speed is improved, the switching frequency is improved, and the waveform quality is improved, and the high-precision inverter power supply is realized.
The integrator 33 is configured to integrate a difference between the signal output by the PID outer loop control module 2 and the data point output by the first filtering and decoding unit 32, and output the integration result to the quantization comparator 34. The quantization comparator 34 is configured to compare the integration result output by the integrator 33 with a reference voltage to generate a quantization value, convert the quantization value into a driving signal corresponding to the driver, and output the driving signal to the driving circuit, so that the driving circuit drives the switching tube of the inverter circuit 1 according to the driving signal, so that the inverter circuit 1 converts the dc signal into a square wave, that is, performs delta-sigma modulation on the signal output by the PID outer loop control module, and the square wave passes through the filter to obtain a desired high-precision ac sinusoidal voltage signal.
The integrator 33 may be designed as an ideal integrator or a lossy integrator, and may be a first-order integrator or a high-order integrator, so that the digital delta-sigma inner loop control module 3 implements corresponding first-order control or high-order control. The quantization comparator 34 is a single-bit quantization comparator or a multi-bit quantization comparator, and is determined according to the number of levels of the inverter circuit 1. In addition, the comparing element of the quantization comparator 34 may be configured to have a certain hysteresis characteristic or a certain time delay characteristic.
The control process of the digital delta-sigma inner loop control module 3 is as follows: the signal at the midpoint of the bridge arm of the inverter circuit 1 is low-pass filtered by an RC filter, sampled by an AD7405 chip, filtered and decoded by a first filtering and decoding unit 32, and subtracted from the signal output by the PID outer loop control module 2, the subtraction result is integrated by an integrator 33 and output to a quantization comparator 34, and the quantization comparator 34 compares the integrated value with a reference voltage (for example, zero level) to generate a high-low level signal, so that a driving chip controls a switching tube in the inverter circuit 1 according to the high-low level signal to realize negative feedback. And realizing delta-sigma control and communication by using an FPGA or a DSP. Further, the digital delta-sigma inner loop control module 3 controls the switching frequency and the duty ratio of each switching tube in the inverter circuit 1 according to the generated driving signal.
Fig. 4A-4C are graphs showing the control effect of the delta-sigma + PID control of the present embodiment compared to the prior art PWM + PID control. Referring to fig. 4A, it can be seen that the frequency response of the delta-sigma control input to the output becomes flatter after the PID control is added as in the PWM control; referring to fig. 4B, it can be seen that after the delta-sigma control is added with the PID control as with the PWM, the error of the output current with respect to the output voltage is effectively suppressed, and the resonance spike is eliminated; referring to fig. 4C, it can be seen that the delta-sigma + PID control has no error resonance peak, and has better error suppression performance compared with open loop PWM, PWM + PID, or delta-sigma control; therefore, the delta-sigma + PID control has better error suppression capability than the traditional PWM and PWM + PID control, can better suppress errors and the influence caused by output current compared with the simple delta-sigma control, can also suppress resonance peak caused by a filter, and theoretically can be considered to have the best high-precision potential. Referring to fig. 5, it can be seen that the delta-sigma + PID control in this embodiment can reduce the total harmonic distortion of the output voltage to 0.091%, and has a good control effect. Referring to fig. 6, it can be seen that, under the condition from no load to sudden load, the output voltage is quickly stabilized, has good transient characteristics, and has almost no steady-state error, and can be used as a high-precision ac voltage source.
The embodiment of the invention also provides a method for designing the inverter based on the digital delta-sigma and PID double-loop control, which includes operation S1-operation S3.
In operation S1, an injection noise source in the digital delta-sigma inner loop control model is replaced with a variable gain λ varying in a range of 0 to + ∞, and a transfer function of the inverter is established based on the replaced model.
In operation S2, a characteristic equation corresponding to the transfer function is calculated, and a root trajectory of the characteristic equation is calculated and drawn according to a variation of the variable gain λ in the characteristic equation, where the characteristic equation is:
Figure BDA0002992122680000111
wherein L is inductance value of filter inductor in inverter, C is capacitance value of filter capacitor in inverter, r is comprehensive damping in inverter, K is equivalent gain of inverter and integrator, and T is equivalent gain of inverter and integrator1For time delay of integral quantization and inversion links, T2For the time delay of the feedback path, kfbFor the gain of the feedback path, kp、kiAnd kdRespectively a proportional parameter, an integral parameter and a differential parameter.
In operation S3, the proportional, integral, and derivative parameters in the PID outer loop control model are adjusted until only one asymmetric root locus among the root loci of the characteristic equation crosses the imaginary axis once in a direction in which the variable gain λ decreases.
It should be noted that, for the root locus symmetrical to the upper plane and the lower plane, only the unilateral root locus (and the root locus of the upper plane or the root locus of the lower plane) is considered, and then in operation S3, the proportional parameter, the integral parameter and the differential parameter in the PID outer-loop control model are adjusted until the unilateral root locus crosses the imaginary axis once along the direction in which the variable gain λ decreases.
In this embodiment, the PID outer-loop control module 2 is designed based on the proportional parameter, the integral parameter, and the differential parameter in the designed PID outer-loop control model, and the overall design based on the inverter is further completed, and the inverter formed finally is as shown in fig. 3.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (10)

1. An inverter based on digital delta-sigma and PID double-loop control is characterized by comprising:
an inverter circuit (1);
the PID outer ring control module (2) is connected with a voltage sampling end on the output side of the inverter circuit (1) and is used for carrying out digital PID adjustment on the voltage signal output by the inverter circuit (1) and then outputting the voltage signal;
the digital delta-sigma inner loop control module (3) is connected with a bridge arm midpoint of the inverter circuit (1) and an output end of the PID outer loop control module (2) and is used for carrying out delta-sigma type AD sampling on a voltage signal of the bridge arm midpoint to obtain a single-bit data stream, carrying out filtering decoding on the M-bit data stream to obtain a data point when the bit number of the data stream reaches M bits, carrying out filtering decoding on the latest obtained M-bit data stream to obtain a corresponding data point when each data stream is obtained, wherein M is the bit number of the data stream required by decoding, and integrating and quantizing a difference value between a signal output by the PID outer loop control module (2) and the data point to convert the signal into a driving signal for outputting so as to drive the inverter circuit (1) to convert a direct current signal into an alternating current voltage signal.
2. The inverter according to claim 1, wherein the digital delta-sigma inner loop control module (3) comprises a first isolation sampling unit (31), a first filter decoding unit (32), an integrator (33) and a quantization comparator (34) which are connected in sequence;
the first isolation sampling unit (31) is used for carrying out delta-sigma type AD sampling on the voltage signal at the midpoint of the bridge arm to obtain a single-bit data stream; the first filtering and decoding unit (32) is used for filtering and decoding the data stream to obtain each data point; the integrator (33) is used for integrating the difference value; the quantization comparator (34) is used for comparing the integration result output by the integrator (33) with a reference voltage and converting the comparison result into the driving signal to be output.
3. The inverter according to claim 2, characterized in that the first filter decoding unit (32) filter decodes the data stream using a sinc3 filter decoding function, and the number of bits of the data stream used in the filtering process is between 1 and 50.
4. The inverter according to claim 2, characterized in that the digital delta-sigma inner loop control module (3) further comprises an RC filter through which the bridge leg midpoint is connected to ground;
the first isolation sampling unit (31) is used for carrying out delta-sigma type AD sampling on the voltage signal of the middle point of the bridge arm after RC filtering.
5. The inverter of claim 2, wherein the quantization comparator (34) is a single-bit quantization comparator or a multi-bit quantization comparator, and the comparison element has hysteresis characteristics.
6. The inverter according to claim 1, wherein the inverter circuit (1) is a half-bridge inverter circuit, a full-bridge inverter circuit or a multilevel inverter circuit, the output terminal is connected to an LC filter, and the voltage sampling terminal is the output terminal of the LC filter.
7. The inverter according to claim 1, characterized in that the PID outer loop control module (2) comprises a second isolated sampling unit (21), a second filtering decoding unit (22) and a PID control unit (23) connected in sequence;
the second isolation sampling unit (21) and the second filtering decoding unit (22) are respectively used for carrying out AD sampling and filtering decoding on the voltage signal output by the inverter circuit (1) in sequence; and the PID control unit (23) is used for performing digital PID adjustment on the difference value between the decoding result of the second filtering and decoding unit (22) and a preset sinusoidal signal and outputting the difference value.
8. Inverter according to any of claims 1 to 7, characterized in that the digital delta-sigma inner loop control module (3) is a first order control module or a higher order control module.
9. A method of designing an inverter according to any one of claims 1 to 8, comprising:
s1, replacing an injection noise source in the digital delta-sigma inner loop control model with a variable gain lambda which changes within the range of 0 to + ∞, and establishing a transfer function of the inverter based on the replaced model;
s2, calculating a characteristic equation corresponding to the transfer function, and calculating and drawing a root track of the characteristic equation according to the change of variable gain lambda in the characteristic equation;
and S3, adjusting the proportional parameter, the integral parameter and the differential parameter in the PID outer loop control model until only one asymmetric root track in the root tracks of the characteristic equation passes through the virtual axis once along the direction of reducing the variable gain lambda.
10. The method of claim 9, wherein the characteristic equation is:
Figure FDA0002992122670000031
wherein L is inductance value of filter inductor in the inverter, C is capacitance value of filter capacitor in the inverter, r is comprehensive damping in the inverter, K is equivalent gain of the inverter and integrator, and T is1For time delay of integral quantization and inversion links, T2For the time delay of the feedback path, kfbFor the gain of the feedback path, kp、kiAnd kdThe proportional parameter, the integral parameter and the differential parameter are respectively.
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