CN113076090B - Side channel safety protection-oriented loop statement execution method and device - Google Patents
Side channel safety protection-oriented loop statement execution method and device Download PDFInfo
- Publication number
- CN113076090B CN113076090B CN202110443636.3A CN202110443636A CN113076090B CN 113076090 B CN113076090 B CN 113076090B CN 202110443636 A CN202110443636 A CN 202110443636A CN 113076090 B CN113076090 B CN 113076090B
- Authority
- CN
- China
- Prior art keywords
- instruction
- loop
- counter
- extended
- inst
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/30—Creation or generation of source code
- G06F8/37—Compiler construction; Parser generation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/40—Transformation of program code
- G06F8/41—Compilation
- G06F8/44—Encoding
- G06F8/447—Target code generation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30047—Prefetch instructions; cache control instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30065—Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
Abstract
The invention discloses a side channel safety protection-oriented loop statement execution method and a side channel safety protection-oriented loop statement execution device, wherein the side channel safety protection-oriented loop statement execution method comprises the steps of pre-identifying a source code of a target program or a loop body in a target code, and inserting an extended loop instruction based on an extensible instruction set architecture coding specification in front of each section of the loop body to obtain the target program using the extended loop instruction; when an extended loop instruction is encountered while executing a target program using the extended loop instruction, a loop body after the extended loop instruction is deterministically executed based on the extended loop instruction. The invention can resist branch prediction attack, not only ensures safety, but also eliminates huge performance loss caused by the prior defense measures to the circulation, controls the increase of the code amount to be only one in each circulation compared with the circulation expansion, and has less modification amount to the prior program.
Description
Technical Field
The invention belongs to the field of processor architecture safety, and particularly relates to a side channel safety protection-oriented loop statement execution method and device.
Background
The branch prediction technology is a key technology used for improving the program execution efficiency of a modern processor, the pipeline delay caused by branch instructions is greatly reduced, and the high-accuracy branch prediction can bring great performance improvement to the processor. But recently exposed to the ghost (spectrum) family of vulnerabilities, showing that the design of typical modern processor architectures presents serious security problems that pose a significant security threat to processor users. The ghost vulnerability family utilizes misleading training of branch prediction technology, so that a processor speculates and executes a code sequence elaborately constructed by an attacker, unauthorized access to data protected by various processors and operating system security mechanisms is achieved, and data is further leaked by utilizing side channels such as a cache.
The most fundamental defense against such attacks is protection from the source, that is, protection from malicious triggering of speculative execution, and the attacker cannot successfully and transiently execute unauthorized access code. The existing measures for defending the ghost bug at the source level are to prevent branch prediction of all branch instructions, the main method at the hardware level is to forbid the branch prediction, and the main method at the software level is to insert a nonce instruction after the branch instruction during compiling. The defense measures are equivalent to the steps that after the processor executes the branch instruction, the pipeline is suspended, and the branch instruction is executed after the branch result of the branch instruction is determined, so that the processor is equivalent to the processor without adopting the branch prediction technology, the program execution efficiency is greatly reduced, the huge performance improvement brought by the branch prediction technology is sacrificed, and the cost is high. Many loop statements are contained in the program, which is also a necessary condition for an attacker to construct a "ghost" attack, and the existing measures ensure processor security by completely disabling branch prediction, but cause huge overhead when executing branch instructions, especially branch instructions in a loop.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: the invention can resist branch prediction attack, not only ensures safety, but also eliminates huge performance loss caused by the existing defense measures to the loop, reduces the expenditure for executing branch instructions, particularly branch instructions in the loop, controls the increase of code amount to only one loop compared with loop expansion, and has less modification to the existing program.
In order to solve the technical problems, the invention adopts the technical scheme that:
a side channel safety protection-oriented loop statement execution method comprises the following steps:
1) identifying a loop body in a source code or a target code of a target program in advance, and inserting an extended loop instruction based on an extensible instruction set architecture coding specification in front of each section of loop body to obtain the target program using the extended loop instruction;
2) when an extended loop instruction is encountered while executing a target program using the extended loop instruction, a loop body after the extended loop instruction is deterministically executed based on the extended loop instruction.
Optionally, the encoding information of the extended loop instruction in step 1) includes the loop iteration number of the loop body after the extended loop instruction and the number of instructions in the loop body.
Optionally, the maximum number of supported instructions in loop of the extended loop instruction is 2a1, where a is the bit width of the number of instructions in the loop body in the extended loop instruction.
Optionally, the pre-identifying the source code or the loop body in the object code of the object program in step 1) refers to: identifying the loop iteration times and the number of instructions in loop bodies of each loop body by a compiler aiming at a source code of a target program, generating an extended loop instruction based on the extensible instruction set architecture coding specification according to the loop iteration times and the number of instructions in the loop bodies, and inserting the extended loop instruction into the front of each corresponding loop body to finally obtain the target program using the extended loop instruction; or, the optimizer identifies the loop iteration times and the number of instructions in each loop body aiming at the target code of the target program, generates an extended loop instruction based on the extensible instruction set architecture coding specification according to the loop iteration times and the number of instructions in the loop bodies, and inserts the extended loop instruction into each corresponding loop body, so as to finally obtain the target program using the extended loop instruction.
Optionally, the step 2) of deterministically executing the loop body after the extended loop instruction based on the extended loop instruction further includes a step of caching the extended loop instruction based on the specified loop instruction buffer LIB.
Optionally, when the loop body after the extended loop instruction is executed deterministically based on the extended loop instruction in step 2), the method further includes a step of recording an execution state of the loop body based on a loop state register set, where the loop state register set includes: a loop _ counter for storing the residual iteration count of the current execution loop; an in-loop instruction number register inst _ counter for storing the in-loop instruction number of the loop body; a loaded instruction number register load _ counter for storing the number of instructions loaded into the circular instruction buffer; and the currently executed instruction address register inst _ pointer is used for storing an instruction address of the currently executed loop instruction, wherein the instruction address of the currently executed loop instruction comprises two parts, one part is an instruction address at the first part of the loop body, and the other part is an offset of the currently executed instruction address relative to the instruction address at the first part of the loop body.
Optionally, the step of executing the target program using the extended loop instruction in step 2) includes:
2.1) judging whether a loop _ counter of a residual iteration number register of a loop instruction buffer area is 0, if so, judging that the previous loop has run completely or has not executed the loop, and skipping to execute the next step; skipping to execute step 2.5);
2.2) grabbing the instruction I from the instruction Cache I-Cache;
2.3) judging whether the captured instruction I is an extended loop instruction, if so, firstly decoding and identifying the loop iteration times k and the instruction number n in a loop body of the extended loop instruction, and then executing initialization of a loop state register set: initializing a residual iteration count register loop _ counter to be a loop iteration count k of an extended loop instruction, wherein a loop internal instruction number register inst _ counter is an instruction number n in the loop of the extended loop instruction, a loaded instruction number register load _ counter is 0, and a currently executed instruction address register inst _ pointer is 0;
2.4) updating the value of the program counter PC to be the address of the next instruction, and skipping to execute the step 2.1);
2.5) judging whether a loaded instruction number register load _ counter of the loop instruction buffer area is smaller than an instruction number register inst _ counter in the loop body, if so, judging that the loop body is currently in the execution process of the first iteration of the loop body and the instruction of the loop body is not loaded completely, and continuously grabbing an instruction I from the instruction Cache I-Cache; if not, judging that the current loop is in the execution process of the second round iteration or the subsequent round iteration of the loop body, and skipping to execute the step 2.7);
2.6) the fetched instruction I enters a pipeline, the fetched instruction I is written into the first load _ counter buffer slot of the loop instruction buffer LIB, the value of the loaded instruction number register load _ counter is added with 1, and the step 2.4) is executed by jumping;
2.7) fetching an instruction I [ inst _ pointer ] from a loop instruction buffer LIB, wherein the inst _ pointer is the offset of an address register inst _ pointer of the current execution instruction;
2.8) the fetched instruction I [ inst _ pointer ] enters a pipeline, and the value of the currently executed instruction address register inst _ pointer is updated to be: (inst _ pointer +1)% inst _ counter, wherein inst _ pointer is the offset of the currently executed instruction address register inst _ pointer, and inst _ counter is the value of the instruction number register inst _ counter in the loop;
2.9) judging whether the value of an instruction number register inst _ counter in a loop body is 0, if so, subtracting 1 from the value of a residual iteration number register loop _ counter; jump execution step 2.1).
In addition, the invention also provides a side channel safety protection-oriented loop statement execution device, which comprises:
the instruction Cache I-Cache is used for caching common instructions;
the loop instruction buffer LIB is used for caching the instructions of the loop body;
the loop state register group is used for recording the instruction execution state of the loop body, and comprises a residual iteration number register loop _ counter which is used for storing the residual iteration number of the current execution loop; an in-loop instruction number register inst _ counter for storing the in-loop instruction number of the loop body; a loaded instruction number register load _ counter for storing the number of instructions loaded into the circular instruction buffer; the current execution instruction address register inst _ pointer is used for storing an instruction address of a current execution cycle instruction, wherein the instruction address of the current execution cycle instruction comprises two parts, one part is an instruction address at the first part of a cycle body, and the other part is the offset of the current execution instruction address relative to the instruction address at the first part of the cycle body;
the instruction selector is used for selecting to fetch instructions from the instruction Cache I-Cache or the circular instruction buffer LIB according to the instruction execution state of the circular body recorded in the circular state register group;
the pre-decoder is used for decoding the taken instruction to judge whether the taken instruction is an extended cycle instruction or not, and if the extended cycle instruction is encountered and the instruction of the cycle body corresponding to the extended cycle instruction is not completely loaded, a selection signal for controlling the program counter selection module is sent out to continue loading the instruction of the cycle body corresponding to the extended cycle instruction; if a non-expansion cycle instruction is encountered, an indication signal of the non-expansion cycle instruction is sent out;
the program counter selection module is used for grabbing instructions from the instruction Cache I-Cache according to a selection signal, putting the instructions into the circulating instruction buffer LIB and entering a production line;
a control module to perform a specified branch prediction defense upon receipt of an indication of a non-expanded loop instruction: pausing the pipeline or inserting an entry instruction, and waiting for determining a branch result and a conditional branch instruction target address; after the branch result and the conditional branch instruction target address are determined, the conditional branch instruction target address is used as a new program counter value, and the pipeline is restored.
In addition, the invention also provides a side channel safety protection-oriented loop statement execution device which comprises a microprocessor and a memory which are connected with each other, wherein the microprocessor is programmed or configured to execute the steps of the side channel safety protection-oriented loop statement execution method.
Furthermore, the present invention also provides a computer-readable storage medium, in which a computer program is stored, the computer program being programmed or configured to execute the aforementioned side channel security guard-oriented loop statement execution method.
Compared with the prior art, the invention mainly has the following advantages:
1. the invention relates to a side channel safety protection-oriented loop statement execution method, which comprises the steps of identifying a source code of a target program or a loop body in a target code in advance, and inserting an extended loop instruction based on an extensible instruction set architecture coding specification in front of each section of loop body to obtain the target program using the extended loop instruction; when an extended loop instruction is encountered while executing a target program using the extended loop instruction, a loop body after the extended loop instruction is deterministically executed based on the extended loop instruction. The invention can resist branch prediction attack, not only ensures safety, but also eliminates huge performance loss caused by the prior defense measures to circulation,
2. the side channel safety protection-oriented loop statement execution method comprises the steps of identifying a loop body in a source code or a target code of a target program in advance, inserting an extended loop instruction based on an extensible instruction set architecture coding specification in front of each section of the loop body, and controlling the increase of code quantity to be only one in each loop compared with loop expansion, so that the modification quantity of the existing program is small.
Drawings
FIG. 1 is a schematic diagram of a basic flow of a method according to an embodiment of the present invention.
FIG. 2 is a schematic structural diagram of an apparatus according to an embodiment of the present invention.
FIG. 3 is a block diagram of an extended loop instruction according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating an implementation of an apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the technical solution of the present disclosure clearer, the following takes RISC-V instruction set architecture as an example to further describe in detail the loop statement execution method and apparatus for defending against speculative execution attacks in the present invention. Needless to say, the loop statement execution method and apparatus for defending against speculative execution attacks in the present invention are not only applicable to RISC-V instruction set architectures, but can be widely applied to all instruction set architectures that can perform instruction expansion.
As shown in fig. 1, the method for executing a loop statement facing side channel security protection in this embodiment includes:
1) identifying a loop body in a source code or a target code of a target program in advance, and inserting an extended loop instruction based on an extensible instruction set architecture coding specification in front of each section of loop body to obtain the target program using the extended loop instruction;
2) when an extended loop instruction is encountered while executing a target program using the extended loop instruction, a loop body after the extended loop instruction is deterministically executed based on the extended loop instruction.
Referring to fig. 3, the encoding information of the extended loop instruction in step 1) of this embodiment includes the loop iteration number of the loop body after the extended loop instruction and the number of instructions in the loop body. Based on the encoding specification of the RISC-V instruction set of the expandable instruction set architecture in this embodiment, bits 1 to 7 of the expanded loop instruction are the basic operation code 0001011, bits 8 to 16 are the field of the number of instructions in the loop, which is used to store the immediate n (i.e., the number of instructions in the loop), bits 17 to 32 are the field of the number of loop iterations, which is used to store the immediate k (i.e., the number of loop iterations),
in this embodiment, the number of instructions in the loop body that are maximally supported by the extended loop instruction is 2a1, where a is the bit width of the number of instructions in the loop body in the extended loop instruction. And obtaining the value of the maximum supported instruction number MAX in the loop body of the extended loop instruction according to the bit width a of the instruction number in the loop body of the extended loop instruction.
As an alternative implementation, in this embodiment, the extensible instruction set is a RISC-V instruction set architecture, and the extended loop instruction based on the encoding specification of the extensible instruction set architecture is named as a loop instruction. The step of generating the extended loop instruction based on the extensible instruction set architecture encoding specification mainly comprises the following steps: defining an extended loop instruction, and identifying a code sequence which can use the extended loop instruction in the code of the target program; a machine instruction program (target program) using an extended loop instruction is generated. It should be noted that the extensible instruction set architecture in the present embodiment is not dependent on a specific extensible instruction set architecture, and similar instructions can be implemented on any extensible instruction set architecture. Moreover, the format of the loop instruction in this embodiment is only one of the feasible instruction formats, and may also be implemented by selecting a different instruction format.
The RISC-V instruction has a basic instruction set of 32 bits, where the [1:0] must be 11, the [6:2] bits represent the basic opcode, and when the [6:2] bits are 00010, 01010, 10110, or 11110, the instruction is a custom extended instruction. As shown in the schematic diagram of the instruction format of the extended loop instruction in FIG. 3, bits [6:2] are selected to be 00010 as the basic operation code, and bits [1:0] are selected to be 11; [15:7] is a loop body instruction number field, which has 9 bits in total and indicates that the maximum number MAX of loop body instructions supported in this embodiment is 512; [31:16] is a loop iteration number field, which has 16 bits and indicates that the maximum loop iteration number supported in the present embodiment is 65536. The maximum instruction number and the maximum loop iteration number of the loop body supported in the embodiment are suitable for most of the maximum memory loops, the pre-decoding logic is simple, and low-cost overhead can be guaranteed in the embodiment.
When the code sequence of the extended loop instruction can be used in the code of the target program, the source code or the target code of the target program can be selected as the object of recognition, and therefore the extended loop instruction can be generated by compiling the source code or can be inserted by recognizing and re-inserting the loop in the binary program. The step 1) of identifying the source code or the loop body in the object code of the object program in advance refers to one of the mode 1 or the mode 2: mode 1: identifying the loop iteration times and the number of instructions in loop bodies of each loop body by a compiler according to the source code of the target program, generating an extended loop instruction based on the structural coding specification of an extensible instruction set system according to the loop iteration times and the number of instructions in the loop bodies, and inserting the extended loop instruction into the corresponding loop bodies to finally obtain the target program using the extended loop instruction; mode 2: and identifying the loop iteration times and the number of instructions in each loop body by the optimizer aiming at the target code of the target program, generating an extended loop instruction based on the extensible instruction set architecture coding specification according to the loop iteration times and the number of instructions in the loop bodies, and inserting the extended loop instruction into each corresponding loop body to finally obtain the target program using the extended loop instruction.
Correspondingly, when the loop iteration number and the instruction number in each loop body are identified, if a compiler is used to directly generate a binary program containing loop instructions from source codes in the embodiment, the reconstructed compiler identifies the loop iteration number and the loop body code sequence number in the source codes; if the binary program containing the loop instruction is generated from the original binary program in the embodiment, the loop times and the loop body code sequence number in the original binary program are identified by using the optimizer, wherein the original binary program is the binary program generated by the existing compiler. When generating an object program using an extended loop instruction, generating a binary program containing the extended loop instruction by using a reconstructed compiler or optimizer; the upper limit of the number of the instruction sequences in the code sequence which can be optimized into the extended loop instruction is determined by the bit width of a field of the number of the code sequences in the extended loop instruction; and if the instruction sequence in the loop body is less than or equal to the upper limit, inserting an extended loop instruction before the loop body starts, wherein the loop number field of the extended loop instruction is determined by the loop number of the loop body, and the instruction number field is determined by the number of the instruction sequence in the loop body.
In this embodiment, when the loop body after the extended loop instruction is executed deterministically based on the extended loop instruction in step 2), the method further includes a step of caching the extended loop instruction based on a specified loop instruction buffer LIB.
In this embodiment, when the loop body after the extended loop instruction is executed deterministically based on the extended loop instruction in step 2), the method further includes a step of recording an execution state of the loop body based on a loop state register set, where the loop state register set includes:
a loop _ counter for storing the residual iteration count of the current execution loop;
an instruction number register inst _ counter in the loop body, which is used for storing the instruction number in the loop body of the loop body;
a loaded instruction number register load _ counter for storing the number of instructions loaded into the circular instruction buffer;
and the currently executed instruction address register inst _ pointer is used for storing an instruction address of the currently executed loop instruction, wherein the instruction address of the currently executed loop instruction comprises two parts, one part is an instruction address at the first part of the loop body, and the other part is an offset of the currently executed instruction address relative to the instruction address at the first part of the loop body.
In this embodiment, the step of executing the target program using the extended loop instruction in step 2) includes:
2.1) judging whether a loop _ counter of a residual iteration number register of a loop instruction buffer area is 0, if so, judging that the previous loop has been operated or not, and skipping to execute the next step; skipping to execute step 2.5);
2.2) grabbing the instruction I from the instruction Cache I-Cache;
2.3) judging whether the captured instruction I is an extended loop instruction, if so, firstly decoding and identifying the loop iteration times k and the instruction number n in a loop body of the extended loop instruction, and then executing initialization of a loop state register set: initializing a residual iteration count register loop _ counter to be a loop iteration count k of an extended loop instruction, wherein a loop internal instruction number register inst _ counter is an instruction number n in the loop of the extended loop instruction, a loaded instruction number register load _ counter is 0, and a currently executed instruction address register inst _ pointer is 0;
2.4) updating the value of the program counter PC to be the address of the next instruction, and skipping to execute the step 2.1);
2.5) judging whether a loaded instruction number register load _ counter of the loop instruction buffer area is smaller than an instruction number register inst _ counter in the loop body, if so, judging that the loop body is currently in the execution process of the first iteration of the loop body and the instruction of the loop body is not loaded completely, and continuously grabbing an instruction I from the instruction Cache I-Cache; if not, judging that the current loop is in the execution process of the second round iteration or the subsequent round iteration of the loop body, and skipping to execute the step 2.7);
2.6) the fetched instruction I enters a pipeline, the fetched instruction I is written into the first load _ counter buffer slot of the loop instruction buffer LIB, the value of the loaded instruction number register load _ counter is added with 1, and the step 2.4) is executed by jumping;
2.7) fetching an instruction I [ inst _ pointer ] from a loop instruction buffer LIB, wherein the inst _ pointer is the offset of an address register inst _ pointer of the current execution instruction;
2.8) the fetched instruction I [ inst _ pointer ] enters a pipeline, and the value of the currently executed instruction address register inst _ pointer is updated to be: (inst _ pointer +1)% inst _ counter (which means modified to the first instruction if the current inst _ pointer points to the last instruction), where inst _ pointer is the offset of the currently executing instruction address register, inst _ pointer, and inst _ counter is the value of the instruction number in loop register, inst _ counter;
2.9) judging whether the value of an instruction number register inst _ counter in the loop is 0, if so, subtracting 1 from the value of a residual iteration number register loop _ counter; the jump performs step 2.1).
In summary, the side channel security protection-oriented loop statement execution method of the embodiment is applicable to an instruction set architecture of an extensible instruction, and can deterministically execute a loop meeting conditions by matching with a loop buffer, so that not only is the security ensured, but also the huge performance loss caused by the existing defense measures to the loop is eliminated, and compared with loop expansion, the increase of the code amount is controlled to be only one per loop. The side channel safety protection-oriented loop statement execution method is based on an extensible instruction set architecture, through the extension of an extended loop instruction (loop instruction) and the matching of the design of a low-cost extended loop instruction buffer area, deterministic loop execution with zero overhead is achieved, circulation is not only guaranteed to be used by an attacker for triggering the spectrum attack, but also the efficiency of loop execution is greatly improved, and performance loss is greatly reduced compared with the existing defense measures.
As shown in fig. 3, the apparatus for executing a loop statement facing side channel security protection in this embodiment includes:
the instruction Cache I-Cache is used for caching common instructions; the instruction Cache I-Cache is similar to the instruction Cache in the existing modern processor system structure and can also be a Cache or a memory;
a loop instruction buffer LIB for caching the instructions of the loop body; the upper limit of the number of instructions in the loop instruction buffer LIB is MAX, for example, MAX is 512, which means that the loop buffer can store at most 512 instructions, and also means a loop body with the maximum number of supported instructions being 512 in this embodiment;
the loop state register group is used for recording the instruction execution state of the loop body, comprises a residual iteration number register loop _ counter and is used for storing the residual iteration number of the current execution loop; an instruction number register inst _ counter in the loop body, which is used for storing the instruction number in the loop body of the loop body; a loaded instruction number register load _ counter for storing the number of instructions loaded into the circular instruction buffer; the current execution instruction address register inst _ pointer is used for storing an instruction address of a current execution cycle instruction, wherein the instruction address of the current execution cycle instruction comprises two parts, one part is an instruction address at the first part of a cycle body, and the other part is the offset of the current execution instruction address relative to the instruction address at the first part of the cycle body;
the instruction selector is used for selecting to fetch instructions from the instruction Cache I-Cache or the circular instruction buffer LIB according to the instruction execution state of the circular body recorded in the circular state register group;
the pre-decoder is used for decoding the taken instruction to judge whether the taken instruction is an extended cycle instruction or not, and if the extended cycle instruction is encountered and the instruction of the cycle body corresponding to the extended cycle instruction is not completely loaded, a selection signal for controlling the program counter selection module is sent out to continue loading the instruction of the cycle body corresponding to the extended cycle instruction; if a non-expansion cycle instruction is encountered, an indication signal of the non-expansion cycle instruction is sent out;
the program counter selection module is used for grabbing instructions from the instruction Cache I-Cache according to a selection signal, putting the instructions into the circulating instruction buffer LIB and entering a production line;
a control module to perform a specified branch prediction defense upon receipt of an indication of a non-expanded loop instruction: pausing the pipeline or inserting an entry instruction, and waiting for determining a branch result and a conditional branch instruction target address; after the branch result and the conditional branch instruction target address are determined, the conditional branch instruction target address is used as a new program counter value, and the pipeline is restored. The fence instruction (synchronization barrier instruction), also called memory barrier instruction or memory fence instruction, is a synchronization point when the CPU performs access operation, and after all read/write/read/write operations before the synchronization point are completed, the operations after the synchronization point can be started to be executed. The nonce instruction has corresponding implementations on various conventional platforms, e.g., sfence, lfence, and mfence in x86, DMB, DSB, ISB in arm, and feng and feng.i in risc-v.
Wherein the predecoder identifies whether the instruction is an extended loop instruction, comprising: identifying the instruction captured from the instruction cache or the memory, and identifying whether the instruction is an extended cycle instruction; if the instruction is an extended loop instruction, the instruction is decoded, a loop number field and an instruction number field in the instruction are obtained, and a loop execution register set is updated. In this embodiment, an extended loop instruction is named as a loop instruction, if the extended loop instruction is the extended loop instruction, a corresponding loop iteration number k and an instruction number n in a loop are decoded, and then a signal is sent to a loop state register group to initialize a relevant register, where a loop _ counter is set to be k and an inst _ counter is set to be n; if the instruction is other branch instructions, sending a pipeline pause signal, pausing instruction fetching, preventing the instruction from being executed in a thrust test mode, modifying the PC value into a corresponding jump address when the related result is obtained from other pipeline stages by the extended loop instruction, and recovering the value; if the instruction is another instruction, a PC (program counter) select signal is sent, and the PC points to the next instruction. During the execution cycle, the predecoder points the PC to the instruction indicated by inst _ pointer every clock cycle.
The loop instruction buffer LIB is used for caching an instruction sequence in a loop body, and includes: after the predecoder identifies an extended cycle instruction, the cycle buffer begins loading instructions into the buffer; when the instructions are loaded to the circular buffer, the instructions enter the pipeline to be continuously executed; when the number of the instructions loaded into the loop buffer is the same as the number indicated by the extended loop instructions, stopping continuing loading, and ending the first round of loop; each subsequent cycle grabs instructions from the circular buffer until the cycle reaches a corresponding number.
The loop state register set is used for storing loading and execution related information of the loop, and comprises the following steps: a loop counter for storing the number of remaining iterations of the loop, initializing after capturing the loop, and decrementing the counter by one in each iteration; the counter is used for storing the number of instructions in the loop body of the current loop, and can be used for judging whether all instructions are loaded or not in the first iteration, or judging whether the loop body is executed or not in each subsequent iteration; the instruction loading counter is used for indicating the number of the currently loaded instructions, is used for indicating the number of the loaded instructions in the first iteration, and is matched with the instruction number counter to judge whether the loading is finished; the pointer register for indicating the instruction currently running in the loop buffer moves to the next instruction every clock cycle, and if the last instruction in the loop body is executed, the secondary register is redirected to the first instruction. The loop _ counter is used for storing the residual iteration number of the current execution loop, the register is initialized when an extended loop instruction is captured, the register is automatically reduced by 1 when each iteration is completed, and the loop iteration is ended when the value is 0; the instruction number register in loop is used for storing the instruction number in the loop of the current execution loop, and the maximum value represented by the register is MAX because the register is related to the extended loop instruction buffer, and the meaning of the maximum value is the same as the parameter MAX in the extended loop instruction buffer; the loaded instruction number register load _ counter is used for storing the number of instructions which are currently loaded into the extended loop instruction buffer, when extended loop instructions are grabbed, the register is set to be 0, in a first iteration, when one instruction is grabbed and stored into the extended loop instruction buffer, the register value is increased by 1, obviously, when the register value is equal to the value in the instruction number register inst _ counter in the loop body, the first iteration is finished, all instructions in the currently executed loop body are loaded into the extended loop instruction buffer, and in a subsequent iteration, the register value is unchanged, so that the register is also used for identifying whether the first iteration is performed or not; the currently executed instruction address register inst _ pointer is used for storing an instruction address of an instruction of a currently executed loop, and comprises two parts, namely an address of a first instruction of a loop body, and an offset of the currently executed instruction address relative to the address of the first instruction of the loop body, wherein the register can indicate which instruction is currently executed, the offset is moved to a next instruction in each clock cycle, and when the register points to a last instruction in an extended loop instruction buffer, the next clock cycle points to the first instruction.
As shown in fig. 4, the steps of the side-channel-oriented loop statement execution apparatus executing the target program using the extended loop instruction in this embodiment include the foregoing steps 2.1) to 2.9), which are not described herein again.
In addition, the embodiment also provides a side channel security protection-oriented loop statement execution device, which includes a microprocessor and a memory connected to each other, where the microprocessor is programmed or configured to execute the steps of the side channel security protection-oriented loop statement execution method.
In addition, the present embodiment also provides a computer-readable storage medium, in which a computer program programmed or configured to execute the foregoing loop statement execution method for side channel oriented security protection is stored.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may occur to those skilled in the art without departing from the principle of the invention, and are considered to be within the scope of the invention.
Claims (8)
1. A side channel security protection-oriented loop statement execution method is characterized by comprising the following steps:
1) pre-identifying a source code of a target program or a loop body in a target code, and inserting an extended loop instruction based on an extensible instruction set architecture coding specification in front of each loop body to obtain the target program using the extended loop instruction;
2) when a target program using an extended loop instruction is executed, if the extended loop instruction is encountered, deterministically executing a loop body after the extended loop instruction based on the extended loop instruction;
the step 2) of deterministically executing the loop body after the extended loop instruction based on the extended loop instruction further includes a step of recording an execution state of the loop body based on a loop state register set, where the loop state register set includes: the loop _ counter is used for storing the residual iteration times of the current execution loop; an in-loop instruction number register inst _ counter for storing the in-loop instruction number of the loop body; a load instruction number register load _ counter for storing the number of instructions loaded into the circular instruction buffer; the current execution instruction address register inst _ pointer is used for storing an instruction address of a current execution cycle instruction, wherein the instruction address of the current execution cycle instruction comprises two parts, one part is an instruction address at the first part of a cycle body, and the other part is the offset of the current execution instruction address relative to the instruction address at the first part of the cycle body; the step of executing the target program using the extended loop instruction in step 2) includes:
2.1) judging whether a loop _ counter of a residual iteration number register of a loop instruction buffer area is 0, if so, judging that the previous loop has run completely or has not executed the loop, and skipping to execute the next step; skipping to execute step 2.5);
2.2) grabbing the instruction I from the instruction Cache I-Cache;
2.3) judging whether the captured instruction I is an extended loop instruction, if so, firstly decoding and identifying the loop iteration times k and the instruction number n in a loop body of the extended loop instruction, and then executing initialization of a loop state register set: initializing a residual iteration count register loop _ counter to be a loop iteration count k of an extended loop instruction, wherein a loop internal instruction number register inst _ counter is an instruction number n in the loop of the extended loop instruction, a loaded instruction number register load _ counter is 0, and a currently executed instruction address register inst _ pointer is 0;
2.4) updating the value of the program counter PC to be the address of the next instruction, and skipping to execute the step 2.1);
2.5) judging whether a loaded instruction number register load _ counter of the loop instruction buffer area is smaller than an instruction number register inst _ counter in the loop body, if so, judging that the loop body is currently in the execution process of the first iteration of the loop body and the instruction of the loop body is not loaded completely, and continuously grabbing an instruction I from the instruction Cache I-Cache; if not, judging that the current loop is in the execution process of the second round iteration or the subsequent round iteration of the loop body, and skipping to execute the step 2.7);
2.6) the fetched instruction I enters a pipeline, the fetched instruction I is written into the first load _ counter buffer slot of the loop instruction buffer LIB, the value of the loaded instruction number register load _ counter is added with 1, and the step 2.4) is executed by jumping;
2.7) fetching an instruction I [ inst _ pointer ] from a loop instruction buffer LIB, wherein the inst _ pointer is the offset of an address register inst _ pointer of the current execution instruction;
2.8) the fetched instruction I [ inst _ pointer ] enters the pipeline, and updates the value of the currently executed instruction address register inst _ pointer to: (inst _ pointer +1)% inst _ counter, wherein inst _ pointer is the offset of the currently executed instruction address register inst _ pointer, and inst _ counter is the value of the instruction number register inst _ counter in the loop;
2.9) judging whether the value of an instruction number register inst _ counter in the loop is 0, if so, subtracting 1 from the value of a residual iteration number register loop _ counter; the jump performs step 2.1).
2. The side-channel-security-protection-oriented loop statement execution method according to claim 1, wherein the encoded information of the extended loop instruction in step 1) includes a loop iteration number of a loop body after the extended loop instruction and a number of instructions in the loop body.
3. The side-channel-security-guard-oriented loop statement execution method according to claim 1, wherein the maximum number of supported loop internal instruction pieces of the extended loop instruction is 2a1, where a is the bit width of the number of instructions in the loop body in the extended loop instruction.
4. The side-channel-security-guard-oriented loop statement execution method according to claim 2, wherein the pre-identifying of the loop body in the source code or the target code of the target program in step 1) is: identifying the loop iteration times and the number of instructions in loop bodies of each loop body by a compiler according to the source code of the target program, generating an extended loop instruction based on the structural coding specification of an extensible instruction set system according to the loop iteration times and the number of instructions in the loop bodies, and inserting the extended loop instruction into the corresponding loop bodies to finally obtain the target program using the extended loop instruction; or, the optimizer identifies the loop iteration times and the number of instructions in loop bodies of each loop body aiming at the target code of the target program, generates an extended loop instruction based on the extensible instruction set architecture coding specification according to the loop iteration times and the number of instructions in the loop bodies, and inserts the extended loop instruction into the corresponding loop bodies, so as to finally obtain the target program using the extended loop instruction.
5. The side-channel-security-protection-oriented loop statement execution method according to claim 2, wherein when deterministically executing the loop body after the extended loop instruction based on the extended loop instruction in step 2), further comprising the step of caching the extended loop instruction based on a specified loop instruction buffer LIB.
6. A side-channel security protection-oriented loop statement execution apparatus, comprising:
the instruction Cache I-Cache is used for caching common instructions;
the loop instruction buffer LIB is used for caching the instructions of the loop body;
the loop state register group is used for recording the instruction execution state of the loop body, and comprises a residual iteration number register loop _ counter which is used for storing the residual iteration number of the current execution loop; an instruction number register inst _ counter in the loop body, which is used for storing the instruction number in the loop body of the loop body; a loaded instruction number register load _ counter for storing the number of instructions loaded into the circular instruction buffer; the current execution instruction address register inst _ pointer is used for storing an instruction address of a current execution cycle instruction, wherein the instruction address of the current execution cycle instruction comprises two parts, one part is an instruction address at the first part of a cycle body, and the other part is the offset of the current execution instruction address relative to the instruction address at the first part of the cycle body;
the instruction selector is used for selecting to fetch instructions from the instruction Cache I-Cache or the circular instruction buffer LIB according to the instruction execution state of the circular body recorded in the circular state register group;
the pre-decoder is used for decoding the taken instruction to judge whether the taken instruction is an extended cycle instruction or not, and if the extended cycle instruction is encountered and the instruction of the cycle body corresponding to the extended cycle instruction is not completely loaded, a selection signal for controlling the program counter selection module is sent out to continue loading the instruction of the cycle body corresponding to the extended cycle instruction; if a non-expansion cycle instruction is encountered, an indication signal of the non-expansion cycle instruction is sent out;
the program counter selection module is used for grabbing instructions from the instruction Cache I-Cache according to a selection signal, putting the instructions into the circulating instruction buffer LIB and entering a production line;
a control module to perform a specified branch prediction defense upon receipt of an indication of a non-expanded loop instruction: pausing the pipeline or inserting an entry instruction, and waiting for determining a branch result and a conditional branch instruction target address; after determining the branch result and the conditional branch instruction target address, taking the conditional branch instruction target address as a new program counter value, and recovering the pipeline;
the step of the side channel safety protection-oriented loop statement execution device executing the target program using the extended loop instruction comprises the following steps:
2.1) judging whether a loop _ counter of a residual iteration number register of a loop instruction buffer area is 0, if so, judging that the previous loop has run completely or has not executed the loop, and skipping to execute the next step; skipping to execute step 2.5);
2.2) grabbing the instruction I from the instruction Cache I-Cache;
2.3) judging whether the captured instruction I is an extended loop instruction, if so, firstly decoding and identifying the loop iteration times k of the extended loop instruction and the number n of instruction in a loop body, and then executing initialization of a loop state register set: initializing a residual iteration count register loop _ counter to be a loop iteration count k of an extended loop instruction, wherein a loop internal instruction number register inst _ counter is an instruction number n in the loop of the extended loop instruction, a loaded instruction number register load _ counter is 0, and a currently executed instruction address register inst _ pointer is 0;
2.4) updating the value of the program counter PC to be the address of the next instruction, and skipping to execute the step 2.1);
2.5) judging whether a loaded instruction number register load _ counter of the loop instruction buffer area is smaller than an instruction number register inst _ counter in a loop body, if so, judging that the loop body is currently in the execution process of the first iteration of the loop body and the instruction of the loop body is not loaded completely, and continuously grabbing an instruction I from the instruction Cache I-Cache; if not, judging that the current loop is in the execution process of the second round iteration or the subsequent round iteration of the loop body, and skipping to execute the step 2.7);
2.6) the fetched instruction I enters a pipeline, the fetched instruction I is written into the first load _ counter buffer slot of the loop instruction buffer LIB, the value of the loaded instruction number register load _ counter is added with 1, and the step 2.4) is executed by jumping;
2.7) fetching an instruction I [ inst _ pointer ] from a loop instruction buffer LIB, wherein the inst _ pointer is the offset of an address register inst _ pointer of the current execution instruction;
2.8) the fetched instruction I [ inst _ pointer ] enters the pipeline, and updates the value of the currently executed instruction address register inst _ pointer to: (inst _ pointer +1)% inst _ counter, wherein inst _ pointer is the offset of the currently executed instruction address register inst _ pointer, and inst _ counter is the value of the instruction number register inst _ counter in the loop;
2.9) judging whether the value of an instruction number register inst _ counter in the loop is 0, if so, subtracting 1 from the value of a residual iteration number register loop _ counter; jump execution step 2.1).
7. A side-channel security protection oriented loop statement execution device, comprising a microprocessor and a memory which are connected with each other, wherein the microprocessor is programmed or configured to execute the steps of the side-channel security protection oriented loop statement execution method according to any one of claims 1 to 5.
8. A computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, the computer program being programmed or configured to perform the side-channel security guard oriented loop statement execution method according to any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110443636.3A CN113076090B (en) | 2021-04-23 | 2021-04-23 | Side channel safety protection-oriented loop statement execution method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110443636.3A CN113076090B (en) | 2021-04-23 | 2021-04-23 | Side channel safety protection-oriented loop statement execution method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113076090A CN113076090A (en) | 2021-07-06 |
| CN113076090B true CN113076090B (en) | 2022-07-05 |
Family
ID=76618466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110443636.3A Active CN113076090B (en) | 2021-04-23 | 2021-04-23 | Side channel safety protection-oriented loop statement execution method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113076090B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115694981A (en) * | 2022-10-27 | 2023-02-03 | 中国人民解放军国防科技大学 | Method and device for preventing side channel information leakage |
| CN116719561B (en) * | 2023-08-09 | 2023-10-31 | 芯砺智能科技(上海)有限公司 | Conditional branch instruction processing system and method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103873229A (en) * | 2014-03-13 | 2014-06-18 | 华南师范大学 | Rapid protection method for resisting timing and cache side channel attack under KLEIN encryption AVR environment |
| CN104168266A (en) * | 2014-07-21 | 2014-11-26 | 苏州大学 | Encryption method for preventing continuous leakage attacks |
| CN107769910A (en) * | 2017-11-15 | 2018-03-06 | 东南大学 | A kind of anti-side channel analysis DES means of defences and circuit based on Latch PUF |
| CN109426614A (en) * | 2017-09-01 | 2019-03-05 | 深圳市源伞新科技有限公司 | Defect inspection method, equipment, system and computer readable storage medium |
| CN110659071A (en) * | 2018-06-29 | 2020-01-07 | 英特尔公司 | Effective mitigation of side-channel based attacks against speculative execution processing architectures |
| EP3754893A1 (en) * | 2019-06-17 | 2020-12-23 | STMicroelectronics (Rousset) SAS | Protection symmetric encryption algorithms executions against side-channel attacks |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3010210B1 (en) * | 2013-08-29 | 2017-01-13 | Stmicroelectronics Rousset | PROTECTION OF CALCULATION AGAINST HIDDEN CHANNEL ATTACKS |
| EP3534253A1 (en) * | 2018-02-28 | 2019-09-04 | Koninklijke Philips N.V. | Compiling device and method |
-
2021
- 2021-04-23 CN CN202110443636.3A patent/CN113076090B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103873229A (en) * | 2014-03-13 | 2014-06-18 | 华南师范大学 | Rapid protection method for resisting timing and cache side channel attack under KLEIN encryption AVR environment |
| CN104168266A (en) * | 2014-07-21 | 2014-11-26 | 苏州大学 | Encryption method for preventing continuous leakage attacks |
| CN109426614A (en) * | 2017-09-01 | 2019-03-05 | 深圳市源伞新科技有限公司 | Defect inspection method, equipment, system and computer readable storage medium |
| CN107769910A (en) * | 2017-11-15 | 2018-03-06 | 东南大学 | A kind of anti-side channel analysis DES means of defences and circuit based on Latch PUF |
| CN110659071A (en) * | 2018-06-29 | 2020-01-07 | 英特尔公司 | Effective mitigation of side-channel based attacks against speculative execution processing architectures |
| EP3754893A1 (en) * | 2019-06-17 | 2020-12-23 | STMicroelectronics (Rousset) SAS | Protection symmetric encryption algorithms executions against side-channel attacks |
Non-Patent Citations (3)
| Title |
|---|
| 《基于可信设计流程的方法研究》;成祥;《中国优秀硕士学位论文信息科技辑》;20180116(第2期);全文 * |
| 乱序超标量处理器核的性能分析与优化;孙彩霞;《国防科技大学学报》;20161031(第5期);全文 * |
| 边信道攻击及防御的研究与实现;孙春辉;《中国优秀博士学位论文信息科技辑》;20130415(第4期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113076090A (en) | 2021-07-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11544070B2 (en) | Efficient mitigation of side-channel based attacks against speculative execution processing architectures | |
| CN109508536B (en) | Detection method and device for tampering program flow attack | |
| JP2875909B2 (en) | Parallel processing unit | |
| CN113076090B (en) | Side channel safety protection-oriented loop statement execution method and device | |
| US6408385B1 (en) | Data processor | |
| US5687360A (en) | Branch predictor using multiple prediction heuristics and a heuristic identifier in the branch instruction | |
| US6263427B1 (en) | Branch prediction mechanism | |
| JP4727491B2 (en) | Branch prediction control | |
| CN113076136A (en) | Safety protection-oriented branch instruction execution method and electronic device | |
| US6304962B1 (en) | Method and apparatus for prefetching superblocks in a computer processing system | |
| US20200380150A1 (en) | Method of encoding and decoding memory data for software security, recording medium and apparatus for performing the method | |
| US20160171213A1 (en) | Apparatus and method for controlling instruction execution to prevent illegal accesses to a computer | |
| US20070245419A1 (en) | Intrusion detection during program execution in a computer | |
| Aimoniotis et al. | Reorder buffer contention: A forward speculative interference attack for speculation invariant instructions | |
| US11307856B2 (en) | Branch target variant of branch-with-link instruction | |
| KR100276138B1 (en) | Branch history table with branch pattern field | |
| US9639370B1 (en) | Software instructed dynamic branch history pattern adjustment | |
| US20090125728A1 (en) | Security method of system by encoding instructions | |
| CN112596792B (en) | Branch prediction method, apparatus, medium, and device | |
| CN112035170B (en) | Method and system for branch predictor | |
| US7130991B1 (en) | Method and apparatus for loop detection utilizing multiple loop counters and a branch promotion scheme | |
| US7428632B2 (en) | Branch prediction mechanism using a branch cache memory and an extended pattern cache | |
| KR920006770B1 (en) | System for controlling instruction fetch controlling | |
| US20210011728A1 (en) | Target injection safe method for dynamically inlining branch predictions | |
| CN115658151A (en) | Safety protection-oriented branch result rapid determination method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |