CN113066756A

CN113066756A - Method for manufacturing semiconductor element

Info

Publication number: CN113066756A
Application number: CN202110022475.0A
Authority: CN
Inventors: 卢柏全; 陈亭纲; 林颂恩; 王俊尧; 卢永诚; 徐志安; 黄泰钧; 王捷平
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2020-04-28
Filing date: 2021-01-08
Publication date: 2021-07-02
Also published as: TW202140839A; TWI766438B

Abstract

A method of fabricating a semiconductor device, i.e., a method of forming a dielectric material in a trench, is described. In an embodiment of a method, the method includes introducing a first precursor into a trench of a dielectric layer such that a portion of the first precursor reacts with the dielectric layer and adheres to sidewalls of the trench. The method also includes partially etching a portion of the first precursor on the sidewalls of the trench to expose an upper portion of the sidewalls of the trench. The method also includes introducing a second precursor into the trench such that a portion of the second precursor reacts with a remaining portion of the first precursor to form a dielectric material at a bottom of the trench.

Description

Method for manufacturing semiconductor element

Technical Field

Some embodiments of the present disclosure relate to methods of fabricating semiconductor devices, and more particularly, to methods of depositing materials.

Background

Semiconductor devices are used in a variety of electronic applications such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are generally produced by: layers of insulating or dielectric, conductive, and semiconductor materials are sequentially deposited over a semiconductor substrate, and various material layers are patterned using a photolithographic process to form circuit elements and devices thereon.

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area.

Disclosure of Invention

In some embodiments of the present disclosure, a method of manufacturing a semiconductor device includes: a first precursor is introduced into the trench such that a portion of the first precursor reacts with sidewalls of the trench to form a first precursor product. The first precursor product is etched to expose an upper portion of the sidewalls of the trench. A second precursor is introduced into the trench such that a portion of the second precursor reacts with the first precursor product.

In some embodiments of the present disclosure, a method of manufacturing a semiconductor device includes: a first precursor layer is formed along the exposed surface in the gap in a self-limiting reaction between the first precursor and the exposed surface. The surface of the portion in the upper portion of the gap is re-exposed by partially etching the first precursor layer. A second precursor layer is formed along the remaining portion of the first precursor layer.

In some embodiments of the present disclosure, a method of manufacturing a semiconductor device includes: a trench is formed in the first material. A first monolayer of a first precursor material is formed along sidewalls and a bottom of the trench. The first monolayer is partially removed along an upper portion of the sidewalls of the trench. A second monolayer of a second precursor material is formed over the remaining portion of the first monolayer within the trench.

Drawings

Aspects of the present disclosure are best understood from the following description when read with the accompanying drawing figures. It is noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates an example of a fin field effect transistor (FinFET) illustrated in a three-dimensional view, in accordance with some embodiments;

fig. 2-4A illustrate cross-sectional views of intermediate stages in the fabrication of a finfet, according to some embodiments;

FIGS. 4B and 4C illustrate a system and control unit for performing a gap-fill process, according to some embodiments;

FIGS. 5A-5F illustrate intermediate steps in a gap-fill process with an enlarged view of the section highlighted in FIG. 4A, in accordance with some embodiments;

fig. 6-15B illustrate cross-sectional views at further intermediate stages in the fabrication of a FinFET, in accordance with some embodiments;

fig. 16A-16F illustrate intermediate steps in a gap-fill process, in accordance with some other embodiments, with an enlarged view of the section highlighted in fig. 4A.

[ notation ] to show

A-A is cross section

B-B cross section

C-C cross section

H1 first height

H2 second height

101 base material

103 fin structure

105 isolation region

107 gate dielectric layer

109 gate electrode

111 source/drain region

201N: N type region

201P-type region

203 separating element

301 groove

400 first gap-fill atomic layer deposition process

401 first gap filling Material

403: section

405 deposition and etch System

407 first precursor delivery System

409 etch precursor delivery system

411 second precursor delivery System

413 deposition and etch chamber

415 gas supply source

417 flow controller

419 precursor gas controller

421 control unit

423 manifold

425 spray head

427 casing

429 mounting platform

431 exhaust outlet

433 vacuum pump

435 flushing gas delivery system

437 processing unit

439 display

441 input/output assembly

443 central processing unit

445 memory

447 mass storage device

449 video adapter

451I/O interface

453 bus line

455 network interface

457 regional/wide area network

501 first monolayer

503 second monolayer

505 film

601 dummy dielectric layer

603 dummy gate layer

605 mask layer

701 mask

703 dummy gate

705 channel region

707 Gate seal spacer

801 gate spacer

1001 first interlayer dielectric

1003 contact etch stop layer

1201 groove

1301: region

1401 gate mask

1403 second interlayer dielectric

1501 gate contact

1503 source/drain contact

1600, second gap filling atomic layer deposition process

1601 third monolayer

1603 second gap filling material

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, in various instances, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as "below," "lower," "above," "higher," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Embodiments disclosed herein are directed to semiconductor devices and methods of forming semiconductor devices. In particular, gap-fill deposition techniques and selective film deposition techniques used in the formation of semiconductor devices are disclosed herein. According to some embodiments, gap-fill deposition techniques use gap-fill materials in an atomic layer deposition process to fill and/or overfill gaps formed in a workpiece. The gap filling material may be a conductive material, a semiconductor material, a dielectric material. In some embodiments, the gap fill material is a dielectric material deposited in gaps of a conductive material, a dielectric material, and/or a semiconductor material (e.g., a semiconductor substrate). In other embodiments, the gap fill material is a conductive material and/or a semiconductor material deposited in the gaps of a dielectric material (e.g., a hard mask layer, an interlayer dielectric layer, a polymer layer, or the like).

In other embodiments, the selective film deposition technique uses a selective film material in an atomic layer deposition process or a Chemical Vapor Deposition (CVD) process to deposit a selective film on a target surface and/or a non-target surface. The selective membrane may be a dielectric material or may be a conductive material. In some embodiments, selective film deposition is performed on target surface and/or non-target surface silicon/metal over dielectric. In other embodiments, selective film deposition is performed on a target surface and/or a non-target surface of a dielectric such as metal/silicon on top. However, other target surfaces and/or non-target surfaces may be used. These selective film techniques may be used to form other structures such as selective liners, selective hard masks, and may be applied to intermediate stages of forming semiconductor devices (e.g., front-end of the line (FEOL), middle of the line (MOL), and/or back-end of the line (BEOL)). Furthermore, these selective membrane techniques can be used for different technology generations, including 5 nm, 3 nm and beyond.

Referring now to fig. 1, fig. 1 illustrates an example of a finfet illustrated in a three-dimensional view, in accordance with some embodiments. A finfet includes a fin structure 103 on a substrate 101 (e.g., a semiconductor substrate). Isolation regions 105 (e.g., Shallow Trench Isolation (STI) regions) are disposed in the substrate 101, and the fin structures 103 protrude from between adjacent isolation regions 105 and over between adjacent isolation regions 105. Although the isolation regions 105 are described/illustrated as being separate from the substrate 101, as used herein, the term "substrate" may be used to refer to only a semiconductor substrate or a semiconductor substrate that includes isolation regions. Additionally, although fin structure 103 is illustrated as a single, continuous material with substrate 101, fin structure 103 and/or substrate 101 may comprise a single material or multiple materials. In this context, fin structure 103 refers to a portion extending between adjacent isolation regions 105.

A gate dielectric layer 107 is along the sidewalls and over the top surface of the fin 103, and a gate electrode 109 is over the gate dielectric layer 107. Source/drain regions 111 are disposed on opposite sides of fin structure 103 relative to gate dielectric layer 107 and gate electrode 109. Fig. 1 further illustrates a reference cross-sectional view used in the following figures. The cross-section a-a is along the longitudinal axis of the gate electrode 109 and in a direction, for example, perpendicular to the direction of current flow between the source/drain regions 111 of the finfet. Cross-section B-B is perpendicular to cross-section a-a and along the longitudinal axis of fin structure 103 and, for example, the direction of current flow between source/drain regions 111 of the finfet. Section C-C is parallel to section a-a and extends through the source/drain region 111 of the finfet. For clarity, the subsequent figures refer to these reference cross-sectional views.

Some embodiments herein are discussed in the context of finfet transistors formed using gate last processes. In other embodiments, a gate prime process may be used. Also, some embodiments contemplate aspects used in planar elements, such as planar field effect transistors, nanostructures (e.g., nanosheets, nanowires, Gate All Around (GAA) or the like), field effect transistors (NSFETs), or the like.

Further, embodiments herein are discussed in the context of using a gap-fill deposition technique in the formation of shallow trench isolation regions using finfet transistors. However, gap-fill deposition techniques may be applied to fill gaps for forming other features of the device, and all such embodiments do not depart from the spirit and scope of the present disclosure.

Fig. 2-4A and 6-16B are cross-sectional views of an intermediate stage in the fabrication of a finfet, according to some embodiments. Fig. 2-4A and 6 illustrate the reference cross section a-a illustrated in fig. 1, in addition to a plurality of fin structures/finfets. Fig. 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, and 15A are illustrated along a reference cross-section a-a in fig. 1, and fig. 7B, 8B, 9B, 10B, 11B, 12B, 13C, 14B, and 15B are illustrated along a similar cross-section B-B in fig. 1, except for a plurality of fin structures/finfets. Fig. 9C and 9D are illustrated along reference cross section C-C of fig. 1, except for a plurality of fin structures/finfets. Fig. 4B and 4C illustrate a system and a control unit, respectively, for performing a gap-filling process according to some embodiments. Fig. 5A-5F each illustrate intermediate steps of an embodiment of a gap-fill process with an enlarged view of the section highlighted in fig. 4A. Fig. 16A-16F each illustrate intermediate steps of another embodiment of a gap-fill process with an enlarged view of the section highlighted in fig. 4A.

In fig. 2-4A and 6-16B, a process is described whereby a dielectric material is deposited in a gap between two adjacent semiconductor fin structures 103. However, although the processes described herein are described as being deposited between two adjacent semiconductor fin structures 103, the processes described are not limited to this embodiment and may be utilized in any suitable embodiment. For example, in another embodiment, a gap-fill deposition process may be utilized to fill the gaps in the dielectric layer covering the active devices. The gap fill process may be used at any suitable step in the fabrication process and all such gap fill processes are fully intended to be included within the scope of the embodiments.

In fig. 2, a substrate 101 is provided. The substrate 101 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI), or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 101 may be a wafer, such as a silicon wafer. Generally, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. An insulating layer is provided onto a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 101 may include silicon, germanium, compound semiconductors including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb), alloy semiconductors including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (InAlAs), aluminum gallium arsenide (GaAlAs), indium gallium arsenide (InGaAs), gallium indium phosphide (InGaP), and/or gallium indium arsenide phosphide (inasgp), or combinations thereof.

The substrate 101 has an N-type region 201N and a P-type region 201P. The N-type region 201N may be used to form an N-type device, such as an N-type metal-oxide-semiconductor (NMOS) transistor, e.g., an N-type finfet transistor. P-type region 201P may be used to form P-type devices, such as P-type metal oxide (PMOS) transistors, e.g., P-type finfet transistors. The N-type region 201N may be physically separated from the P-type region 201P (as by the illustrated spacers 203), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the N-type region 201N and the P-type region 201P.

In fig. 3, fin structure 103 is formed in substrate 101. Fin structure 103 is a semiconductor strip. In some embodiments, the fin structure 103 may be formed in the substrate 101 by etching a trench 301 in the substrate 101. The etching process may be any acceptable etching process, such as Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), the like, or combinations thereof. The etching may be an anisotropic process. In addition, the trench 301 may be formed to have an aspect ratio of between about 5: 1 and about 20: 1. However, any suitable aspect ratio may be used.

The fin structure may be patterned by any suitable method. For example, fin structure 103 may be patterned using one or more photolithography processes, including a double patterning process or a multiple patterning process. Generally, double patterning or multiple patterning processes combine photolithography and self-alignment processes to allow the patterning to be created with, for example, a smaller pitch than would otherwise be possible using a single, direct photolithography process. For example, in one embodiment, a photolithography process is used to form a sacrificial layer over the substrate and to pattern the sacrificial layer. A self-aligned process is used to form spacers alongside the patterned sacrificial layer. The sacrificial layer is then removed and the remaining spacers are then used to pattern fin structure 103. In some embodiments, a mask (or other layer) may remain on fin structure 103.

A first gap-fill Atomic Layer Deposition (ALD) process 400 and deposition and etch system 405 are illustrated in figures 4A-4C, according to some embodiments. In particular, fig. 4A illustrates a first gap-fill atomic layer deposition process 400 being used to form a first gap-fill material 401 in the trench 301 when finally forming the isolation region 105 between adjacent ones of the fin structures 103, in accordance with a specific embodiment. Fig. 4A further illustrates the section 403 referenced in the following figures. Figure 4B illustrates a deposition and etch system 405 for performing the first gap-fill atomic layer deposition process 400, in accordance with some embodiments.

Although the embodiments of the first gap-fill ald process 400 are disclosed herein with respect to filling the trench 301 between the fin structures 103 in the final configuration of the isolation region 105, the first gap-fill ald process 400 may be used as an intermediate step in forming a semiconductor device for forming a dielectric or semiconductor material in any suitable gap, without departing from the spirit and scope of the present disclosure. In particular, the first gap-fill atomic layer deposition process 400 may be used to deposit a thin film having a thickness of about 5: 1 to about 20: a seamless and void-free dielectric material or semiconductor material is formed in the gap with the aspect ratio of 1. However, the first gap-fill ald process 400 may also be used to fill gaps having other aspect ratios.

Turning to fig. 4A, a first gap-fill atomic layer deposition process 400 is used to form a first gap-fill material 401 in the trench 301, in accordance with some embodiments. In these embodiments, the first gap fill material 401 may be a material such as silicon oxide or silicon nitride (e.g., silicon oxide (SiO), silicon nitride (SiN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), low-k spacers, or high-k dielectrics, silicon carbonitride (SiCN)), metal oxides (e.g., aluminum oxide (Al), for example)₂O₃) Titanium oxide (TiO)₂) A dielectric film of metal nitride (e.g., aluminum nitride (AlN), titanium nitride (TiN)), or the like. In the illustrated embodiment, the isolation region 105 is formed as silicon nitride using a first gap-fill atomic layer deposition process 400. Although the illustrated embodiment is shown with the first gap-fill atomic layer deposition process 400 performed in both the N-type region 201N and the P-type region 201P, the first gap-fill material 401 may also be deposited separately by using, for example, an appropriate masking technique to protect regions while performing the first gap-fill atomic layer deposition process 400 in other regionsAnd all such embodiments do not depart from the spirit and scope of the present disclosure.

Figure 4B illustrates a deposition and etch system 405 for performing the first gap-fill atomic layer deposition process 400, in accordance with some embodiments. Deposition and etch system 405 may be utilized to receive precursor material from first precursor delivery system 407, etch precursor delivery system 409, and second precursor delivery system 411 and form a layer of material onto substrate 101 between fin structures 103. In an embodiment, first precursor delivery system 407, etch precursor delivery system 409, and second precursor delivery system 411 may work in conjunction with one another to supply various precursor materials and etch materials to deposition and etch chamber 413 in which substrate 101 (and, as a result, fin structure 103) is placed. However, first precursor delivery system 407, etch precursor delivery system 409, and second precursor delivery system 411 may have similar physical components to one another.

For example, first precursor delivery system 407, etch precursor delivery system 409, and second precursor delivery system 411 may each include a gas supply 415 and a flow controller 417 (labeled in fig. 4B with reference to first precursor delivery system 407, but not labeled with respect to etch precursor delivery system 409 and second precursor delivery system 411 for clarity). In embodiments where the first precursor is stored in a gaseous state, the gas supply 415 may supply the first precursor to the deposition and etch chamber 413. The gas supply 415 may be a container, such as a gas storage cylinder located locally to the deposition and etch chamber 413 or may be located remotely from the deposition and etch chamber 413. In other embodiments, gas supply 415 may be a facility that independently prepares and delivers the first precursor to flow controller 417. Any suitable source for the first precursor may be utilized as the gas supply 415, and all such sources are fully intended to be included within the scope of the embodiments.

Gas supply 415 may supply on-demand precursors to flow controller 417. A flow controller 417 may be utilized to control the flow of precursors to the precursor gas controller 419 and ultimately to the deposition and etch chamber 413 to also help control the pressure within the deposition and etch chamber 413. The flow controller 417 may be, for example, a proportional valve, a modulating valve, a needle valve, a pressure regulator, a mass flow controller, combinations of these, or the like. However, any suitable method may be utilized for controlling and regulating the flow of carrier gas to a precursor tank (not otherwise illustrated), and all such components and methods are fully intended to be included within the scope of the embodiments.

However, as those skilled in the art will recognize, although first precursor delivery system 407, etch precursor delivery system 409, and second precursor delivery system 411 have been described herein as having identical components, this is merely an illustrative example and is not intended to limit embodiments in any way. Any type of suitable precursor delivery system may be utilized, with any type and number of individual components being identical or different from any other precursor delivery system within deposition and etch system 405. All such precursor systems are fully intended to be included within the scope of the embodiments.

Further, in embodiments where the first precursor is stored in a solid or liquid state, the gas supply 415 may store a carrier gas and may introduce the carrier gas into a precursor tank (not otherwise illustrated) that stores the first precursor in a solid or liquid state. The carrier gas is then used to drive and carry the first precursor as it is either vaporized or sublimated into the gaseous section of the precursor canister prior to delivery to precursor gas controller 419. Any suitable method and combination of units may be utilized to provide the first precursor, and all combinations of these units are fully intended to be included within the scope of the embodiments.

First precursor delivery system 407, etch precursor delivery system 409, and second precursor delivery system 411 may supply their respective precursor materials into precursor gas controller 419. Precursor gas controller 419 connects and isolates first precursor delivery system 407, etch precursor delivery system 409, and second precursor delivery system 411 from deposition and etch chamber 413 to deliver the desired precursor materials to deposition and etch chamber 413. Precursor gas controllers 419 may include devices such as valves, flow meters, sensors, and the like to control the delivery rate of each precursor gas, and may be controlled by instructions received from control unit 421 (described further below with reference to fig. 4C).

Upon receiving instructions from control unit 421, precursor gas controller 419 may open and close the valves to connect one of first precursor delivery system 407, etch precursor delivery system 409, and second precursor delivery system 411 to deposition and etch chamber 413 and direct the desired precursor material through manifold 423 into deposition and etch chamber 413 and to showerhead 425. The showerhead 425 may be utilized to disperse selected precursor materials into the deposition and etch chamber 413, and the showerhead 425 may be designed to uniformly disperse precursor materials in order to minimize undesirable process conditions that may result from non-uniform dispersion. In an embodiment, the showerhead 425 may have a circular design with openings evenly distributed around the showerhead 425 to allow dispersion of the desired precursor materials into the deposition and etch chamber 413.

However, as one of ordinary skill in the art will recognize, the introduction of precursor materials to the deposition and etch chamber 413 by a single showerhead 425 or by a single introduction point as previously described is intended to be exemplary only and not intended to be limiting to embodiments. Any number of separate and independent showerheads 425 or other openings for introducing precursor materials into the deposition and etch chamber 413 may be utilized. All such combinations and other introduction points of the showerhead 425 are fully intended to be included within the scope of the embodiments.

Deposition and etch chamber 413 may receive a desired precursor material and expose the precursor material to substrate 101 and fin structure 103, and deposition and etch chamber 413 may be any desired shape suitable for dispersing the precursor material and contacting the precursor material with substrate 101 and fin structure 103. In the embodiment illustrated in fig. 4B, the deposition and etch chamber 413 has a cylindrical sidewall and a bottom. However, the deposition and etching chamber 413 is not limited to a cylindrical shape and may utilize any other suitable shape, such as a hollow square tube, an octagon, or the like. In addition, the deposition and etch chamber 413 may be surrounded by a housing 427 made of a material inert to the various process materials. The housing 427 may be any suitable material capable of withstanding the chemistries and pressures involved in the deposition process, and in embodiments, the housing 427 may be steel, stainless steel, nickel (Ni), aluminum (Al), alloys thereof, combinations thereof, or the like.

Within the deposition and etch chamber 413, the substrate 101 may be placed on a mounting table 429 to position and control the substrate 101 and fin structure 103 during the deposition process. The mounting platform 429 may include a heating mechanism to heat the substrate 101 during the deposition process. Additionally, although a single mounting stage 429 is illustrated in FIG. 4B, any number of mounting stages 429 may additionally be included in the deposition and etch chamber 413.

In addition, the deposition and etch chamber 413 and mounting stage 429 may be part of a cluster tool system (not shown). The cluster tool system may be used in conjunction with an automated handling system to place the substrate 101 in the deposition and etch chamber 413 prior to a deposition process, position, maintain the substrate 101 during a deposition process, and remove the substrate 101 from the deposition and etch chamber 413 after a deposition process.

The deposition and etch chamber 413 may also have an exhaust outlet 431 for the exhaust gases exiting the deposition and etch chamber 413. A vacuum pump 433 may be connected to the exhaust outlet 431 of the deposition and etch chamber 413 to facilitate evacuation of the exhaust gases. The vacuum pump 433 may also be utilized to reduce and control the pressure in the deposition and etch chamber 413 to a desired pressure under the control of the control unit 421.

Fig. 4B further illustrates a purge gas delivery system 435. In an embodiment, the purge gas delivery system 435 may be a gas cylinder or other means that provides a purge gas, such as nitrogen, argon, xenon, or other non-reactive gas, to the deposition and etch chamber 413. In addition, the purge gas delivery system 435 and/or the vacuum pump 433 may also be utilized to evacuate precursor material from the deposition and etch chamber 413 in preparation for the introduction of the next precursor material under the control of the control unit 421.

Fig. 4C illustrates an embodiment of a control unit 421 that may be utilized to control the precursor gas controller 419 and the vacuum pump 433. The control unit 421 may be any form of computer processor that may be used in an industrial environment to control a process machine. The control unit 421 may in embodiments comprise a processing unit 437, such as a desktop computer, a workstation, a laptop computer, or a dedicated unit tailored to the specific application. The control unit 421 may be provided with a display 439 and an input/output (I/O) component 441 such as a command output, a sensor input, a mouse, a keyboard, a printer, a combination of these, or the like. The processing unit 437 may include a Central Processing Unit (CPU) 443, a memory 445, a mass storage device 447, a video adapter 449, and an input/output interface 451 connected to a bus 453.

The bus 453 can be any of one or more of several types of bus structures including a memory bus or memory controller, a peripheral bus, or a video bus. The central processing unit 443 may include any type of electronic data processor, while the memory 445 may include any type of system memory, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), or read-only memory (ROM). The mass storage device 447 may comprise any type of storage device configured to store data, programs, and other information and to make the data, programs, and other information accessible via the bus 453. The mass storage device 447 may include, for example, one or more hard disk drives, magnetic disk drives, or optical disk drives.

A video adapter 449 and an input/output (I/O) interface 451 provide an interface to couple external input and output devices to the processing unit 437. As illustrated in FIG. 3, examples of input and output devices include a display 439 coupled to a video adapter 449 and an input/output component 441 coupled to an input/output interface 451, such as a mouse, keyboard, printer, and the like. Other devices may be coupled to the processing unit 437, and additional or fewer interface cards may be utilized. For example, a serial interface card (not shown) may be used to provide a serial interface for a printer. The processing unit 437 may also include a network interface 455, and the network interface 455 may be a wired connection and/or a wireless connection to a Local Area Network (LAN)/Wide Area Network (WAN) 457.

It should be noted that the control unit 421 may comprise other components. For example, the control unit 421 may include a power supply, a cable, a motherboard, a removable storage medium, a housing, and the like. These other components (although not shown in fig. 4C) are considered part of the control unit 421.

Fig. 5A-5F illustrate, in an enlarged view of section 403 of fig. 4A but not to scale, a series of atomic layer deposition and partial etch steps of a gap-fill atomic layer deposition process 404, according to some embodiments. In particular, fig. 5A to 5F illustrate an embodiment of a gap-fill atomic layer deposition process 404, wherein a first gap-fill material 401 is formed in the trench 301 when the isolation region 105 is finally formed.

Figure 5A illustrates the deposition of a first monolayer 501 formed on fin structure 103 and in trench 301. In an embodiment, the deposition and etch system 405 uses a first precursor material to deposit a first monolayer 501 onto the fin structure 103 and into the trench 301. The first precursor material may be a chemical such as silicon (Si) with or without a halogen group, or may be a metal with or without a halogen group (e.g., Silane (SiH)₄) Disilane (Si)₂H₆) Dichlorosilane (DCS) (SiH)₂Cl₂) N- (diethylaminosilyl) -N-ethylethylamine (SAM24), titanium tetrachloride (TiCl)₄) Trimethylaluminum (Al (CH)₃)₃) Silicon tetrachloride (SiCl)₄) Or the like. In the illustrated embodiment, Dichlorosilane (DCS) (SiH) may be used₂Cl ₂) As a first precursor material to form a first monolayer 501. The first monolayer 501 may be formed in the deposition and etch chamber 413 using a deposition process such as atomic layer deposition (ald). However, such materials and such processes are intended to be exemplary, and not intended to be limiting, since it is advantageousOther desirable materials, such as other dielectric materials and other suitable deposition processes (e.g., Chemical Vapor Deposition (CVD)), may be used.

In an embodiment, formation of first monolayer 501 may begin by placing a first precursor material into first precursor delivery system 407. For example, in embodiments where the first monolayer 501 is formed as a thin film of dichlorosilane, the first precursor material may be a precursor such as dichlorosilane and may be placed in the first precursor delivery system 407. However, as one of ordinary skill in the art will recognize, this precursor is not the only precursor that can form a dichlorosilane layer, and the use of dichlorosilane is not intended to be limited to the examples. Any suitable precursor material in any suitable phase (solid, liquid, or gaseous) may be utilized.

In addition, a first etch precursor may be placed in etch precursor delivery system 409. In embodiments in which the first gap fill material 401 is controlled to a desired height within the trench 301, the first etch precursor may be, for example, hydrogen (H)₂) Halide gas (X)₂) Hydrogen halide gas (HX), or the like, with or without the use of an etching chemistry as a plasma. A first etch precursor may be placed in etch precursor delivery system 409 and may be used to partially etch first monolayer 501 of the first precursor material. For example, in embodiments where silane or silicon tetrachloride is utilized as the first precursor material, a hydrogen plasma may be utilized as the first etch precursor, and in embodiments where the first precursor material is a metal, hydrochloric acid (HCl) gas may be utilized as the first etch precursor. However, the description of a halide etch gas as the first etch precursor is not intended to be limiting to the embodiments, and any other suitable first etch precursor, such as hydrogen, hydrogen halide, combinations of these, or the like, may be utilized as the first etch precursor.

In addition, a second precursor material may be placed in second precursor delivery system 411. In embodiments of a silicon nitride layer to be formed as the first gap fill material 401, the second precursor material may be a precursor material that may contain nitrogen gas so as to react with the first precursor material to form a silicon nitride film. For example, in embodiments where dichlorosilane is used as the first precursor material, ammonia may be used as the second precursor material and placed in second precursor delivery system 411. However, the description of ammonia as the second precursor material is not intended to be limited to embodiments, and any other suitable precursor material, such as oxygen, ozone, nitrogen, combinations of these, or the like, for forming any other suitable material (e.g., oxide), may be utilized as the second precursor material in high temperature deposition without plasma or in deposition with plasma.

Once the first precursor material, first etch precursor, and second precursor material have been placed in first precursor delivery system 407, etch precursor delivery system 409, and second precursor delivery system 411, respectively, instructions may be sent by control unit 421 to precursor gas controller 419 to connect first precursor delivery system 407 to deposition and etch chamber 413 to initiate formation of first gap fill material 401. Once connected, first precursor delivery system 407 may deliver a first precursor material (e.g., dichlorosilane) to showerhead 425 via precursor gas controller 419 and manifold 423. Next, the showerhead 425 may dispense a first precursor material into the deposition and etch chamber 413, wherein the first precursor material may be adsorbed by and react with the exposed surfaces of the substrate 101 and the fin structure 103.

In embodiments where a silicon nitride layer is formed, the first precursor material may be flowed into the deposition and etch chamber 413 at a flow rate of between about 1 standard liter per minute (slm) and about 5 standard liters per minute (slm) for about 50 seconds per cycle. In addition, the deposition and etch chamber 413 may be maintained at a pressure between about 3 torr and about 5 torr and a temperature between about 450 degrees celsius and about 700 degrees celsius. However, as one of ordinary skill in the art will recognize, such process conditions are intended to be exemplary only, as any suitable process conditions may be utilized and still fall within the scope of the embodiments.

When the first precursor material is adsorbed onto the substrate 101 and the fin structure 103, the first precursor material reacts with the open active sites on the exposed surfaces of the substrate 101 and the fin structure 103. However, once all of the open active sites on substrate 101 and fin structure 103 have reacted with the first precursor material, the reaction stops because there are no more open active sites to bond with the first precursor material. This confinement causes the reaction of the first precursor material with the substrate 101 and the fin structure 103 to be self-limiting and form a monolayer of the reacted first precursor material on the surface of the substrate 101 and the fin structure 103, allowing for more precise control of the thickness of the first monolayer 501.

After the self-limiting reaction on substrate 101 and fin structure 103 is complete, deposition and etch chamber 413 may be purged of the first precursor material. For example, the control unit 421 may instruct the precursor gas controller 419 to disconnect the first precursor delivery system 407 (containing the first precursor material to be purged from the deposition and etch chamber 413) and connect the purge gas delivery system 435 to deliver the purge gas to the deposition and etch chamber 413. In an embodiment, the purge gas delivery system 435 may be a gas cylinder or other means that provides a purge gas, such as nitrogen, argon, xenon, or other non-reactive gas, to the deposition and etch chamber 413. In addition, the control unit 421 may also activate the vacuum pump 433 to apply a pressure differential to the deposition and etch chamber 413 to facilitate removal of the first precursor material. The purge gas may purge the first precursor material from the deposition and etch chamber 413 for about 3 seconds along with the vacuum pump 433. However, any suitable time may be used.

Referring to fig. 5B, after the purging of the first precursor material has been completed, instructions may be sent by the control unit 421 to the precursor gas controller 419 to disconnect the purge gas delivery system 435 and connect the etch precursor delivery system 409 (containing the first etch precursor) to the deposition and etch chamber 413 to begin introducing the first etch precursor (e.g., halide gas) into the deposition and etch chamber 413. Once connected, etch precursor delivery system 409 may deliver a first etch precursor to showerhead 425. The showerhead 425 may then dispense a first etch precursor into the deposition and etch chamber 413, where the first etch precursor may be used to partially etch the first monolayer 501. According to some embodiments, the first monolayer 501 may be partially etched to a desired height (e.g., first height H1) at or below the bottom of the trench 301. According to some embodiments, the partial etch is a dry etch or a plasma etch and is timed to stop at a desired height within the trench 301. However, any suitable etch process and/or process conditions may be used.

By using a timed etch, the unconsumed portion of the first monolayer 501 remains at the bottom of the trench 301. In a particular embodiment where the first gap fill material 401 is ultimately formed into the isolation region 105, the first height H1 may be between approximately 20 nanometers and approximately 50 nanometers. However, any suitable height may be used. Thereby, the surface of the fin structure 103 is exposed above the first height H1 by the partial etching of the first single layer 501.

In the previously discussed embodiments using dichlorosilane as the first precursor material to partially etch the first monolayer 501, a high temperature halide gas may be introduced into the deposition and etch chamber 413 at a flow rate of between about 0.1 standard liters per minute to about 1.0 standard liters per minute for about 3 seconds to about 20 seconds. In addition, the deposition and etch chamber 413 may be maintained at a pressure between about 0 torr and about 150 torr and a temperature between about 75 degrees celsius and about 550 degrees celsius. However, as will be appreciated by those of ordinary skill in the art, these process conditions are intended to be exemplary only, as any suitable process conditions may be utilized to introduce other suitable etch chemistries using other suitable process conditions and still fall within the scope of the embodiments.

After the partial etch of the first monolayer 501 is complete, the deposition and etch chamber 413 may be flushed of a first etch precursor. For example, the control unit 421 may instruct the precursor gas controller 419 to disconnect the etch precursor delivery system 409 (containing the first etch precursor to be purged from the deposition and etch chamber 413) and connect the purge gas delivery system 435 to deliver the purge gas to the deposition and etch chamber 413. In addition, the control unit 421 may also activate the vacuum pump 433 to apply a pressure differential to the deposition and etch chamber 413 to facilitate removal of the first etch precursor. The purge gas may purge the first etch precursor from the deposition and etch chamber 413 for about 3 seconds along with the vacuum pump 433. However, any suitable time may be used.

Referring to fig. 5C, after the first etch precursor has been purged, introduction of a second precursor material (e.g., ammonia) to the deposition and etch chamber 413 may begin by the control unit 421 sending instructions to the precursor gas controller 419 to disconnect the purge gas delivery system 435 and connect the second precursor delivery system 411 (containing the second precursor material) to the deposition and etch chamber 413. Once connected, second precursor delivery system 411 may deliver a second precursor material precursor to showerhead 425. The showerhead 425 may then dispense a second precursor material into the deposition and etch chamber 413. Thereby, a second monolayer 503 of a second precursor material (e.g., ammonia) may be adsorbed on the remaining surface of the first monolayer 501 (e.g., dichlorosilane) and reacted with the first monolayer 501 in another self-limiting reaction to form a thin film 505 of a first gap fill material 401 (e.g., silicon nitride) on the surface of the substrate 101 and fin structures 103.

In the previously discussed embodiments in which dichlorosilane is used to form the silicon nitride layer, ammonia may be introduced into the deposition and etch chamber 413 at a flow rate of between about 2 standard liters per minute and about 10 standard liters per minute for about 30 seconds. In addition, the deposition and etch chamber 413 may be maintained at a pressure between about 0 torr and about 150 torr and at a temperature between about 450 degrees celsius and about 700 degrees celsius. However, as one of ordinary skill in the art will appreciate, it is within the scope of the embodiments that any suitable process conditions may be utilized to introduce any suitable precursor material and are intended to be exemplary only.

After the thin film 505 of first gap fill material 401 (e.g., silicon nitride) has been formed, the third precursor may be continuously purged from the deposition and etch chamber 413 for about three seconds using, for example, a purge gas from the purge gas delivery system 435. Once the deposition and etch chamber 413 has been flushed, the first cycle for forming the first gap fill material 401 has been completed such that the first layer of thin film 505 remains at the bottom of the trench 301.

Referring to fig. 5D, once the first cycle for forming the first gap fill material 401 has been completed, a second cycle similar to the first cycle may begin. According to some embodiments, the second cycle may begin by forming another layer of the first monolayer 501 (e.g., dichlorosilane) over the film 505 of the first gap fill material 401. An instruction may be sent by the control unit 421 to the precursor gas controller 419 to disconnect the purge gas delivery system 435 and connect the first precursor delivery system 407 (containing the first precursor material) to the deposition and etch chamber 413 to initiate formation of the first monolayer 501. Once connected, first precursor delivery system 407 may deliver a first precursor material to showerhead 425. Thereby, another layer of the first monolayer 501 is formed over the film 505 and along the exposed surfaces of the fin structures 103.

When the first precursor material is adsorbed onto film 505 (e.g., silicon nitride) and fin structure 103, the first precursor material will react with the open active sites on the exposed surfaces of film 505 and fin structure 103. However, once film 505 and all open active sites on fin structure 103 have reacted with the first precursor material, the reaction stops because there are no open active sites that will bond with the first precursor material. This confinement causes the reaction of the first precursor material with the thin film 505 and the fin structure 103 to be self-limiting and form a monolayer of the reacted first precursor material (e.g., dichlorosilane) on the surfaces of the thin film 505 and the fin structure 103, allowing for more precise control of the thickness of the first monolayer 501. After the self-limiting reaction on film 505 and fin structure 103 has ended, deposition and etch chamber 413 may be purged of the first precursor material.

Continuing to fig. 5E, the second cycle may continue by reintroducing the first etch precursor (e.g., halide gas) to perform the partial etch of the first monolayer 501. An instruction may be sent by the control unit 421 to the precursor gas controller 419 to disconnect the purge gas delivery system 435 and reconnect the etch precursor delivery system 409 to begin reintroducing the first etch precursor to the deposition and etch chamber 413. Once reconnected, etch precursor delivery system 409 may deliver a first etch precursor to showerhead 425 to disperse the first etch precursor into deposition and etch chamber 413, where the first etch precursor is used to partially etch first monolayer 501 formed over thin film 505 and fin structure 103. According to some embodiments, the first monolayer 501 may be partially etched to a height equal to or below a desired height above the bottom of the trench 301 (e.g., the first height H1). Thereby, the unconsumed portion of the first monolayer 501 remains over the thin film 505 at the bottom of the trench 301 and the surface of the fin structure 103 is exposed above the first height H1.

Continuing to fig. 5F, a second cycle may continue by reintroducing a second precursor material (e.g., ammonia) to form another second monolayer 503 over the unconsumed portion of the first monolayer 501 within the trench 301. Reintroduction of the second precursor material into the deposition and etch chamber 413 may be initiated by the control unit 421 sending instructions to the precursor gas controller 419 to disconnect the purge gas delivery system 435 and reconnect the second precursor delivery system 411. Once reconnected, second precursor delivery system 411 may deliver a second precursor material to showerhead 425 to disperse the second precursor material into deposition and etch chamber 413. Thereby, a second monolayer 503 of a second precursor material may be adsorbed on the remaining surface of the unconsumed portion of the first monolayer 501 disposed over the first layer film 505. The second monolayer 503 reacts with the first precursor material of the first monolayer 501 in another self-limiting reaction to form another film 505 of a first gap fill material 401 (e.g., silicon nitride) over the first layer film 505.

After the self-limiting reaction has been completed and the second layer of film 505 has been formed, a third precursor may be purged from the deposition and etch chamber 413. Once the deposition and etch chamber 413 is flushed, the second cycle for forming the first gap fill material 401 has been completed such that the second layer of film 505 is disposed over the first layer of film 505 at the bottom of the trench 301.

Further cycles can be repeated in the manner previously disclosed to continue filling the trench 301 in the void-free and seamless deposition of the first gap fill material 401. These cycles may be repeated until the first gap fill material 401 fills the region of the trench 301 to a desired thickness (e.g., the first height H1). However, other desirable thicknesses of the first gap fill material 401 may be achieved by performing more cycles or fewer cycles, including filling and/or overfilling the trench 301. Once the first gap fill material 401 has reached a desired thickness, the substrate 101 may be removed from the deposition and etch chamber 413 for further processing.

However, as will be appreciated by those skilled in the art, the above-described process of forming the first gap fill material 401 is intended to be exemplary only and is not intended to be limiting to the embodiments. The first gap fill material 401 may be formed using any other suitable process and such suitable process shapes are fully intended to be included within the scope of the embodiments.

In some other embodiments, the first gap fill material 401 may be formed to not partially fill the trench 301 (described above), but to initially completely fill and/or overfill the trench 301 and cover the fin structure 103. In these other embodiments, a removal process is applied to the first gap fill material 401 to remove excess material of the first gap fill material 401 on the fin structure 103. In some embodiments, a planarization process such as Chemical Mechanical Polishing (CMP), an etch back process, a combination thereof, or the like may be utilized. The planarization process exposes the fin structure 103 such that the top surfaces of the fin structure 103 and the first gap fill material 401 are flush after the planarization process is completed.

Once planarized, the first gap fill material 401 is recessed to form the isolation region 105 to a desired height. According to some embodiments, the first gap fill material 401 is recessed to a desired height (e.g., the first height H1) and such that the upper portions of the fin structures 103 in the N-type region 201N and the P-type region 201P protrude from between adjacent isolation regions 105. Further, by using an appropriate etch, the top surface of the isolation region 105 may have a planar surface, a convex-like surface, a concave-like surface (such as a concave disk), or a combination thereof as illustrated. The isolation region 105 may be recessed using an acceptable etch process, such as an etch process that is selective to the material of the first gap fill material 401 (e.g., the material of the first gap fill material 401 is etched at a faster rate than the material of the fin structure 103). According to some embodiments, once the first gap fill material 401 has reached a desired thickness, an optional annealing process and/or an optional treatment (e.g., an oxidation process, a densification process, or the like) may be performed on the first gap fill material 401 to form the isolation region 105. Once the isolation regions 105 have been formed, the substrate 101 may be removed from the deposition and etch chamber 413 for further processing. Although isolation region 105 is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surface of the substrate 101 and the fin structure 103. Thereafter, a fill material such as those previously discussed may be formed over the liner.

Although the first gap-fill ald process 400 is illustrated with respect to forming the first gap-fill material 401 in the trench 301 in the finally formed isolation region 105 (see fig. 1), the first gap-fill ald process 400 may be utilized to fill other gaps when other structures are finally formed. The first gap-filling ald process 400 may be used to fill any target gap in which the first monolayer 501 reacts in a self-limiting reaction with a material in which the target gap is formed and in which the second monolayer 503 reacts in a self-limiting reaction with the first monolayer 501 to form a thin film of the first gap-filling material 401 in the target gap. Examples of other structures that may be formed using the first gap-fill atomic layer deposition process 400 include, but are not limited to, devices such as a dummy gate electrode, a gate spacer, a top spacer, a bottom spacer, a dummy mask, source/drain regions, a gate contact, a source/drain contact, a dielectric plug, or the like.

Moreover, the process described with reference to fig. 2-3 is only one example of how to form fin structure 103, and the process described with reference to fig. 4A-5F is only one example of how to form isolation region 105. In some embodiments, a heteroepitaxial structure may be used for the fin structure 103. For example, in embodiments where the first gap fill material 401 is initially formed to fill and overfill the trench 301 and prior to recessing the first gap fill material 401 to form the isolation region 105, the fin structure 103 may be recessed, and a different material than the fin structure 103 may be epitaxially grown on the recessed fin structure 103. In these embodiments, the fin structure 103 includes a recessed material and an epitaxially grown material disposed above the recessed material. In yet further embodiments, a homoepitaxial structure of a different material than the substrate 101 may be used for the fin structure 103. For example, in embodiments where the first gap fill material 401 is initially formed to fill and overfill the trench 301, the fin structure 103 may be recessed, and instead of the recessed fin structure 103, a different material may be epitaxially grown from the substrate 101. In these embodiments, the fin structure 103 comprises an epitaxially grown material grown from the substrate 101. In some embodiments where the homoepitaxial or heteroepitaxial structure is grown epitaxially, the epitaxially grown material may be doped in situ during the growth, and while in situ doping and implantation processes may be used together, in situ doping during the growth may eliminate the need for prior and subsequent implantation processes.

Still further, it may be advantageous to epitaxially grow a different material in N-type region 201N (e.g., an N-type metal oxide semiconductor region) than in P-type region 201P (e.g., a P-type metal oxide semiconductor region). In various embodiments, an upper portion of the fin structure 103 may be formed of silicon-germanium (Si)_xGe_1-xWhere x may be in the range of about 0 and 1), silicon carbide, pure or substantially pure germanium, tri-penta (III-V) compound semiconductors, di-hexa (II-VI) compound semiconductors, or the like. For example, useful materials for forming tri-penta (III-V) compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide (AlAs), gallium arsenide, indium phosphide, gallium nitride (GaN), indium gallium arsenide, aluminum indium arsenide, gallium antimonide (GaSb), aluminum antimonide (AlSb), aluminum phosphide (AlP), gallium phosphide, and the like.

In addition, appropriate wells (not shown) may be formed in fin structure 103 and/or substrate 101. In some embodiments, a P-type well may be formed in the N-type region 201N and an N-type well may be formed in the P-type region 201P. In some embodiments, a P-type well or an N-type well may be formed in both the N-type region 201N and the P-type region 201P.

In embodiments with different well types, photoresist and/or other masks (not shown) may be used to achieve different implantation steps for N-type region 201N and P-type region 201P. For example, photoresist may be formed over fin structures 103 and isolation regions 105 in N-type region 201N. The photoresist is patterned to expose P-type region 201P of substrate 101. The photoresist may be formed by using spin-on techniques and may be patterned using acceptable photolithographic process techniques. Once the photoresist is patterned, an N-type impurity implant is performed in P-type region 201P, and the photoresist may serve as a mask to substantially prevent N-type impurities from being implanted into N-type region 201N. The n-type impurity may be 10 or less¹⁸Per cubic centimeter, such as at about 10¹⁶Per cubic centimeter to about 10¹⁸Concentrations of between cubic centimeters are implanted into the region of phosphorus (P), arsenic (As), antimony (Sb) or the like. After the n-type impurity is implanted, the photoresist is removed (such as by an acceptable ashing process).

After the implantation of P-type region 201P, photoresist is formed over fin structures 103 and isolation region 105 in P-type region 201P. The photoresist is patterned to expose N-type region 201N of substrate 101. The photoresist may be formed by using spin-on techniques and may be patterned using acceptable photolithographic process techniques. Once the photoresist is patterned, a P-type impurity implant is performed in the N-type region 201N, and the photoresist may act as a mask to substantially prevent the P-type impurity from being implanted into the P-type region 201P. The p-type impurity may be 10 or less¹⁸Per cubic centimeter, such as at about 10¹⁶Per cubic centimeter to about 10¹⁸A concentration of between/cubic centimeter of boron (B), Boron Fluoride (BF), indium (In), or the like implanted into the region. After implantation, the photoresist may be removed (such as by an acceptable ashing process).

Following implantation of the N-type region 201N and the P-type region 201P, an anneal may be performed to repair implantation damage and activate the implanted P-type and/or N-type impurities. In some embodiments, the growth material of the epitaxial fin structure may be doped in-situ during growth, although in-situ doping may be used in conjunction with implantation processes, and may eliminate the need for prior and/or subsequent implantation processes during growth.

In fig. 6, after isolation regions 105 have been formed as previously described, a dummy dielectric layer 601 is formed on fin structure 103. The dummy dielectric layer 601 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and the dummy dielectric layer 601 may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 603 is formed over the dummy dielectric layer 601 and a mask layer 605 is formed over the dummy gate layer 603. Dummy gate layer 603 may be deposited over dummy dielectric layer 601 and then dummy gate layer 603 may be planarized, such as by chemical mechanical polishing. A mask layer 605 may be deposited over the dummy gate layer 603. The dummy gate layer 603 may be a conductive or non-conductive material, and may be selected from the group including: amorphous silicon, polysilicon, poly-silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 603 may be deposited by physical vapor deposition (pvd), chemical vapor deposition, sputter deposition, or other techniques for depositing selected materials. Dummy gate layer 603 may be made of other materials that have a high etch selectivity to the etching of adjacent materials, such as isolation region 105 and/or dummy dielectric layer 601. The mask layer 605 may comprise one or more layers of materials, such as silicon nitride, silicon oxynitride (SiON), or the like. In this example, a single dummy gate layer 603 and a single masking layer 605 are formed across the N-type region 201N and the P-type region 201P. It should be noted that dummy dielectric layer 601 is shown covering only portions of fin structure 103 extending above isolation region 105 for exemplary purposes only. In some embodiments, dummy dielectric layer 601 may be deposited such that dummy dielectric layer 601 covers portions of fin structure 103 extending above isolation region 105 and further covers isolation region 105. In these embodiments, dummy dielectric layer 601 separates dummy gate layer 603 from fin structure 103 and isolation region 105.

Fig. 7A-15B illustrate various additional steps in the fabrication of an embodiment element. Fig. 7A-15B illustrate features in either the N-type region 201N or the P-type region 201P. For example, the structures illustrated in fig. 7A-15B may be applied to both the N-type region 201N and the P-type region 201P. The differences, if any, in the structure of the N-type region 201N and the P-type region 201P are described in the text accompanying the figures.

In fig. 7A and 7B, the mask layer 605 (see fig. 6) may be patterned using acceptable photolithography and etching techniques to form a mask 701. The pattern of mask 701 may then be transferred to dummy gate layer 603. In some embodiments (not illustrated), the pattern of mask 701 may also be transferred to dummy dielectric layer 601 by acceptable etching techniques to form dummy gate 703. The dummy gate 703 covers a corresponding channel region 705 of the fin structure 103. The pattern of the mask 701 may be used to physically separate each dummy gate 703 from adjacent dummy gates 703. The dummy gate 703 may also have a longitudinal axis direction substantially perpendicular to a longitudinal axis direction of the corresponding fin structure 103.

Further in fig. 7A and 7B, gate seal spacers 707 may be formed on the dummy gate 703, the mask 701, and/or exposed surfaces of the fin structure 103. Thermal oxidation or deposition following the anisotropic etch may form the gate seal spacers 707. The gate seal spacers 707 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

After the formation of the gate seal spacers 707, an implant for lightly doped source/drain (ldd) regions (not explicitly illustrated) may be performed. In embodiments having different device types, similar to the implantation discussed above, upon exposing the P-type region 201P, a mask, such as photoresist, may be formed over the N-type region 201N, and appropriate type (e.g., P-type) impurities may be implanted into the exposed fin structures 103 in the P-type region 201P. The mask can then be removed. Subsequently, upon exposing the N-type region 201N, a mask (such as photoresist) may be formed over the P-type region 201P, and appropriate type (e.g., N-type) impurities may be implanted into the exposed fin structures 103 in the N-type region 201N. The mask can then be removed. The n-type impurity may be any of the n-type impurities discussed previously, and the p-type impurity may be any of the p-type impurities discussed previously. The lightly doped source/drain region may have a thickness of from about 10¹⁵Per cubic centimeter to about 10¹⁹Impurities in a concentration of/cubic centimetreAnd (4) quality. An annealing process may be used to repair implant damage and activate implanted impurities.

In fig. 8A and 8B, gate spacers 801 are formed on gate seal spacers 707 along the sidewalls of dummy gate 703 and mask 701. The gate spacers 801 may be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 801 may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, or the like.

It is noted that the foregoing disclosure generally describes the process of forming spacers and lightly doped source/drain regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, a different sequence of steps may be utilized (e.g., gate seal spacer 707 may be etched prior to forming gate spacer 801 to obtain an "L-shaped" seal spacer, spacers may be formed and removed, and/or the like). In addition, different structures and steps may be used to form n-type and p-type devices. For example, lightly doped source/drain regions for n-type elements may be formed before forming the gate seal spacers 707, while lightly doped source/drain regions for p-type elements may be formed after forming the gate seal spacers 707.

In fig. 9A to 9B, source/drain regions 111 are formed in the fin structure 103. Source/drain regions 111 are formed in fin structure 103 such that each dummy gate 703 is disposed between an adjacent pair of source/drain regions 111. In some embodiments, source/drain region 111 may extend into fin structure 103 and may also penetrate through fin structure 103. In some embodiments, gate spacers 801 are used to separate source/drain regions 111 from dummy gate 703 by an appropriate lateral distance so that source/drain regions 111 are not shorted to the resulting gate of a subsequently formed finfet. The material of the source/drain regions 111 may be selected to exert stress in the corresponding channel regions 705, thereby improving performance.

The source/drain regions 111 in the N-type region 201N may be formed by masking the P-type region 201P and etching the source/drain regions of the fin structure 103 in the N-type region 201N to form recesses in the fin structure 103. Next, source/drain regions 111 in N-type region 201N are epitaxially grown in the recess. The source/drain regions 111 may comprise any acceptable material such as is suitable for an n-type finfet. For example, if the fin structure 103 is silicon, the source/drain regions 111 in the N-type region 201N may comprise a material that exerts a tensile strain in the channel region 705, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide (SiP), or the like. The source/drain regions 111 in the N-type region 201N may have surfaces that protrude from corresponding surfaces of the fin structure 103 and may have facets.

The source/drain regions 111 in the P-type region 201P may be formed by masking the N-type region 201N and etching the source/drain regions of the fin structure 103 in the P-type region 201P to form recesses in the fin structure 103. Next, source/drain regions 111 in P-type region 201P are epitaxially grown in the recess. The source/drain regions 111 may comprise any acceptable material such as is suitable for a p-type finfet. For example, if fin structure 103 is silicon, source/drain regions 111 in P-type region 201P may comprise a material that exerts a compressive strain in channel region 705, such as silicon germanium, boron doped silicon germanium, germanium (Ge), germanium tin (GeSn), or the like. The source/drain regions 111 in the P-type region 201P may have surfaces that protrude from corresponding surfaces of the fin structure 103 and may have facets.

Similar to the processes discussed above for forming lightly doped source/drain regions, source/drain regions 111 and/or fin structure 103 may be implanted with dopants, followed by an anneal. The source/drain regions 111 may have a thickness of about 10a¹⁹Per cubic centimeter and about 10²¹Impurity concentration between cubic centimeters. The n-type and/or p-type impurities for source/drain regions 111 can be any of the impurities discussed previously. In some embodiments, the source/drain regions 111 may be doped in-situ during growth.

Due to the epitaxial process used to form the source/drain regions 111 in the N-type region 201N and the P-type region 201P, the upper surfaces of the epitaxial source/drain regions have facets that extend laterally outward beyond the sidewalls of the fin structure 103. In some embodiments, as illustrated in fig. 9C, these facets cause adjacent source/drain regions 111 of the same finfet to merge. In other embodiments, as illustrated in fig. 9D, the adjacent source/drain regions 111 remain separated after the epitaxial process is completed. In the embodiment illustrated in fig. 9C and 9D, gate spacers 801 are formed to cover the sidewalls of portions of fin structure 103 that extend above isolation region 105, thereby blocking epitaxial growth. In some other embodiments, the spacer etch used to form the gate spacers 801 may be adjusted to remove the spacer material to allow the epitaxially grown regions to extend to the surface of the isolation region 105.

In fig. 10A and 10B, a first interlayer dielectric (ILD) 1001 is deposited over the structure illustrated in fig. 9A and 9B. The first interlayer dielectric 1001 may be formed of a dielectric material, and the first interlayer dielectric 1001 may be deposited by any suitable method, such as chemical vapor deposition (cvd), Plasma Enhanced Chemical Vapor Deposition (PECVD), or Flowable Chemical Vapor Deposition (FCVD). The dielectric material may comprise phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), Undoped Silicate Glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a Contact Etch Stop Layer (CESL) 1003 is disposed between the first interlayer dielectric 1001 and the source/drain regions 111, the mask 701, and the gate spacers 801. The contact etch stop layer 1003 may comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a lower etch rate than the material of the first interlayer dielectric 1001 covering the contact etch stop layer 1003.

In fig. 11A and 11B, a planarization process, such as chemical mechanical polishing, may be performed to make the top surface of the first interlayer dielectric 1001 flush with the top surface of the dummy gate 703 or the mask 701. The planarization process may also remove the mask 701 over the dummy gate 703, and the gate seal spacer 707 and gate spacer 801 along portions of the sidewalls of the mask 701. After the planarization process, the top surfaces of the dummy gate 703, gate seal spacer 707, gate spacer 801 and first interlayer dielectric 1001 are flush. Accordingly, the top surface of the dummy gate 703 is exposed through the first interlayer dielectric 1001 and the contact etch stop layer 1003. In some embodiments, the mask 701 may remain, in which case the planarization process makes the top surface of the first interlayer dielectric 1001 flush with the top surface of the mask 701.

In fig. 12A and 12B, dummy gate 703 and mask 701 (if present) are removed in an etching step (or the like), thereby forming recess 1201. Portions of the dummy dielectric layer 601 in the recesses 1201 may also be removed. In some embodiments, only dummy gate 703 is removed and dummy dielectric layer 601 remains and is exposed by recess 1201. In some embodiments, the dummy dielectric layer 601 is removed from the recess 1201 in a first region (e.g., a core logic region) of the die and the dummy dielectric layer 601 remains in the recess 1201 in a second region (e.g., an input/output region) of the die. In some embodiments, the dummy gate 703 is removed by an anisotropic dry etch process. For example, the etching process may include a dry etching process using a reactive gas (es) that selectively etches the dummy gate 703 but does not etch or slightly etches the first interlayer dielectric 1001, the contact etch stop layer 1003, or the gate spacer 801. Each recess 1201 exposes and/or covers channel region 705 of a corresponding fin structure 103. Each channel region 705 is disposed between an adjacent pair of source/drain regions 111. During the removal process, the dummy dielectric layer 601 may be used as an etch stop layer when etching the dummy gate 703. After removal of the dummy gate 703, the dummy dielectric layer 601 may then be optionally removed.

In fig. 13A and 13B, a gate dielectric layer 107 and a gate electrode 109 are formed for the replacement gate. Fig. 13C illustrates a detailed view of region 1301 of fig. 13B. Gate dielectric layer 107 may be formed to be deposited over the top surface of fin structure 103 and to extend along one or more layers of the sidewalls of fin structure 103. Gate dielectric layer 107 may be further deposited within recess 1201 along the sidewalls of gate seal spacer 707 and/or gate spacer 801. The gate dielectric layer 107 may also be formed on the surface outside the recess 1201 on the top surface of the gate seal spacer 707, the gate spacer 801, the contact etch stop layer 1003, and the first interlayer dielectric 1001. In some embodiments, the gate dielectric layer 107 comprises one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, or the like. For example, in some embodiments, the gate dielectric layer 107 comprises an interfacial layer of silicon oxide formed by thermal or chemical oxidation and an overlying high-k dielectric material, such as a metal oxide or silicate of hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), manganese (Mn), barium (Ba), titanium (Ti), lead (Pb), and combinations thereof. The gate dielectric layer 107 may comprise a dielectric layer having a dielectric constant greater than about 7.0. The gate dielectric layer 107 may be formed by molecular-beam deposition (MBD), atomic layer deposition, electro-deposition enhanced chemical vapor deposition (pecvd), and the like. In embodiments where portions of dummy dielectric layer 601 remain in recesses 1201, gate dielectric layer 107 comprises the material (e.g., silicon oxide) of dummy dielectric layer 601.

Gate electrodes 109 are deposited over the gate dielectric layers 107, respectively, and the gate electrodes 109 fill the remaining portions of the recesses 1201. The gate electrode 109 may include a metal-containing material such as titanium nitride (TiN), titanium oxide (TiO), tantalum nitride (TaN), tantalum carbide (TaC), cobalt (Co), ruthenium (Ru), aluminum (Al), tungsten (W), a combination thereof, or a multilayer thereof. For example, although the gate electrode 109 is illustrated as a single layer in fig. 13B, the gate electrode 109 may include any number of liner layers 109A, any number of work function tuning layers 109B, and fill material 109C, as illustrated in fig. 13C. After filling the recess 1201, a planarization process, such as chemical mechanical polishing, may be performed to remove excess portions of the material of the gate dielectric layer 107 and the gate electrode 109, which are above the top surface of the first interlayer dielectric 1001. Thus, the material of the gate electrode 109 and the remaining portion of the gate dielectric layer 107 form a replacement gate for the resulting finfet. The gate electrode 109 and the gate dielectric layer 107 may be collectively referred to as a "gate stack". The gate and gate stack may extend along sidewalls of the channel region 705 of the fin structure 103.

The formation of the gate dielectric layers 107 in the N-type region 201N and the P-type region 201P may occur simultaneously such that the gate dielectric layers 107 in each region are formed of the same material, and the formation of the gate electrodes 109 may occur simultaneously such that the gate electrodes 109 in each region are formed of the same material. In some embodiments, the gate dielectric layer 107 in each region may be formed by a different process such that the gate dielectric layer 107 may be a different material, and/or the gate electrode 109 in each region may be formed by a different process such that the gate electrode 109 may be a different material. Various masking steps may be used to mask and expose the appropriate areas when different processes are used.

In fig. 14A and 14B, a gate mask 1401 is formed over the gate stack (including the gate dielectric layer 107 and the corresponding gate electrode 109), and the gate mask 1401 may be disposed between opposing portions of the gate spacer 801. In some embodiments, the step of forming the gate mask 1401 includes recessing the gate stack layer, thereby forming a recess directly above the gate stack layer and between opposing portions of the gate spacer 801. A gate mask 1401 comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride or the like, is filled into the recess, followed by a planarization process to remove excess portions of the dielectric material extending outside the recess and above the planar surface of the first interlayer dielectric 1001.

As also illustrated in fig. 14A and 14B, a second interlayer dielectric 1403 is deposited over the first interlayer dielectric 1001. In some embodiments, the second interlayer dielectric 1403 is a flowable film formed by a flowable cvd method. In some embodiments, the second interlayer dielectric 1403 is formed of a dielectric material of phosphosilicate glass, borosilicate glass, boron doped phosphosilicate glass, undoped silicate glass, or the like, and may be deposited by any suitable method, such as chemical vapor deposition and plasma enhanced chemical vapor deposition. A subsequently formed gate contact 1501 (fig. 15A and 15B) penetrates through the second interlayer dielectric 1403 and the gate mask 1401 to contact the top surface of the recessed gate electrode 109.

In fig. 15A and 15B, a gate contact 1501 and a source/drain contact 1503 are formed through the second interlayer dielectric 1403 and the first interlayer dielectric 1001, according to some embodiments. Openings for source/drain contacts 1503 are formed through the first interlayer dielectric 1001 and the second interlayer dielectric 1403, and openings for gate contacts 1501 are formed through the second interlayer dielectric 1403 and the gate mask 1401. The openings may be formed using acceptable photolithography and etching techniques. A liner (not shown), such as a diffusion barrier layer, adhesion layer, or the like, and a conductive material are formed in the opening. The liner may comprise titanium, titanium nitride, tantalum nitride, or the like. The conductive material may be copper (Cu), copper alloy, silver (Ag), gold (Au), tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as chemical mechanical polishing, may be performed to remove excess material from the surface of the second interlayer dielectric 1403. The remaining liner and conductive material form source/drain contacts 1503 and gate contacts 1501 in the openings. An anneal process may be performed to form a silicide at the interface between source/drain region 111 and source/drain contact 1503. Source/drain contact 1503 is physically and electrically coupled to source/drain region 111 and gate contact 1501 is physically and electrically coupled to gate electrode 109. The source/drain contact 1503 and the gate contact 1501 may be formed in different processes, or the source/drain contact 1503 and the gate contact 1501 may be formed in the same process. Although illustrated as being formed at the same cross-section, it is understood that each of the source/drain contacts 1503 and the gate contact 1501 can be formed at different cross-sections, which can avoid shorting of the contacts.

In accordance with yet other embodiments, a second gap-fill atomic layer deposition process 1600 is illustrated in fig. 16A-16F. For example, according to other embodiments, a second gap fill atomic layer deposition process 1600 may be used to form a second gap fill material 1603 in the trench 301 of fig. 3 when finally forming the isolation region 105. The second gap-fill atomic layer deposition process 1600 is similar to the first gap-fill atomic layer deposition process 400 illustrated in fig. 5A-5F; however, rather than depositing the second precursor over the first monolayer 501 to form the first gap fill material 401, the second gap fill atomic layer deposition process 1600 uses the third precursor to form the third monolayer 1601 over the fin structure 103 to form a thin layer accumulation of the second gap fill material 1603. According to some embodiments, the third monolayer 1601 is deposited layer by layer to form a thin layer build-up. In a particular embodiment, the second gap fill material 1603 may be used in void-free and seamless deposition of a dielectric film, such as silicon (Si), in the final configuration of the isolation region 105. Once the accumulation of the thin layer of the second gap fill material 1603 has reached a desired thickness, an alternative anneal process and/or an optional treatment (e.g., an oxidation treatment, a nitridation treatment, a densification treatment, or the like) may be performed on the second gap fill material 1603 to form the isolation region 105. However, the second gap-fill atomic layer deposition process 1600 and the second gap-fill material 1603 may be used to deposit a dielectric film in any gap in the final construction of a void-free and seamless structure within the gap. For example, once isolation region 105 has been formed, second gap-filling atomic layer deposition process 1600 may be used to form dummy gate layer 603 in the gaps between dummy dielectric layers 601 and over isolation region 105, as described above.

Although embodiments of the second gap-filling atomic layer deposition process 1600 are directed to forming the second gap-filling material 1603 in the final configuration of the isolation region 105 and/or the final configuration of the dummy gate layer 603, the second gap-filling atomic layer deposition process 1600 may be utilized to fill other gaps of the final configuration of other structures. The second gap-filling atomic layer deposition process 1600 may be used to fill any target gap in which the third monolayer 1601 reacts in a self-limiting reaction with a material in which a thin accumulation of the second gap-filling material 1603 is formed in the target gap, the thin accumulation being formed by deposition of the third monolayer 1601 in a layer-by-layer stack. Examples of other structures that may be formed using the second gap-fill atomic layer deposition process 1600 include, but are not limited to, structures such as dummy gate electrodes, gate spacers, top spacers, bottom spacers, dummy masks, source/drain regions, gate contacts, source/drain contacts, dielectric plugs, or the like.

Fig. 16A illustrates a deposition process of a third monolayer 1601 formed on the fin structure 103 and in the trench 301. According to some embodiments, deposition and etch system 405 uses a third precursor material to deposit third monolayer 1601 onto fin structure 103 and to deposit third monolayer 1601 within trench 301.

According to some embodiments, the third monolayer 1601 may be formed as a thin film (e.g., silane, Dichlorosilane (DCS), or the like) similar to the formation of the first monolayer 501 previously described with respect to fig. 5A. Thus, silane may be placed in first precursor delivery system 407.

In some embodiments, the deposition and etch system 405 uses a second etch precursor to etch the third monolayer 1601. The second etch precursor may be any etch precursor material suitable for the first etch precursor described above with reference to fig. 5B. In this example, hydrogen (H)₂) The plasma is used as a second etching material for partially etching the third monolayer 1601. Thereby, hydrogen (H) is introduced₂) Is disposed within etch precursor delivery system 409.

Once the third precursor material and the second precursor have been placed in first precursor delivery system 407 and etch precursor delivery system 409, respectively, instructions may be sent by control unit 421 to precursor gas controller 419 to connect first precursor delivery system 407 to deposition and etch chamber 413 to begin forming second gap fill material 1603. Once connected, first precursor delivery system 407 may deliver a third precursor material (e.g., silane) to showerhead 425 via precursor gas controller 419 and manifold 423. The showerhead 425 may then dispense a third precursor material into the deposition and etch chamber 413. According to some embodiments, a third precursor material may be flowed into deposition and etch chamber 413 using any suitable process conditions for depositing such materials, wherein the third precursor material may be adsorbed by and react with the exposed surfaces of substrate 101 and fin structure 103. Thereby, a monolayer of reacted third precursor material is formed in the reaction on the surface of the substrate 101 and the fin structure 103, allowing for more precise control of the thickness of the third monolayer 1601.

After the third monolayer 1601 has been formed, the third precursor material in the deposition and etch chamber 413 may be purged using the precursor gas controller 419 and/or vacuum pump 433, as previously discussed, to facilitate removal of the third precursor material. The purge gas may purge the third precursor material from the deposition and etch chamber 413 for about 3 seconds along with the vacuum pump 433. However, any suitable time may be used.

Referring to fig. 16B, after the purging of the third precursor material has been completed, instructions may be sent by the control unit 421 to the precursor gas controller 419 to disconnect the purge gas delivery system 435 and connect the etch precursor delivery system 409 (containing the second etch precursor) to the deposition and etch chamber 413 to begin introducing the second etch precursor (e.g., a hydrogen gas plasma) into the deposition and etch chamber 413. Once connected, etch precursor delivery system 409 may deliver a second etch precursor to showerhead 425. Next, the showerhead 425 may dispense a second etch precursor (e.g., a hydrogen plasma) into the deposition and etch chamber 413, where the second etch precursor may be used to partially etch the third monolayer 1601.

According to some embodiments, any suitable process conditions may be used to flow a second etch precursor into the deposition and etch chamber 413 for etching a material such as the third monolayer 1601, where the second etch precursor may react with exposed surfaces of the third monolayer 1601. According to some embodiments, the third monolayer 1601 may be partially etched to a desired height equal to or below the bottom of the trench 301 (e.g., the second height H2 is between about 20 nanometers and about 50 nanometers). According to some embodiments, the partial etch is a dry etch or a plasma etch and is timed to stop at a desired height within the trench 301. However, any suitable etch process time and/or process conditions may be used. Thereby, the unconsumed portion of the third monolayer 1601 remains at the bottom of the trench 301. In a particular embodiment where the second gap fill material 1603 is ultimately formed into the isolation regions 105, the second height H2 may be a desired height of the isolation regions 105 between about 20 nanometers and about 50 nanometers. However, any suitable height may be used. Thereby, the surface of the fin structure 103 is exposed above the second height H2 by the partial etching of the third single layer 1601.

After the partial etch of the third monolayer 1601 is completed, the deposition and etch chamber 413 may be flushed of a second etch precursor. For example, the control unit 421 may instruct the precursor gas controller 419 to disconnect the etch precursor delivery system 409 (containing the second etch precursor to be purged from the deposition and etch chamber 413) and connect the purge gas delivery system 435 to deliver the purge gas to the deposition and etch chamber 413. In addition, the control unit 421 may also activate the vacuum pump 433 to apply a pressure differential to the deposition and etch chamber 413 to facilitate removal of the second etch precursor. The purge gas may purge the second etch precursor from the deposition and etch chamber 413 for about 3 seconds along with the vacuum pump 433. However, any suitable time may be used.

Referring to fig. 16C, after the purging of the second etch precursor has been completed, instructions may be sent by control unit 421 to precursor gas controller 419 to disconnect purge gas delivery system 435 to reintroduce the third precursor material into deposition and etch chamber 413 and reconnect first precursor delivery system 407 (containing the third precursor material) to deposition and etch chamber 413. Once connected, first precursor delivery system 407 may deliver a third precursor material to showerhead 425. Next, showerhead 425 may dispense a third precursor material into deposition and etch chamber 413, where the third precursor material may be used to form another layer of third monolayer 1601 over the unconsumed portions of third monolayer 1601 and over the exposed portions of fin structure 103.

Once connected, the third precursor material may flow into the deposition and etch chamber 413, where the third precursor material may be adsorbed and react in another reaction on the unconsumed portions of the third monolayer 1601 and the exposed surfaces of the fin structure 103 to form a subsequent thin film of the third monolayer 1601. Thereby, an accumulation of second gap fill material 1603, e.g., silicon (Si), is formed within trench 301. After the subsequent thin films of the third monolayer 1601 have been formed, the deposition and etch chamber 413 may be purged of the third precursor material, as previously discussed.

Referring to fig. 16D, after the flush of the third precursor material has been completed, a second etch precursor (e.g., a hydrogen plasma) may be reintroduced into the deposition and etch chamber 413 via the etch precursor delivery system 409, as previously discussed. Once the etch precursor delivery system 409 has been reconnected, a second etch precursor may be dispensed into the deposition and etch chamber 413 through the showerhead 425, where the second etch precursor is used to partially etch subsequent thin films of the third monolayer 1601 to a second height H2. Once the partial etching of the subsequent thin films of the third monolayer 1601 has ended, the deposition and etch chamber 413 may be flushed of a second etch precursor, as previously discussed.

Continuing to fig. 16E, after the purging of the second etch precursor has been completed, yet another thin layer of the third monolayer 1601 may be formed over the unconsumed portion of the third monolayer 1601 to increase the accumulation of the second gap fill material 1603, e.g., silicon (Si). By performing another cycle as described above, i.e., deposition and reaction of a third precursor material (e.g., Dichlorosilane (DCS)), purging of the deposition and etch chamber 413 of the third precursor material, subsequent partial etch using a second etch precursor (e.g., hydrogen plasma) and purging of the second etch precursor, a further thin layer of the third monolayer 1601 may be formed to increase the accumulation of the second gap fill material 1603.

Referring now to fig. 16F, after the purging of the second etch precursor has been completed, another thin layer of the third monolayer 1601 may also be formed over the unconsumed portions of the third monolayer 1601 to further increase the accumulation of the second gap fill material 1603, e.g., silicon (Si). By performing yet further cycles of third precursor material deposition and reaction, purging of the third precursor material in the deposition and etch chamber 413, subsequent partial etching using the second etch precursor (e.g., hydrogen plasma), and purging of the second etch precursor as previously described, a yet further thin layer of the third monolayer 1601 may be formed to increase the accumulation of the second gap fill material 1603.

Further cycles may be repeated in the manner previously disclosed to continue filling the trench 301 in the void-free and seamless deposition of the second gap fill material 1603. These cycles may be repeated until the second gap fill material 1603 fills the region of the trench 301 to a desired thickness (e.g., the second height H2). However, other desired thicknesses of the second gap fill material 1603 may be achieved by performing more cycles or fewer cycles, including filling and/or overfilling the trench 301. According to some embodiments, once the second gap fill material 1603 has reached a desired thickness, an alternative annealing process and/or an alternative treatment (e.g., an oxidation treatment, a densification treatment, or the like) may be performed on the second gap fill material 1603 to form the isolation region 105. Once the isolation regions 105 have been formed, the substrate 101 may be removed from the deposition and etch chamber 413 for further processing.

In accordance with embodiments disclosed herein, semiconductor devices, such as finfet devices, may be formed using the methods and systems described herein. In particular, embodiments are disclosed of methods and systems for forming a dielectric material in a trench that may have one or more of the following advantages and/or benefits. The disclosed method of depositing a first precursor material in a self-limiting reaction with material along the sidewalls and exposed surfaces at the bottom of the trench allows for precise control of the deposition of the first precursor material. Etching of the first precursor material from the upper portion of the trench allows for precise deposition of the second precursor material in a self-limiting reaction between the first precursor material and the second precursor material to form a monolayer of desirable dielectric material within the trench. Furthermore, the formation of these monolayers enables the selective deposition of dielectric films on target surfaces of arbitrary thickness. Thus, the dielectric structure can be formed seamlessly and without voids in a bottom-up process that can be scaled to very small trenches (e.g., trenches having an aspect ratio between about 5: 1 to about 20: 1). Furthermore, these deposition methods allow for precise deposition and control of the gap fill material to be seamless and void-free, even in trenches containing overhang structures or sloped configurations. Thereby, improved device performance and yield are achieved.

The disclosed finfet embodiments may also be applied to nanostructured devices such as nanostructured (e.g., nano-sheet, nano-wire, fully-wrapped-gate, or the like) field effect transistors (NSFETs). In the nanostructured field effect transistor embodiment, the fin structures are replaced by nanostructured fin structures formed by patterning alternating layer stacks of a channel layer and a sacrificial layer. The dummy gate stack and source/drain regions are formed in a manner similar to the embodiments described above. After removing the dummy gate stack, the sacrificial layer may be partially or fully removed in the channel region. Replacement gate structures are formed in a manner similar to the embodiments described above, which may partially or completely fill the opening left by the removal of the sacrificial layer, and which may partially or completely surround the channel layer in the channel region of the nanostructured field effect transistor element. The interlayer dielectric and the contacts and source/drain regions of the replacement gate structure may be formed in a manner similar to the embodiments described above. The nanostructured elements may be formed as disclosed in U.S. patent application publication No. 2016/0365414, which is incorporated herein by reference in its entirety.

In some embodiments, a method of fabricating a semiconductor device includes: a first precursor is introduced into the trench such that a portion of the first precursor reacts with sidewalls of the trench to form a first precursor product. The first precursor product is etched to expose an upper portion of the sidewalls of the trench. A second precursor is introduced into the trench such that a portion of the second precursor reacts with the first precursor product.

In some embodiments, the first precursor comprises silane.

In some embodiments, the step of etching the first precursor product uses a hydrogen plasma.

In some embodiments, the second precursor comprises ammonia.

In some embodiments, the second precursor is the same as the first precursor.

In some embodiments the first precursor comprises a metal.

In some embodiments, the trench is located within the dielectric material.

In other embodiments, a method of fabricating a semiconductor device includes: a first precursor layer is formed along the exposed surface in the gap in a self-limiting reaction between the first precursor and the exposed surface. The surface of the portion in the upper portion of the gap is re-exposed by partially etching the first precursor layer. A second precursor layer is formed along the remaining portion of the first precursor layer.

In some embodiments, forming the second precursor layer includes forming a monolayer of the second material in a self-limiting reaction between the first precursor layer and the second precursor layer.

In some embodiments, the monolayer of the second material comprises silicon.

In some embodiments, the monolayer of the second material comprises a metal.

In some embodiments, forming the second precursor layer further includes forming the second precursor layer along the re-exposed surface in the gap.

In some embodiments, the second precursor layer is the same as the first precursor layer.

In some embodiments, etching the first precursor layer includes using a hydrogen plasma.

In some embodiments, forming the first precursor layer includes forming a first silicon layer.

In yet other embodiments, a method of fabricating a semiconductor device includes: a trench is formed in the first material. A first monolayer of a first precursor material is formed along sidewalls and a bottom of the trench. The first monolayer is partially removed along an upper portion of the sidewalls of the trench. A second monolayer of a second precursor material is formed over the remaining portion of the first monolayer within the trench.

In some embodiments, forming the first monolayer comprises forming a first film layer within the trench in a first self-limiting reaction.

In some embodiments, partially removing the first monolayer comprises using a halide gas.

In some embodiments, forming the second monolayer comprises forming a second film layer in a second self-limiting reaction.

In some embodiments, forming the second monolayer includes forming a second film layer over the first monolayer, the second film layer and the first film layer including the same material.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such effective constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of fabricating a semiconductor device, comprising:

introducing a first precursor into a trench such that a portion of the first precursor reacts with sidewalls of the trench to form a first precursor product;

etching the first precursor product to expose upper portions of the sidewalls of the trench; and

a second precursor is introduced into the trench such that a portion of the second precursor reacts with the first precursor product.

2. The method of claim 1, wherein the first precursor comprises silane.

3. The method of claim 1, wherein the first precursor comprises a metal.

4. The method of claim 1 wherein the trench is in a dielectric material.

5. A method of fabricating a semiconductor device, comprising:

forming a first precursor layer along exposed surfaces in a gap in a self-limiting reaction between a first precursor and the exposed surfaces;

re-exposing a surface of a portion of the upper portion of the gap by partially etching the first precursor layer; and

a second precursor layer is formed along a remaining portion of the first precursor layer.

6. The method of claim 5, wherein forming the second precursor layer comprises:

a monolayer of a second material is formed in a self-limiting reaction between the first precursor layer and a second precursor.

7. The method of claim 5, wherein forming the second precursor layer further comprises:

the second precursor layer is formed along the re-exposed surface in the gap.

8. A method of fabricating a semiconductor device, comprising:

forming a trench in a first material;

forming a first monolayer of a first precursor material along sidewalls and a bottom of the trench;

partially removing the first monolayer along an upper portion of the plurality of sidewalls of the trench; and

a second monolayer of a second precursor material is formed over a remaining portion of the first monolayer within the trench.

9. The method of claim 8, wherein forming the first monolayer comprises forming a first layer in the trench in a first self-limiting reaction.

10. The method of claim 8, wherein forming the second monolayer comprises forming a second layer in a second self-limiting reaction.