CN113066725B - Transistor and manufacturing method thereof - Google Patents
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- CN113066725B CN113066725B CN202110286665.3A CN202110286665A CN113066725B CN 113066725 B CN113066725 B CN 113066725B CN 202110286665 A CN202110286665 A CN 202110286665A CN 113066725 B CN113066725 B CN 113066725B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
- 238000002955 isolation Methods 0.000 claims abstract description 52
- 238000000034 method Methods 0.000 claims abstract description 42
- 239000004065 semiconductor Substances 0.000 claims abstract description 41
- 230000004888 barrier function Effects 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 6
- 230000008569 process Effects 0.000 abstract description 18
- 230000010354 integration Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 239000002070 nanowire Substances 0.000 description 6
- 230000009471 action Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a transistor and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: providing an isolation layer; forming a semiconductor layer on the insulating layer; forming a barrier layer on one side of the semiconductor layer, which is far away from the isolation layer, wherein the barrier layer covers the isolation region of the semiconductor layer; carrying out doping treatment on other regions of the semiconductor layer to form a source electrode and a drain electrode, wherein the isolation region is positioned between the source electrode and the drain electrode; forming a mask layer on the side wall of the barrier layer, wherein the mask layer covers a partial region of the source electrode and a partial region of the drain electrode; and carrying out etching treatment to etch away the source electrode region and the drain electrode region which are not covered by the mask layer. By etching the source and drain regions, a smaller and more integrated transistor architecture is achieved with reduced source and drain dimensions. Compared with the manufacturing method of the exposure technology, the source electrode and the drain electrode with smaller sizes can be realized on the premise of simple process.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a transistor and a manufacturing method thereof.
Background
With the continuous development of science and technology, the number of transistors that can be accommodated in an integrated circuit is continuously increasing according to moore's law, which requires the size of the transistors to be continuously reduced, and the difficulty of manufacturing the transistors is also increased.
Therefore, how to manufacture a transistor with higher integration is a technical problem to be solved urgently by those skilled in the art.
Disclosure of Invention
In view of this, in order to solve the above problems, the present invention provides a transistor and a method for manufacturing the same, and the technical solution is as follows:
a method of fabricating a transistor, the method comprising:
providing an isolation layer;
forming a semiconductor layer on one side of the isolation layer;
forming a barrier layer on one side of the semiconductor layer, which faces away from the isolation layer, wherein the barrier layer covers the isolation region of the semiconductor layer;
carrying out doping treatment on other regions of the semiconductor layer to form a source electrode and a drain electrode, wherein the isolation region is positioned between the source electrode and the drain electrode;
forming a mask layer on the side wall of the barrier layer, wherein the mask layer covers a partial region of the source electrode and a partial region of the drain electrode;
and carrying out etching treatment to etch away the source electrode region and the drain electrode region which are not covered by the mask layer.
Optionally, in the above manufacturing method, before forming the semiconductor layer on the isolation layer, the manufacturing method further includes:
and forming a grid electrode on the isolation layer, wherein the grid electrode penetrates through the source electrode, the isolation region and the drain electrode.
Optionally, in the above manufacturing method, the gate includes a plurality of independent gate units;
the independent grid units are arranged at equal intervals.
Optionally, in the above manufacturing method, the gate unit is strip-shaped;
the strip-shaped extending direction penetrates through the source electrode, the isolation region and the drain electrode.
Optionally, in the above manufacturing method, the doping other regions of the semiconductor layer to form a source and a drain includes:
and carrying out P-type doping treatment on other regions of the semiconductor layer to form a source electrode and a drain electrode.
Optionally, in the above manufacturing method, the doping other regions of the semiconductor layer to form a source and a drain includes:
and carrying out N-type doping treatment on other regions of the semiconductor layer to form a source electrode and a drain electrode.
Optionally, in the manufacturing method, forming a mask layer on a sidewall of the barrier layer includes:
and forming a mask layer on the side wall of the barrier layer by adopting a Mandrel technology.
A transistor, the transistor comprising:
an insulating layer;
a source electrode and a drain electrode both disposed at one side of the insulating layer;
an isolation region disposed between the source and the drain.
Optionally, in the above transistor, the transistor further includes:
and the grid electrode is arranged on the isolation layer and penetrates through the source electrode, the isolation region and the drain electrode.
Optionally, in the transistor, the gate includes a plurality of independent gate units;
the independent grid units are arranged at equal intervals;
the grid unit is strip-shaped;
the strip-shaped extending direction penetrates through the source electrode, the isolation region and the drain electrode.
Compared with the prior art, the invention has the following beneficial effects:
the manufacturing method of the transistor provided by the invention comprises the following steps: providing an isolation layer; forming a semiconductor layer on one side of the isolation layer; forming a barrier layer on one side of the semiconductor layer, which faces away from the isolation layer, wherein the barrier layer covers the isolation region of the semiconductor layer; carrying out doping treatment on other regions of the semiconductor layer to form a source electrode and a drain electrode, wherein the isolation region is positioned between the source electrode and the drain electrode; forming a mask layer on the side wall of the barrier layer, wherein the mask layer covers a part of the source electrode and a part of the drain electrode; and carrying out etching treatment to etch away the source electrode region and the drain electrode region which are not covered by the mask layer. By adopting the manufacturing method to etch the source electrode region and the drain electrode region, a transistor framework with smaller size and higher integration level is realized under the condition of reducing the sizes of the source electrode and the drain electrode. Compared with the manufacturing method of the exposure technology, the manufacturing method can realize the source electrode and the drain electrode with smaller sizes on the premise of simple process.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a transistor in the prior art;
FIG. 2 is a schematic diagram of another prior art transistor structure;
fig. 3 is a schematic flow chart illustrating a method for manufacturing a transistor according to an embodiment of the present invention;
FIGS. 4-10 are schematic structural diagrams corresponding to the manufacturing method shown in FIG. 3;
fig. 11 is a schematic flowchart illustrating a manufacturing method of another transistor according to an embodiment of the present invention;
FIG. 12 is a schematic structural diagram corresponding to the method of FIG. 11;
FIG. 13 is a schematic view of a doping process according to an embodiment of the present invention;
fig. 14 is a schematic view of another doping process according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
In the process of the invention, the inventor finds that in a 7nm or 5nm semiconductor process, a Fin-type Transistor (FinFET for short) cannot meet the actual requirement, so that a Gate-All-Around FET (Gate-All-Around FET) is widely used, and the control force on a Gate is more effective in addition to further size reduction.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a transistor in the prior art.
As shown in fig. 1, the transistor is of a GAA (Gate-All-Around) Horizontal architecture, i.e., a Horizontal architecture.
The Drain Drain, the Source and the Gate are planar structures, and the capacitance between the Drain and the Gate and the capacitance between the Source and the Gate are relatively large, so that the RC delay is caused to the circuit, and the operation speed of the circuit is further influenced.
It should be noted that the Drain, the Source, and the Gate are connected by a nanowire structure.
Furthermore, due to the limitation of the current exposure technology, the Drain electrode Drain, the Source electrode Source and the Gate electrode cannot be made smaller, and thus the integration of the transistor cannot be improved.
Referring to fig. 2, fig. 2 is a schematic structural diagram of another transistor in the prior art.
As shown in fig. 2, the transistor has a GAA (Gate-All-Around) Vertical structure, i.e., a Vertical structure. The nanowire structure is in a vertical direction, so that the utilization rate of the transistor can be further increased.
The Drain Drain, the Source and the Gate are planar structures, and the capacitance between the Drain and the Gate and the capacitance between the Source and the Gate are relatively large, so that the RC delay is caused to the circuit, and the operation speed of the circuit is further influenced.
An isolation layer (it should be noted that, as shown in fig. 2, no isolation layer is shown) is required to be disposed between the Drain and the Gate and between the Source and the Gate to isolate the Drain, source and Gate, respectively.
Therefore, the transistor with the above structure has a large number of layers in the vertical direction, and the integration level of the transistor cannot be improved.
Furthermore, since the transistor of the architecture is a stacked structure in the vertical direction, when a film is fabricated, the previously fabricated film is still affected by the current process for fabricating the film, and the transistor finally has an obvious electrical property difference due to the process difference.
Based on the transistor, the invention provides a novel transistor, improves the manufacturing method thereof and realizes a transistor with high integration level and high performance.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 3, fig. 3 is a schematic flow chart illustrating a method for manufacturing a transistor according to an embodiment of the present invention.
The manufacturing method comprises the following steps:
s101: as shown in fig. 4, an insulating layer 11 is provided.
In this step, the material, thickness, and other parameters of the insulating layer 11 are provided in the embodiment of the present invention, and are not limited.
It should be noted that the isolation layer 11 is generally disposed on a substrate, which is not shown in the figure.
S102: as shown in fig. 5, a semiconductor layer 12 is formed on one side of the isolation layer 11.
In this step, the semiconductor layer 12 is mainly used to form a source electrode and a drain electrode, and isolate the source electrode and the drain electrode, and parameters such as material and thickness thereof are not limited in the embodiment of the present invention.
S103: as shown in fig. 6, a barrier layer 13 is formed on a side of the semiconductor layer 12 facing away from the isolation layer 11, and the barrier layer 13 covers an isolation region of the semiconductor layer 12.
In this step, the size of the isolation region where the barrier layer 13 covers the semiconductor layer 12 is set appropriately based on the requirement of transistor integration.
S104: as shown in fig. 7, the other region of the semiconductor layer 12 is doped to form a source electrode and a drain electrode, and the isolation region is located between the source electrode and the drain electrode.
S105: as shown in fig. 8, a mask layer 14 is formed on the sidewall of the barrier layer 13, and the mask layer 14 covers a partial region of the source and a partial region of the drain.
In this step, the mask layer 14 is appropriately set to cover the source and the drain in size based on the requirement of transistor integration level.
S106: as shown in fig. 9, an etching process is performed to etch away the source and drain regions not covered by the mask layer 14.
As shown in fig. 10, the barrier layer 13 and the mask layer 14 are removed.
In the embodiment, the source region and the drain region are etched by adopting the manufacturing method, and a transistor framework with smaller size and higher integration level is realized under the condition of reducing the sizes of the source and the drain.
Compared with the manufacturing method of the exposure technology, the manufacturing method can realize the source electrode and the drain electrode with smaller sizes on the premise of simple process.
Further, based on the above embodiments of the present invention, referring to fig. 11, fig. 11 is a schematic flowchart of another method for manufacturing a transistor according to an embodiment of the present invention.
Before forming the semiconductor layer 12 on one side of the isolation layer 11, the manufacturing method further includes:
s107: a gate electrode is formed at one side of the isolation layer 11, and the gate electrode penetrates the source electrode, the isolation region, and the drain electrode.
Alternatively, as shown in fig. 12, the gate includes a plurality of independent gate units; the grid unit is strip-shaped; the strip-shaped extending direction penetrates through the source electrode, the isolation region and the drain electrode.
Optionally, a plurality of independent gate units are arranged at equal intervals.
In this embodiment, the gate structure of the nanowire structure is adopted, and an additional nanowire structure is not required to be arranged, so that the size of the transistor can be further reduced, and the integration level of the transistor can be improved.
And the capacitance values of the source electrode, the grid electrode, the drain electrode and the grid electrode are also greatly reduced, so that the RC delay of the circuit is reduced, and the operation speed of the circuit is improved.
Further, the series connection can be directly realized between the same transistors in the horizontal direction.
It should be noted that an insulating layer is disposed between each gate unit and the source, the isolation region, and the drain.
Further, based on the above embodiment of the present invention, the doping processing on other regions of the semiconductor layer 12 to form a source electrode and a drain electrode includes:
and carrying out P-type doping treatment on other regions of the semiconductor layer 12 to form a source electrode and a drain electrode.
In this embodiment, referring to fig. 13, fig. 13 is a schematic view of a doping process provided by an embodiment of the invention, in which a P-type doping process is performed on other regions of the semiconductor layer 12 by using a P-type doping method to form a source and a drain.
Further, according to the above embodiment of the present invention, the doping the other region of the semiconductor layer 12 to form the source and the drain includes:
and carrying out N-type doping treatment on other regions of the semiconductor layer 12 to form a source electrode and a drain electrode.
In this embodiment, referring to fig. 14, fig. 14 is a schematic view of another doping process provided in the embodiment of the present invention, in which an N-type doping process is performed on other regions of the semiconductor layer 12 by using an N-type doping method to form a source and a drain.
Further, based on the above embodiment of the present invention, the forming a mask layer 14 on the sidewall of the barrier layer 13 includes:
a masking layer 14 is formed on the sidewalls of the barrier layer 13 using the Mandrel technique.
In this embodiment, the Mandrel technique is also called a self-aligned dual imaging technique, and compared with the manufacturing method of the exposure technique, the source and the drain with smaller sizes can be realized on the premise of simple process.
Further, based on all the above embodiments of the present invention, in another embodiment of the present invention, there is provided a transistor, as shown in fig. 12, the transistor includes:
an insulating layer 11;
a source electrode and a drain electrode both disposed at one side of the insulating layer 11;
an isolation region 12 disposed between the source and the drain.
The transistor further includes:
and the grid electrode is arranged on the isolation layer and penetrates through the source electrode, the isolation region and the drain electrode.
The gate comprises a plurality of independent gate units;
the independent grid units are arranged at equal intervals;
the grid unit is in a strip shape;
the strip-shaped extending direction penetrates through the source electrode, the isolation region and the drain electrode.
In this embodiment, the transistor is a high-integration transistor structure, and the gate structure of the nanowire structure is adopted, so that an additional nanowire structure is not required, the size of the transistor can be further reduced, and the integration level of the transistor is improved.
And the capacitance values of the source electrode, the grid electrode, the drain electrode and the grid electrode are also greatly reduced, so that the RC delay of the circuit is reduced, and the operation speed of the circuit is improved.
Further, the series connection can be directly realized between the same transistors in the horizontal direction.
The above detailed description is provided for a transistor and a method for manufacturing the same, and the principle and the implementation of the present invention are explained in detail by applying specific examples, and the descriptions of the above examples are only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include or include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A method for manufacturing a transistor, the method comprising:
providing an isolation layer;
forming a semiconductor layer on one side of the isolation layer;
forming a barrier layer on one side of the semiconductor layer, which is far away from the isolation layer, wherein the barrier layer covers the isolation region of the semiconductor layer;
carrying out doping treatment on other regions of the semiconductor layer to form a source electrode and a drain electrode, wherein the isolation region is positioned between the source electrode and the drain electrode;
forming a mask layer on the side wall of the barrier layer, wherein the mask layer covers a part of the source electrode and a part of the drain electrode;
etching to remove the source region and the drain region uncovered by the mask layer;
before forming a semiconductor layer on the isolation layer, the manufacturing method further comprises:
and forming a grid electrode on the isolation layer, wherein the grid electrode penetrates through the source electrode, the isolation region and the drain electrode.
2. The method of claim 1, wherein the gate comprises a plurality of independent gate units;
the independent grid units are arranged at equal intervals.
3. The method of claim 2, wherein the gate unit is shaped as a stripe;
the strip-shaped extending direction penetrates through the source electrode, the isolation region and the drain electrode.
4. The method of claim 1, wherein doping the other region of the semiconductor layer to form a source and a drain comprises:
and carrying out P-type doping treatment on other regions of the semiconductor layer to form a source electrode and a drain electrode.
5. The method of claim 1, wherein the doping the other region of the semiconductor layer to form a source and a drain comprises:
and carrying out N-type doping treatment on other regions of the semiconductor layer to form a source electrode and a drain electrode.
6. The method of claim 1, wherein forming a mask layer on sidewalls of the barrier layer comprises:
and forming a mask layer on the side wall of the barrier layer by adopting a Mandrel technology.
7. A transistor, wherein the transistor comprises:
an insulating layer;
a source electrode and a drain electrode both disposed at one side of the insulating layer;
an isolation region disposed between the source electrode and the drain electrode;
the transistor further includes:
and the grid electrode is arranged on the isolation layer and penetrates through the source electrode, the isolation region and the drain electrode.
8. The transistor of claim 7, wherein the gate comprises a plurality of independent gate cells;
the independent grid units are arranged at equal intervals;
the grid unit is in a strip shape;
the strip-shaped extending direction penetrates through the source electrode, the isolation region and the drain electrode.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102768957A (en) * | 2011-05-06 | 2012-11-07 | 中国科学院微电子研究所 | Fin field effect transistor and manufacturing method thereof |
| CN104900521A (en) * | 2014-03-04 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Fin field-effect transistor and forming method thereof |
| CN109037069A (en) * | 2017-06-09 | 2018-12-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112309856A (en) * | 2019-07-24 | 2021-02-02 | 中芯国际集成电路制造（天津）有限公司 | Method for forming semiconductor structure |
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| US9324830B2 (en) * | 2014-03-27 | 2016-04-26 | International Business Machines Corporation | Self-aligned contact process enabled by low temperature |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102768957A (en) * | 2011-05-06 | 2012-11-07 | 中国科学院微电子研究所 | Fin field effect transistor and manufacturing method thereof |
| CN104900521A (en) * | 2014-03-04 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Fin field-effect transistor and forming method thereof |
| CN109037069A (en) * | 2017-06-09 | 2018-12-18 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN112309856A (en) * | 2019-07-24 | 2021-02-02 | 中芯国际集成电路制造（天津）有限公司 | Method for forming semiconductor structure |
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