CN113065424A - Fingerprint identification structure, preparation method thereof, display substrate and display device - Google Patents
Fingerprint identification structure, preparation method thereof, display substrate and display device Download PDFInfo
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- CN113065424A CN113065424A CN202110296686.3A CN202110296686A CN113065424A CN 113065424 A CN113065424 A CN 113065424A CN 202110296686 A CN202110296686 A CN 202110296686A CN 113065424 A CN113065424 A CN 113065424A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/12—Fingerprints or palmprints
- G06V40/13—Sensors therefor
- G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V10/00—Arrangements for image or video recognition or understanding
- G06V10/10—Image acquisition
- G06V10/12—Details of acquisition arrangements; Constructional details thereof
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Abstract
The application provides a fingerprint identification structure and a preparation method thereof, a display substrate and a display device, wherein the fingerprint identification structure comprises: a plurality of first lower electrodes disposed above the substrate at intervals; a first insulating layer over the first lower electrode; a plurality of second lower electrodes disposed above the first insulating layer at intervals; wherein the orthographic projection of the first lower electrode on the substrate and the orthographic projection of the second lower electrode on the substrate are alternately arranged at intervals; a second insulating layer over the second lower electrode; a plurality of first upper electrodes disposed above the second insulating layer at intervals; wherein an orthographic projection of each first upper electrode on the substrate at least covers a part of the orthographic projection of the first lower electrode and/or a part of the second lower electrode on the substrate. This application sets up fingerprint identification sensing capacitance's bottom electrode is crisscross in the different layers, very big increase the resolution ratio of electric capacity, and then improved fingerprint identification's precision.
Description
Technical Field
The application relates to the technical field of display, in particular to a fingerprint identification structure, a preparation method of the fingerprint identification structure, a display substrate and a display device.
Background
Fingerprint identification is a biological identification mode, and is widely applied to the fields of smart phones, safety equipment and the like. Currently, optical, capacitive and ultrasonic fingerprint identification technologies are common. As is well known, the mobile phones supporting fingerprint identification in the market are classified into three types, one is integrated on the power key at the bottom of the front side, the other is designed on the back body, and the third is designed on the frame. After the smart phone enters the full screen era, the industry generally considers that the fingerprint under the screen is the future development trend. From the technical principle of fingerprint identification, optical, capacitive, thermal and ultrasonic are four common fingerprint identification methods. On electronic devices such as mobile phones and tablet computers, capacitive modules with light volume and low cost are the first choice of most consumer electronics manufacturers.
In the prior art in the market, the capacitive ultrasonic fingerprint is placed on a mobile phone or other electronic products in a form of an independent module, and is not integrated with a display panel. When fingerprint identification is integrated in a display area of a display panel, because the aperture ratio of the display area is ensured, a capacitance sensing electrode for fingerprint identification needs to be integrated on an array substrate, when a PPI is displayed to be large, the area left for the capacitance sensing electrode is small, and the sensing precision is reduced due to the limitation of the minimum process size and the process precision. In addition, when fingerprint recognition is integrated in the non-display area of the display panel, in the case of a relatively narrow bezel, the area left for the capacitive sensor electrode is also small due to the limitation of the minimum process size and process accuracy, which results in a decrease in sensing accuracy.
Disclosure of Invention
In order to solve the problems, the application provides a fingerprint identification structure, a manufacturing method thereof, a display substrate and a display device, and solves the technical problem that in the prior art, fingerprint identification sensing precision is low due to the fact that an identification area of the fingerprint identification display substrate is small and process precision is limited.
In a first aspect, the present application provides a fingerprint identification structure, including:
a substrate;
a plurality of first lower electrodes disposed above the substrate at intervals;
a first insulating layer over the first lower electrode;
a plurality of second lower electrodes disposed above the first insulating layer at intervals;
wherein the orthographic projection of the first lower electrode on the substrate and the orthographic projection of the second lower electrode on the substrate are alternately arranged at intervals;
a second insulating layer over the second lower electrode;
a plurality of first upper electrodes disposed above the second insulating layer at intervals; wherein an orthographic projection of each first upper electrode on the substrate at least covers a part of the first lower electrode or a part of the second lower electrode on the substrate.
In some embodiments, the fingerprint identification structure further includes:
a third insulating layer over the first upper electrode;
a plurality of second upper electrodes disposed above the third insulating layer at intervals; wherein the orthographic projection of each second upper electrode on the substrate at least covers part of the orthographic projection of the first lower electrode and/or part of the orthographic projection of the second lower electrode on the substrate, and the orthographic projection of the first upper electrode on the substrate and the orthographic projection of the second upper electrode on the substrate are alternately arranged at intervals.
In some embodiments, the fingerprint identification structure further includes:
a first data signal line electrically connected to the first lower electrode;
a second data signal line electrically connected to the second lower electrode;
a third data signal line electrically connected to the first upper electrode.
In some embodiments, in the above fingerprint identification structure, the first data signal line and the second data signal line are located above the first insulating layer;
the first data signal line is electrically connected to the first lower electrode through a first connection portion filled in the first via hole.
In some embodiments, in the fingerprint identification structure, the first data signal line and the second data signal line are located above the second insulating layer;
the first data signal line is electrically connected to the first lower electrode through a first connection portion filled in the first via hole, and the second data signal line is electrically connected to the second lower electrode through a second connection portion filled in the second via hole.
In some embodiments, in the fingerprint identification structure, the first connecting portion includes at least one longitudinally stacked conductive layer.
In some embodiments, in the fingerprint identification structure, the second connection portion includes at least one longitudinally stacked conductive layer.
In some embodiments, the fingerprint identification structure further includes:
a first thin film transistor, wherein the first data signal line is electrically connected to the first thin film transistor such that the first data signal line is electrically connected to the first lower electrode through the first thin film transistor;
a second thin film transistor, wherein the second data signal line is electrically connected to the second thin film transistor such that the second data signal line is electrically connected to the second lower electrode through the second thin film transistor;
a third thin film transistor, wherein the third data signal line is electrically connected to the third thin film transistor such that the third data signal line is electrically connected to the first upper electrode through the third thin film transistor.
In a second aspect, the present application provides a method for preparing a fingerprint identification structure, including:
providing a substrate;
forming a plurality of first lower electrodes spaced above the substrate;
forming a first insulating layer over the first lower electrode;
forming a plurality of second lower electrodes disposed at intervals over the first insulating layer; wherein the orthographic projection of the first lower electrode on the substrate and the orthographic projection of the second lower electrode on the substrate are alternately arranged at intervals;
forming a second insulating layer over the second lower electrode;
forming a plurality of first upper electrodes disposed at intervals over the second insulating layer; wherein an orthographic projection of each first upper electrode on the substrate at least covers a part of the first lower electrode or a part of the second lower electrode on the substrate.
In some embodiments, in the above method for manufacturing a fingerprint identification structure, after the step of forming a plurality of first upper electrodes spaced apart from each other over the second insulating layer, the method further includes:
forming a third insulating layer over the first upper electrode;
forming a plurality of second upper electrodes disposed at intervals over the third insulating layer; wherein the orthographic projection of each second upper electrode on the substrate at least covers part of the orthographic projection of the first lower electrode and/or part of the orthographic projection of the second lower electrode on the substrate, and the orthographic projection of the first upper electrode on the substrate and the orthographic projection of the second upper electrode on the substrate are alternately arranged at intervals.
In a third aspect, the present application provides a display substrate comprising the fingerprint identification structure according to any one of the first aspect or the fingerprint identification structure prepared by the preparation method according to any one of the second aspect.
In some embodiments, in the display substrate, the fingerprint identification structure is located in a display area of the display substrate.
In some embodiments, in the display substrate, the fingerprint identification structure is located outside the display area of the display substrate.
In a fourth aspect, the present application provides a display device comprising the display substrate according to any one of the third aspect.
By adopting the technical scheme, the following technical effects can be at least achieved:
the application provides a fingerprint identification structure and a preparation method thereof, a display substrate and a display device, wherein the fingerprint identification structure comprises: a substrate; a plurality of first lower electrodes disposed above the substrate at intervals; a first insulating layer over the first lower electrode; a plurality of second lower electrodes disposed above the first insulating layer at intervals; wherein the orthographic projection of the first lower electrode on the substrate and the orthographic projection of the second lower electrode on the substrate are alternately arranged at intervals; a second insulating layer over the second lower electrode; a plurality of first upper electrodes disposed above the second insulating layer at intervals; wherein an orthographic projection of each first upper electrode on the substrate at least covers a part of the orthographic projection of the first lower electrode and/or a part of the second lower electrode on the substrate. This application sets up fingerprint identification sensing capacitance's bottom electrode is crisscross in the different layers, can pass through piling up of electric capacity electrode, very big increase the resolution ratio of electric capacity, and then improved fingerprint identification's precision.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application and not to limit the application. In the drawings:
FIG. 1 is a schematic cross-sectional view of a fingerprint identification structure;
FIG. 2 is a schematic cross-sectional view of a fingerprint identification structure according to an exemplary embodiment of the present application;
FIG. 3 is a cross-sectional schematic view of another fingerprint identification structure shown in an exemplary embodiment of the present application;
FIG. 4 is a schematic cross-sectional view of another fingerprint identification structure according to an exemplary embodiment of the present application;
FIG. 5 is a schematic circuit diagram illustrating a fingerprint identification structure according to an exemplary embodiment of the present application;
FIG. 6 is a cross-sectional schematic view of another fingerprint identification structure shown in an exemplary embodiment of the present application;
FIG. 7 is a cross-sectional schematic view of another fingerprint identification structure shown in an exemplary embodiment of the present application;
FIG. 8 is a cross-sectional schematic view of another fingerprint identification structure shown in an exemplary embodiment of the present application;
FIG. 9 is another cross-sectional schematic view of another fingerprint identification structure shown in an exemplary embodiment of the present application;
FIG. 10 is a cross-sectional schematic view of another fingerprint identification structure shown in an exemplary embodiment of the present application;
FIG. 11 is a schematic diagram of another cross-sectional structure of another fingerprint identification structure shown in an exemplary embodiment of the present application;
FIG. 12 is a cross-sectional schematic view of another fingerprint identification structure shown in an exemplary embodiment of the present application;
FIG. 13 is a cross-sectional schematic view of another fingerprint identification structure shown in an exemplary embodiment of the present application;
FIG. 14 is another cross-sectional schematic view of another fingerprint identification structure shown in an exemplary embodiment of the present application;
FIG. 15 is a cross-sectional schematic view of another fingerprint identification structure shown in an exemplary embodiment of the present application;
FIG. 16 is another cross-sectional schematic view of another fingerprint identification structure shown in an exemplary embodiment of the present application;
FIG. 17 is a flow chart illustrating a method for fabricating a fingerprint identification structure according to an exemplary embodiment of the present application;
FIG. 18 is a cross-sectional structural view of a first intermediate structure formed in accordance with a related step of a method for making a fingerprint identification structure according to an exemplary embodiment of the present application;
FIG. 19 is a cross-sectional structural view of a second intermediate structure formed in accordance with a related step of a method for making a fingerprint identification structure according to an exemplary embodiment of the present application;
FIG. 20 is a cross-sectional view of a third intermediate structure formed in accordance with a related step of a method for making a fingerprint identification structure according to an exemplary embodiment of the present application;
FIG. 21 is a cross-sectional view of a fourth intermediate structure formed in accordance with a related step of a method for making a fingerprint identification structure according to an exemplary embodiment of the present application;
FIG. 22 is a cross-sectional view of a fifth intermediate structure formed in accordance with a related step of a method for making a fingerprint identification structure according to an exemplary embodiment of the present application;
FIG. 23 is a schematic cross-sectional view of a fifth intermediate structure formed in accordance with a related step of a method for fabricating a fingerprint identification structure according to an exemplary embodiment of the present application;
in the drawings, wherein like parts are designated with like reference numerals, the drawings are not necessarily to scale;
the reference signs are:
101-a substrate; 102-a buffer layer; 103-a semiconductor layer; 104-a first gate insulation layer; 105-a first gate; 106-a second gate insulation layer; 107-interlayer insulating layer; 109-source drain metal layer; 111-a lower electrode; 112-a capacitor insulating layer; 113-a first upper electrode;
201-a substrate; 202-a buffer layer; 203-a semiconductor layer; 204 — first gate insulation layer; 205-a first gate; 206-a second gate insulation layer; 207-interlayer insulating layer; 208-a fourth via; 209-source drain metal layer; 210-a planar layer; 211-a first lower electrode; 212 — a first insulating layer; 213-a second lower electrode; 214-a second insulating layer; 2141A portion of the second insulating layer corresponding to the insulating layer of the interlayer insulating layer; 2142 the second insulating layer corresponds to the insulating layer portion of the planarization layer; 215-a first upper electrode; 216 — a first via; 217-second via holes; 218-a first connection; 219 — a second connecting portion; 220-first data signal line; 221-a first thin film transistor; 222-a third thin film transistor; 223-third data signal lines; 224-a third insulating layer; 225-second upper electrode;
301-a substrate; 302-a buffer layer; 303-a semiconductor layer; 304-a first gate insulation layer; 305-a first gate; 306-a second gate insulation layer; 307-interlayer insulating layer; 308-a fourth via; 309-a first source drain metal layer; 310-a first planar layer; 311-a fifth via; 312-a second source drain metal layer; 313-a second planar layer; 321-a first lower electrode; 322-a first insulating layer; 323-second lower electrode; 324-a second insulating layer; 3241 — the second insulating layer corresponds to the insulating layer portion of the interlayer insulating layer; 3242-the second insulating layer corresponds to the insulating layer portion of the first flat layer; 325 — a first upper electrode; 326-a planarization layer; 327-a third via; 328-a third connecting portion; 329 — a first portion of a first via; 330 — a first portion of a second via; 331-portion SD1 of the first connection; 332-the SD1 portion of the second connection; 333-a second portion of the first via; 334-a second portion of a second via; 335-SD 2 part of first connection; 336-portion SD2 of the second connection.
Detailed Description
The following detailed description will be provided with reference to the accompanying drawings and embodiments, so that how to apply the technical means to solve the technical problems and achieve the corresponding technical effects can be fully understood and implemented. The embodiments and various features in the embodiments of the present application can be combined with each other without conflict, and the formed technical solutions are all within the scope of protection of the present application. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
It will be understood that spatial relationship terms, such as "above", "below", "beneath", and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" other elements would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the present application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing.
In order to provide a thorough understanding of the present application, detailed structures and steps will be provided in the following description in order to explain the technical solutions proposed in the present application. The following detailed description of the preferred embodiments of the present application, however, will suggest that the present application may have other embodiments in addition to these detailed descriptions.
As shown in fig. 1, the fingerprint recognition structure includes: the substrate 101, the buffer layer 102, the lower electrode 111, the capacitor insulating layer 112, and the upper electrode 113 are sequentially stacked.
In addition, the fingerprint identification structure further includes a thin film transistor structure, which includes a semiconductor layer 103, a first Gate insulating layer 104(GI1), a first Gate 105(Gate1), a second Gate insulating layer 106(GI2), an interlayer insulating layer 107(ILD), and a source/drain metal layer 109(SD) stacked in this order above the buffer layer 102.
The source-drain metal layer 109 is filled in the via hole 108 to electrically connect with the semiconductor layer 103. The lower electrode 111 of the fingerprint identification capacitive sensor and the second Gate (Gate2, not shown in the figure) of the display substrate are arranged on the same layer, i.e. are prepared synchronously, and the upper electrode 113 and the source drain metal layer 109 are arranged on the same layer, i.e. are prepared synchronously. However, since the lower electrodes 111 are disposed on the same layer as the second gate electrode (not shown) of the display region, the sensing accuracy is reduced due to the limitation of the minimum process size and the process accuracy when the area reserved for the capacitive sensor electrode is small. The minimum pitch of the single metal layer is limited, i.e. if only the second Gate (Gate2) is used as the capacitor plate, the effective resolution accuracy is limited by the minimum process size and process accuracy.
The embodiment of the application provides a fingerprint identification structure. Referring to fig. 2, the fingerprint identification structure includes: the organic light emitting diode includes a substrate 201, a buffer layer 202, a first lower electrode 211, a first insulating layer 212, a second lower electrode 213, a second insulating layer 214, and a first upper electrode 215, which are sequentially stacked.
The plurality of first lower electrodes 211 are disposed above the substrate 201 and the buffer layer 202 at intervals.
The first insulating layer 212 is located over the first lower electrode 211.
A plurality of second lower electrodes 213 are disposed above the first insulating layer 212 at intervals, and an orthographic projection of the first lower electrodes 211 on the substrate 201 is alternately disposed at intervals with an orthographic projection of the second lower electrodes 213 on the substrate 201.
The second insulating layer 214 is positioned over the second lower electrode 213.
A plurality of first upper electrodes 215 are disposed at intervals above the second insulating layer 214, wherein an orthographic projection of each first upper electrode 215 on the substrate 201 at least partially covers the orthographic projection of the first lower electrode 211 and/or the partial second lower electrode 213 on the substrate 201.
That is to say, the first lower electrode 211 and the second lower electrode 213 of the fingerprint sensing capacitor are arranged in two layers, the first lower electrode 211 and the second lower electrode 213 are simultaneously used as the lower electrodes of the capacitor, and the first lower electrode 211 and the second lower electrode 213 are alternately arranged at intervals, so that the minimum process size and the process precision of a single-layer metal are not limited, dense interval arrangement is formed, the distance between adjacent capacitor plates can be greatly shortened, the number of the capacitor plates which can be arranged in a unit area can be increased to more than 20% of the original number, and can be about 50% at most, thereby improving the resolution ratio, and further improving the precision of fingerprint identification.
Since the film thickness of the first insulating layer 212 is uniform at each position (not shown in the figure), the first insulating layer 212 protrudes (not shown in the figure) at the position of the first lower electrode 211, the first insulating layer 212 has a certain recess (not shown in the figure) between two adjacent first lower electrodes 211 (at the position of the gap), the second lower electrode 213 is arranged at the recess, and the finally formed first lower electrode 211 and the second lower electrode 213 are substantially (approximately) in the same layer and are used as the same layer of electrode, and the fingerprint identification resolution can be improved by about 50% -75% by arranging the first lower electrode 211 and the second lower electrode 213 at intervals.
In some embodiments, a first upper electrode 215 corresponds to a first lower electrode 211 or a second lower electrode 213, forming a fingerprint sensing capacitor.
As shown in fig. 3, in some embodiments, one first upper electrode 215 may also correspond to a plurality of first lower electrodes 211 and second lower electrodes 213, forming a plurality of fingerprint sensing capacitors.
As shown in fig. 4 and 5, in some embodiments, the fingerprint identification structure further includes a first data signal line 220 electrically connected to the first lower electrode 211, a second data signal line (not labeled) electrically connected to the second lower electrode 213, and a third data signal line 223 electrically connected to the first upper electrode 215. The first data signal line 220 and the second data signal line are located in the same layer, and are located above the first insulating layer 212 or the second insulating layer 214. The third data signal line 223 is positioned at the same layer as the first upper electrode 215 or above the first upper electrode 215.
In some embodiments, when the first data signal line 220 and the second data signal line are located over the second insulating layer 214, the first data signal line 220 is electrically connected to the first lower electrode 211 through the first connection portion 218 filled in the first via hole 216, and the second data signal line is electrically connected to the second lower electrode 213 through the second connection portion 219 filled in the second via hole 217. The first via hole 216 penetrates through the first insulating layer 212 and the second insulating layer 214, and the second via hole 217 penetrates through the second insulating layer 214.
In some embodiments, when the third data signal line 223 is located above the first upper electrode 215, the third data signal line 223 is electrically connected to the first upper electrode 215 through a third connection portion (not shown) filled in a third via hole (not shown).
In some embodiments, as shown in fig. 5, the fingerprint identification structure further comprises: a first thin film transistor 221 and a second thin film transistor (not labeled). The first data signal line 220 is electrically connected to the first thin film transistor 221, such that the first data signal line 220 is electrically connected to the first lower electrode 211 through the first thin film transistor 221; the second data signal line is electrically connected to the second thin film transistor such that the second data signal line is electrically connected to the second lower electrode 213 through the second thin film transistor.
The first data signal line 220 includes a data signal line connected to a gate electrode of the first thin film transistor 221 and a data signal line connected to a source electrode (or drain electrode) of the first thin film transistor 221, and correspondingly, the drain electrode (or source electrode) of the first thin film transistor 221 is connected to the first lower electrode 211.
Similarly, the second data signal line includes a data signal line connected to the gate of the second thin film transistor and a data signal line connected to the source (or drain) of the second thin film transistor, and correspondingly, the drain (or source) of the second thin film transistor is connected to the second lower electrode 213.
In some embodiments, the fingerprint identification structure further comprises: and a third thin film transistor 222, wherein a third data signal line 223 is electrically connected to the first upper electrode 215 through the third thin film transistor 222.
The third data signal line 223 includes a data signal line connected to the gate of the third thin film transistor 222 and a data signal line connected to the source (or drain) of the third thin film transistor 222, and correspondingly, the drain (or source) of the third thin film transistor 222 is connected to the first upper electrode 215.
The first data signal line 220, the second data signal line and the third data signal line 223 are used for collecting fingerprint signals of a user, and a fingerprint identification function is achieved.
The first thin film transistor 221, the second thin film transistor, and the third thin film transistor 222 are used to reset the corresponding fingerprint identification capacitor.
The first thin film transistor 221, the second thin film transistor, and the third thin film transistor 222 have the same structure, and a (TFT structure) thereof includes: a semiconductor layer 203, a first Gate insulating layer 204(GI1), a first Gate 205(Gate1), a second Gate insulating layer 206(GI2), an interlayer insulating layer 207(ILD), and a source/drain metal layer 209(SD) are sequentially stacked over the buffer layer 202. Each TFT structure is a single-layer SD structure, and the source/drain metal layer 209 is filled in the fourth via hole 208 to be electrically connected to the semiconductor layer 203.
In some embodiments, the first bottom electrode 211 and the first Gate 205 are disposed on the same layer (same as Gate1), the first insulating layer 212 and the second Gate insulating layer 206 are disposed on the same layer (same as GI2), the second bottom electrode 213 and the second Gate (not shown) of the display substrate are disposed on the same layer (same as Gate2), the second insulating layer 214 and the interlayer insulating layer 207 are disposed on the same layer (same as ILD), and the first top electrode 215 and the source/drain metal layer 209 are disposed on the same layer (same as SD). The first, second, and third data signal lines 220, 223 are disposed at the same layer (also SD layer) as the first upper electrode 215 (i.e., the source-drain metal layer 209), the first via hole 216 penetrates the first and second insulating layers 212 and 214, and the second via hole 217 penetrates the second insulating layer 214.
The sensing capacitor of the fingerprint identification structure is synchronously prepared with each TFT, so that the process flow can be simplified, the number of masks is reduced, and the cost is reduced.
Correspondingly, the conductive layers of the first connection portion 218 in the first via hole 216 and the second connection portion 218 in the second via hole 217 are both the source drain metal layers 209.
As shown in fig. 6, in some embodiments, the TFT structure further includes a planarization layer 210.
Correspondingly, in addition to the first upper electrode 215 being disposed on the same layer as the source/drain metal layer 209 (also referred to as the SD layer), in some embodiments, the first upper electrode 215 may also be disposed on the same layer as the Anode layer of the display substrate (also referred to as the Anode layer). Correspondingly, the second insulating layer 214 includes an insulating layer portion 2141 corresponding to the interlayer insulating layer 207 and an insulating layer portion 2142 corresponding to the planarization layer 210.
As shown in fig. 7, in some embodiments, the fingerprint identification structure further includes a third insulating layer 224 and a second upper electrode 225.
The third insulating layer 224 is positioned over the first upper electrode 215.
A plurality of second upper electrodes 225 are spaced above the third insulating layer 224, wherein an orthographic projection of each second upper electrode 225 on the substrate at least covers a part of the first lower electrode 211 and/or a part of the second lower electrode 224 on the substrate 201, and the orthographic projections of the first upper electrodes 215 on the substrate 201 are alternately and spaced from the orthographic projections of the second upper electrodes 225 on the substrate 201.
In some embodiments, the first bottom electrode 211 and the first Gate 205 are disposed on the same layer (same Gate1 layer), the first insulating layer 212 and the second Gate insulating layer 206 are disposed on the same layer (same GI2 layer), the second bottom electrode 213 and the second Gate (not shown) of the display substrate are disposed on the same layer (same Gate2 layer), the second insulating layer 214 and the interlayer insulating layer 207 are disposed on the same layer (same ILD layer), the first top electrode 215 and the source/drain metal layer 209 are disposed on the same layer (same SD layer), the third insulating layer 224 and the planarization layer 210 are disposed on the same layer (same PLN layer), and the second top electrode 225 and the Anode layer of the display substrate are disposed on the same layer (same Anode layer).
That is, in addition to the lower electrodes (the first lower electrode 211 and the second lower electrode 213) being located at different layers, the upper electrodes (the first upper electrode 215 and the second upper electrode 225) of the fingerprint sensing capacitor may also be located at different layers. The upper electrode plate and the lower electrode plate are not limited by the minimum process size and the process precision of single-layer metal any more, the distance between adjacent capacitor plates can be further shortened, the number of the capacitor plates which can be arranged in unit area can be further increased, the resolution ratio is further improved, and the fingerprint identification precision is further improved.
Corresponding to the second upper electrode 225, the fingerprint identification structure further includes a fourth data signal line (not shown) electrically connected to the second upper electrode 225 for signal transmission.
In some embodiments, corresponding to the second upper electrode 225 and the fourth data signal line, the fingerprint recognition structure further includes: and a fourth thin film transistor (not shown), wherein the fourth data signal line is electrically connected to the second upper electrode 225 through the fourth thin film transistor.
As shown in fig. 8 and 9, in the case that the first upper electrode 215 is disposed at the same layer as the anode layer of the display substrate, in some embodiments, the first lower electrode 211 may also be disposed at the same layer (also, Gate2 layer) as the second Gate electrode (not shown) of the display substrate. Correspondingly, the first insulating layer 212 and the interlayer insulating layer 207 are disposed on the same layer (also referred to as an ILD layer), and the second bottom electrode 213 and the source/drain metal layer 209 are disposed on the same layer (also referred to as an SD layer). The first data signal line 220, the second data signal line and the second lower electrode 213 (i.e., the source-drain metal layer 209) are disposed on the same layer (i.e., the first data signal line 220 and the second data signal line are both located above the first insulating layer 212 and are also an SD layer), and the first via hole 216 penetrates through the first insulating layer 212 without disposing the second via hole 217.
In some embodiments, the first lower electrode 211 may be disposed on the same layer (also LS layer) as the light shielding layer (LS layer, disposed below the semiconductor layer 203, not shown) of the TFT structure.
As shown in fig. 10, in some embodiments, a TFT structure includes: a semiconductor layer 303, a first Gate insulating layer 304(GI1), a first Gate 305(Gate1), a second Gate insulating layer 306(GI2), an interlayer insulating layer 307(ILD), a first source/drain metal layer 309(SD1), a first planarization layer 310(PLN1), and a second source/drain metal layer 312(SD2) which are stacked in this order over the substrate 301 and the buffer layer 302. That is, each TFT structure is a double-layer SD structure, the first source/drain metal layer 309 is filled in the fourth via hole 308 to be electrically connected to the semiconductor layer 303, and the second source/drain metal layer 312 is filled in the fifth via hole 311 to be electrically connected to the first source/drain metal layer 309.
Correspondingly, the first lower electrode 321, the second lower electrode 323, and the first upper electrode 325 may be any combination of a Gate1 layer, a Gate2 layer, an SD1 layer, an SD2 layer, and an Anode layer, on the basis that the first lower electrode 321 and the second lower electrode 323 are located at different layers.
In some embodiments, in the case where the fingerprint recognition structure includes the second upper electrode, the first lower electrode 321, the second lower electrode 323, the first upper electrode 325, and the second upper electrode may be any combination of a Gate1 layer, a Gate2 layer, an SD1 layer, an SD2 layer, and an Anode layer.
As shown in fig. 10 and 11, in some embodiments, the first lower electrode 321 and the first Gate 305 are disposed on the same layer (same as a Gate1 layer), the first insulating layer 322 and the second Gate insulating layer 306 are disposed on the same layer (same as a GI2 layer), the second lower electrode 323 and the second Gate (not shown) of the display substrate are disposed on the same layer (same as a Gate2 layer), the second insulating layer 324 and the interlayer insulating layer 307 are disposed on the same layer (same as an ILD layer), and the first upper electrode 325 and the first source/drain metal layer 309 are disposed on the same layer (same as an SD1 layer). The first, second, and third data signal lines 328 may be disposed at the same layer (the same layer as the SD2 layer) as the second source-drain metal layer 312.
Correspondingly, the fingerprint identification structure further includes a flat layer 326.
Correspondingly, the first data signal line is electrically connected to the first lower electrode 321 through a first connection portion (including the SD1 portion 331 and the SD2 portion 335) within a first via hole (including the first portion 329 extending through the first and second insulating layers 322 and 324 and the second portion 333 extending through the planarization layer 326), and the second data signal line is electrically connected to the second lower electrode 323 through a second connection portion (including the SD1 portion 332 and the SD2 portion 336) within a second via hole (including the first portion 330 extending through the second insulating layer 324 and the second portion 334 extending through the planarization layer 326). The third data signal line (SD2) is electrically connected to the first upper electrode 325 through a third connection 328 in the third via 327 (penetrating the planarization layer 326).
As shown in fig. 12, in some embodiments, the first upper electrode 325 may be disposed at the same layer (the same layer as SD2) as the second source/drain metal layer 312. At this time, the second insulating layer 324 includes an insulating layer portion 3241 corresponding to an interlayer insulating layer and an insulating layer portion 3242 of the first flat layer.
As shown in fig. 13, in some embodiments, when the first upper electrode 325 is an SD2 layer, the first lower electrode 321 may also be a Gate2 layer, and correspondingly, the second lower electrode 323 is an SD1 layer.
Correspondingly, as shown in fig. 14, the first data signal line is electrically connected to the first lower electrode 321 through a first connection portion (including the SD1 portion 331 and the SD2 portion 335) in a first via (including the first portion 329 penetrating the first insulating layer 322 and the second portion 333 penetrating the second insulating layer 324), and the second data signal line is electrically connected to the second lower electrode 323 through a second connection portion (the SD2 portion 336) in a second via (penetrating the second portion 334 of the second insulating layer 324).
As shown in fig. 15, in some embodiments, the TFT structure (dual layer SD) further includes a second planarization layer 313(PLN2 layer).
In some embodiments, in addition to the first upper electrode 325 being disposed on the same layer (the same layer as the SD1 layer or the SD2 layer) as the first source/drain metal layer 309 or the second source/drain metal layer 312, in some embodiments, the first upper electrode 325 may be disposed on the same layer (the same layer as the Anode layer) as an Anode layer (not shown) of the display substrate.
In some embodiments, when the first upper electrode 325 is an Anode layer, the first lower electrode 321 may also be an SD1 layer, correspondingly, the second lower electrode 323 is an SD2 layer, the first insulating layer 322 and the first planarization layer 310 are disposed on the same layer (also PLN1 layer), correspondingly, the second insulating layer 324 corresponds to the second planarization layer (also PLN2 layer).
As shown in fig. 16, correspondingly, the first data signal line (SD2) is electrically connected to the first lower electrode 321 through the first via (the second portion 333 penetrating the planarization layer 326), in which case the second via need not be provided.
In some embodiments, the first lower electrode 321 may be disposed on the same layer (also LS layer) as the light shielding layer (LS layer, disposed below the semiconductor layer 303, not shown) of the TFT structure.
The embodiment of the application also provides a preparation method of the fingerprint identification structure, and the following patterning comprises the processes of coating photoresist, mask exposure, developing, etching, stripping the photoresist and the like. The "deposition" may be selected from any one or more of sputtering, evaporation and chemical vapor deposition, and the etching may be performed using any one or more selected from dry etching and wet etching.
Referring to fig. 17, a method for manufacturing a fingerprint identification structure (such as the fingerprint identification structure shown in fig. 2) provided in the embodiment of the present application includes the following steps:
step S110: a substrate 201 is provided.
The substrate 201 may be a flexible substrate 201 or may be a rigid (glass) substrate 201.
The flexible substrate 201 is an organic film layer, and includes at least one of polyimide, negative glue, or positive glue.
In some embodiments, the buffer layer 202 may be formed first over the substrate 201.
In some embodiments, the sensing capacitor and the TFT structure in the fingerprint identification structure are formed synchronously, so that the process flow can be simplified, the number of masks is reduced, and the cost is reduced.
Correspondingly, after the buffer layer 202 is formed, a semiconductor layer 203 (including deposition and patterning) and a first gate insulating layer 204 (including deposition and patterning) are sequentially formed over the buffer layer 202.
Step S120: as shown in fig. 18, a plurality of first lower electrodes 211 are formed over a substrate 201 at intervals.
In some embodiments, a metal layer is deposited on the first insulating layer 212, and then a patterning process is performed to obtain a plurality of spaced first lower electrodes 211 and the first gate electrode 205 of the TFT structure.
Step S130: a first insulating layer 212 is formed over the first lower electrode 211.
In some embodiments, the second gate insulating layer 206 of the TFT structure is also formed simultaneously with the formation of the first insulating layer 212.
Step S140: as shown in fig. 19, a plurality of second lower electrodes 213 disposed at intervals are formed over the first insulating layer 212; wherein, the orthographic projection of the first lower electrode 211 on the substrate 201 and the orthographic projection of the second lower electrode 213 on the substrate 201 are alternately arranged at intervals.
In some embodiments, the second gate electrode of the display substrate is also simultaneously formed while the second lower electrode 213 is formed.
Step S150: as shown in fig. 20, a second insulating layer 214 is formed over the second lower electrode 213.
In some embodiments, the interlayer insulating layer 207 of the TFT structure is also simultaneously formed while the second insulating layer 214 is formed.
As shown in fig. 21, after step S150, the method further includes: a first via hole 216 penetrating the second insulating layer 214 and the first insulating layer 212 is formed over the first lower electrode 211, a second via hole 217 penetrating the second insulating layer 214 is formed over the second lower electrode 213, and a fourth via hole 208 penetrating the interlayer insulating layer 207, the second gate insulating layer 206, and the first gate insulating layer 204 is formed at the TFT position.
Step S160: as shown in fig. 22 and 23, a plurality of first upper electrodes 215 are formed over the second insulating layer 214, disposed at intervals; wherein, the orthographic projection of each first upper electrode 215 on the substrate 201 at least covers a part of the orthographic projection of the first lower electrode 211 or a part of the second lower electrode 213 on the substrate 201.
In some embodiments, the first upper electrode 215 and the source/drain metal layer 209 are disposed in the same layer (SD layer), and at the same time of forming the first upper electrode 215, a source/drain metal layer of the TFT structure is also formed (filled in the fourth via 208 to be electrically connected to the semiconductor layer 203), and a first data signal line 220 (electrically connected to the first lower electrode 211 through the first connection portion 218 in the first via 216), a second data signal line (electrically connected to the second lower electrode 213 through the second connection portion 219 in the second via 217), and a third data signal line 223 are also formed.
In some embodiments, after step S160, the method further includes:
step S170: a third insulating layer 224 is formed over the first upper electrode 215.
Step S180: forming a plurality of second upper electrodes 225 disposed at intervals over the third insulating layer 224; wherein, the orthographic projection of each second upper electrode 225 on the substrate 201 at least covers part of the orthographic projection of the first lower electrode 211 and/or part of the second lower electrode 213 on the substrate 201, and the orthographic projection of the first upper electrode 215 on the substrate 201 is alternately and alternately arranged with the orthographic projection of the second upper electrode 225 on the substrate 201.
Correspondingly, the prepared fingerprint identification structure is shown in fig. 7.
The embodiment of the application also provides a display substrate, wherein the display substrate comprises the fingerprint identification structure of any one of the embodiments or the fingerprint identification structure prepared by the preparation method of any one of the embodiments.
In some embodiments, the fingerprint identification structure may be located within a display area of a display substrate, i.e., the display substrate employs an off-screen fingerprint technology.
In some embodiments, the fingerprint identification structure may be located outside the display area of the display substrate.
The embodiment of the application also provides a display device, which comprises the display substrate in any one of the embodiments.
In some embodiments, the display device is a display panel, and the display panel includes the display substrate and the glass cover plate.
In some embodiments, the display device may include a display panel and a housing, the display panel being connected with the housing, e.g., the display panel being embedded in the housing. The display device can be any device with a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator and the like.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application. Although the embodiments disclosed in the present application are described above, the embodiments are merely used for the understanding of the present application, and are not intended to limit the present application. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims.
Claims (14)
1. A fingerprint identification structure, comprising:
a substrate;
a plurality of first lower electrodes disposed above the substrate at intervals;
a first insulating layer over the first lower electrode;
a plurality of second lower electrodes disposed above the first insulating layer at intervals; wherein the orthographic projection of the first lower electrode on the substrate and the orthographic projection of the second lower electrode on the substrate are alternately arranged at intervals;
a second insulating layer over the second lower electrode;
a plurality of first upper electrodes disposed above the second insulating layer at intervals; wherein an orthographic projection of each first upper electrode on the substrate at least covers a part of the orthographic projection of the first lower electrode and/or a part of the second lower electrode on the substrate.
2. The fingerprint recognition structure of claim 1, further comprising:
a third insulating layer over the first upper electrode;
a plurality of second upper electrodes disposed above the third insulating layer at intervals; wherein the orthographic projection of each second upper electrode on the substrate at least covers part of the orthographic projection of the first lower electrode and/or part of the orthographic projection of the second lower electrode on the substrate, and the orthographic projection of the first upper electrode on the substrate and the orthographic projection of the second upper electrode on the substrate are alternately arranged at intervals.
3. The fingerprint recognition structure of claim 1, further comprising:
a first data signal line electrically connected to the first lower electrode;
a second data signal line electrically connected to the second lower electrode;
a third data signal line electrically connected to the first upper electrode.
4. The fingerprint identification structure of claim 3, wherein the first and second data signal lines are located over the first insulating layer;
the first data signal line is electrically connected to the first lower electrode through a first connection portion filled in the first via hole.
5. The fingerprint identification structure of claim 3, wherein the first data signal line and the second data signal line are located over the second insulating layer;
the first data signal line is electrically connected to the first lower electrode through a first connection portion filled in the first via hole, and the second data signal line is electrically connected to the second lower electrode through a second connection portion filled in the second via hole.
6. The fingerprint identification structure of claim 4 or 5, wherein the first connection portion comprises at least one longitudinally stacked conductive layer.
7. The fingerprint identification structure of claim 5, wherein the second connection portion comprises at least one longitudinally stacked conductive layer.
8. The fingerprint recognition structure of claim 3, further comprising:
a first thin film transistor, wherein the first data signal line is electrically connected to the first thin film transistor such that the first data signal line is electrically connected to the first lower electrode through the first thin film transistor;
a second thin film transistor, wherein the second data signal line is electrically connected to the second thin film transistor such that the second data signal line is electrically connected to the second lower electrode through the second thin film transistor;
a third thin film transistor, wherein the third data signal line is electrically connected to the third thin film transistor such that the third data signal line is electrically connected to the first upper electrode through the third thin film transistor.
9. A method for preparing a fingerprint identification structure is characterized by comprising the following steps:
providing a substrate;
forming a plurality of first lower electrodes spaced above the substrate;
forming a first insulating layer over the first lower electrode;
forming a plurality of second lower electrodes disposed at intervals over the first insulating layer; wherein the orthographic projection of the first lower electrode on the substrate and the orthographic projection of the second lower electrode on the substrate are alternately arranged at intervals;
forming a second insulating layer over the second lower electrode;
forming a plurality of first upper electrodes disposed at intervals over the second insulating layer; wherein an orthographic projection of each first upper electrode on the substrate at least covers a part of the orthographic projection of the first lower electrode and/or a part of the second lower electrode on the substrate.
10. The method for manufacturing according to claim 9, wherein after the step of forming a plurality of first upper electrodes arranged at intervals over the second insulating layer, the method further comprises:
forming a third insulating layer over the first upper electrode;
forming a plurality of second upper electrodes disposed at intervals over the third insulating layer; wherein the orthographic projection of each second upper electrode on the substrate at least covers part of the orthographic projection of the first lower electrode and/or part of the orthographic projection of the second lower electrode on the substrate, and the orthographic projection of the first upper electrode on the substrate and the orthographic projection of the second upper electrode on the substrate are alternately arranged at intervals.
11. A display substrate comprising the fingerprint identification structure according to any one of claims 1 to 8 or the fingerprint identification structure prepared by the preparation method according to any one of claims 9 to 10.
12. The display substrate of claim 11, wherein the fingerprint identification structure is located in a display area of the display substrate.
13. The display substrate of claim 11, wherein the fingerprint identification structure is located outside a display area of the display substrate.
14. A display device comprising the display substrate according to any one of claims 11 to 13.
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