CN113065298B - Method and system for converting super-large-scale netlist into DAG (direct current) diagram - Google Patents
Method and system for converting super-large-scale netlist into DAG (direct current) diagram Download PDFInfo
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Abstract
The invention discloses a method for converting a super-large-scale netlist into a DAG (direct current) graph, which comprises the following steps of: the method comprises the steps of obtaining a netlist, extracting circuit units and connection information thereof from the netlist to generate a graph, storing the graph with an incoming edge adjacency list and an outgoing edge adjacency list, preprocessing the graph to obtain a preprocessed graph, detecting all strongly connected components in the preprocessed graph, identifying a plurality of rings according to all strongly connected components, extracting node serial numbers in each ring and serial numbers of edges, connected with each node, in the ring in the incoming edge adjacency list and the outgoing edge adjacency list, cutting incoming edges, meeting preset conditions, in the ring according to the serial numbers of the nodes and the edges in the incoming edge adjacency list in each ring to obtain a plurality of unidirectionally connected subgraphs, and associating the plurality of unidirectionally connected graphs by using virtual nodes to obtain a target DAG graph. The invention can overcome the technical problem of poor applicability of the existing method for designing and analyzing the circuit unit.
Description
Technical Field
The invention belongs to the technical field of design and analysis of very large scale integrated circuits, and particularly relates to a method and a system for converting a very large scale netlist into a DAG (direct current) graph.
Background
In designing and analyzing a very large scale integrated circuit, the design is usually performed for circuit units. The existing method for designing and analyzing circuit units generally abstracts the information of the circuit units into a netlist, converts the obtained netlist into a diagram, then performs a series of design and analysis on the converted diagram, and finally maps the result back to the original integrated circuit.
However, the existing method for designing and analyzing the circuit unit usually requires that the input graph cannot contain a ring (i.e. a strongly connected component with a node number greater than 1). However, in practice, a netlist abstracted from circuit unit information often has a ring, and a graph obtained by conversion also includes a ring, which may cause that the existing methods cannot be applied in many scenes, thereby reducing the applicability of the methods.
Disclosure of Invention
In view of the above defects or improvement requirements of the prior art, the present invention provides a method and a system for converting a very large-scale netlist into a DAG diagram, which aims to convert netlist information into a form of a DAG diagram in a short time, and overcome the technical problems that the existing method for designing and analyzing circuit units cannot be applied in many scenes, and further the applicability of the methods is reduced.
To achieve the above object, according to one aspect of the present invention, there is provided a method for converting a very large netlist into a DAG graph, comprising the steps of:
(1) obtaining a netlist, extracting circuit units and connection information thereof from the netlist to generate a graph, and storing the graph by using an incoming side adjacency list and an outgoing side adjacency list;
(2) preprocessing the graph obtained in the step (1) to obtain a preprocessed graph;
(3) detecting all the strongly connected components in the graph preprocessed in the step (2), identifying a plurality of rings according to all the strongly connected components, and extracting the node serial number in each ring and the serial numbers of the edges connected with each node in the ring in an edge-entering adjacency list and an edge-exiting adjacency list;
(4) cutting the incoming edges meeting the preset conditions in the ring according to the sequence numbers of the nodes and the edges in the incoming edge adjacency list in each ring obtained in the step (3) to obtain a plurality of unidirectionally communicated subgraphs;
(5) and (4) associating the plurality of unidirectional connected graphs obtained in the step (4) by using the virtual nodes, so as to obtain a target DAG graph.
Preferably, the step (1) is to firstly obtain the netlist, convert the circuit units and the connection information thereof in the netlist into a form of a graph, omit the input and output connection between the external and circuit modules, and record the circuit units and the connection information between the internal and external circuit units in the netlist;
in the conversion process, a circuit unit is abstracted into a node, a type identifier is used for representing the type of the circuit unit mapped by the node, parameters such as the area or the capacity of the circuit unit are abstracted into point weights, communication time among the circuit units is abstracted into edge weights, and then topology information of a graph is stored by using an edge-entering adjacency list and an edge-exiting adjacency list respectively.
Preferably, the entry of each node in the edge adjacency list includes the sequence number of the node in the graph, the sequence numbers of all edges pointing to the node, the weight of each edge (i.e., edge weight), the sequence number of another node corresponding to the edge, and a pointer pointing to the node corresponding to the another node;
the entry of each node in the outgoing edge adjacency list comprises the serial number of the node, the serial numbers of all edges pointed by the node, the edge weight of each edge, the serial number of another node corresponding to the edge, and a pointer pointing to the node corresponding to the another node.
Preferably, the step (2) is specifically to sequentially access each node in the edge-entering adjacency list and the edge-exiting adjacency list in the graph obtained in the step (1), find all isolated points, delete the isolated points from the graph obtained in the step (1), reorder the sequence numbers of the remaining points, and fill up the nodes with large sequence numbers forward so that the sequence numbers of the nodes are still continuous, thereby obtaining the preprocessed graph, wherein the isolated points are nodes without edges entering and exiting.
Preferably, step (3) comprises in particular the following sub-steps:
(3-1) setting a counter i to 1;
(3-2) judging whether i is larger than the total number of the nodes in the graph preprocessed in the step (2), if so, turning to the step (3-5), otherwise, turning to the step (3-3);
(3-3) processing the graph preprocessed in the step (2) according to a depth-first search algorithm (DFS), reading in the ith node, setting the access sequence number value p of the node as i, and placing the node on the top of the stack;
(3-4) setting i ═ i +1, and returning to step (3-2);
(3-5) setting a counter j equal to 1;
(3-6) judging whether j is larger than the total number of the nodes in the graph preprocessed in the step (2), if so, turning to the step (3-9), otherwise, turning to the step (3-7);
(3-7) acquiring the jth node A from the stack obtained in the step (3-3) according to the sequence from top to bottom, acquiring the node B with the smallest access sequence number value p which can be reached by the node A through an outgoing edge according to an outgoing edge adjacency list, setting the farthest backtracking value q of the node A as the sequence number of the node B, and taking the path from the node A to the node B as the farthest backtracking path of the node A;
(3-8) setting j ═ j +1, and returning to step (3-6);
(3-9) setting a counter k equal to 1;
(3-10) judging whether k is larger than the total number of the nodes in the graph preprocessed in the step (2), if so, turning to the step (3-13), otherwise, turning to the step (3-11);
(3-11) acquiring the kth node from the stack obtained in the step (3-7) according to the sequence from top to bottom, judging whether the access sequence number value p of the node is equal to the farthest backtracking value q, if so, popping all nodes between the top of the stack and the kth node, extracting all nodes and edge sequence numbers on the farthest backtracking path of the kth node from an edge-entering adjacency list, wherein the nodes and the edges form a strongly-connected component, and turning to the step (3-12), otherwise, turning to the step (3-12);
(3-12) setting k ═ k +1, and returning to step (3-10);
(3-13) identifying the strongly connected component with the number of nodes larger than 1 in the obtained strongly connected component as a ring;
(3-14) recording nodes corresponding to the nodes in the edge-in adjacency list and the edge-out adjacency list in the graph and edges corresponding to the nodes in the edge-in adjacency list and the edge-out adjacency list in the graph aiming at the nodes and the edges in each ring identified in the step (3-13), and ending the process.
Preferably, step (4) comprises the sub-steps of:
(4-1) storing the type identifications corresponding to all circuit units in the process of converting the netlist in the step (1) into the diagram into a register list;
(4-2) setting a counter m to 1;
(4-3) judging whether m is larger than the total number of the rings identified in the step (3), if so, ending the process, otherwise, turning to the step (4-4);
(4-4) setting a counter n to 1;
(4-5) judging whether n is larger than the total number of the nodes in the mth ring identified in the step (3), if so, turning to the step (4-11), otherwise, turning to the step (4-6);
(4-6) obtaining a type identifier corresponding to the nth node C in the mth ring, judging whether the type identifier exists in the register list in the step (4-1), if so, turning to the step (4-7), otherwise, turning to the step (4-10);
(4-7) acquiring a corresponding node of the node C in the incoming edge adjacency list and an edge list of a corresponding node of the node C in the incoming edge adjacency list corresponding to the edge of the mth ring, acquiring a type identifier corresponding to a node D at the other end of the edge, judging whether the type identifier exists in the register list, if so, turning to the step (4-8), otherwise, turning to the step (4-9);
(4-8) according to the node C and the corresponding node in the edge entering adjacency list and the edge exiting adjacency list obtained by the node D in the step (1), judging whether the number of the edge entering of the node C is larger than 1 or an edge exists or not, and whether the number of the edge exiting of the node C is larger than 1 or an edge entering exists or not, if so, deleting all the edge entering of the node C in the mth ring in the preprocessed graph obtained in the step (2), deleting the corresponding data of the edge entering in the edge entering adjacency list and the edge exiting adjacency list, then turning to the step (4-10), otherwise, turning to the step (4-10).
(4-9) judging whether the number of incoming edges of the node C is larger than 1 or an outgoing edge exists according to the corresponding node of the node C in the incoming edge adjacency list and the outgoing edge adjacency list obtained in the step (1), deleting all incoming edges of the node C in the mth ring in the preprocessed graph obtained in the step (2) if the number of incoming edges of the node C is larger than 1 or the outgoing edge exists, deleting data of the edges in the incoming edge adjacency list and the outgoing edge adjacency list corresponding to the edges, turning to the step (4-10), and otherwise, turning to the step (4-10);
(4-10) setting n ═ n +1, and returning to step (4-5);
(4-11) setting m ═ m +1, and returning to step (4-3).
Preferably, for each single unidirectional connected graph obtained in step (4), a node with an in degree of 0 of the unidirectional connected graph is found at the head of the outgoing adjacency list. And additionally constructing a node with the point weight of 0, namely a pseudo source point, setting the serial number of the pseudo source point as the maximum node serial number plus 1, connecting the pseudo source point with the node with the degree of income of each sub-graph acquired in the previous step through a directed edge with the edge weight of 0, and adding the pseudo source point and the edge associated with the pseudo source point into an edge entering adjacent table and an edge exiting adjacent table. The subgraphs are synthesized into a weakly connected graph in this way, so that a final target DAG graph is formed, wherein the DAG graph comprises all nodes except isolated points and pseudo source points in the original graph.
According to another aspect of the invention, there is provided a system for converting a very large netlist into a DAG map, comprising:
a first module for obtaining a netlist, extracting circuit units and connection information thereof from the netlist to generate a graph, which is stored with an incoming adjacency list and an outgoing adjacency list;
the second module is used for preprocessing the graph obtained by the first module to obtain a preprocessed graph;
a third module, configured to detect all strongly connected components in the graph preprocessed by the second module, identify multiple rings according to all strongly connected components, extract a node number in each ring, and sequence numbers of edges connected to each node in the ring in an edge entry adjacency table and an edge exit adjacency table;
a fourth module, configured to cut incoming edges meeting the predetermined condition in the ring according to sequence numbers, in the incoming edge adjacency table, of the nodes and edges in each ring obtained in the third module, so as to obtain multiple unidirectionally-communicated subgraphs;
and the fifth module is used for associating the plurality of unidirectional connected graphs obtained by the fourth module by using the virtual node so as to obtain the target DAG graph.
In general, compared with the prior art, the above technical solution contemplated by the present invention can achieve the following beneficial effects:
(1) because the invention adopts the method of abstracting the netlist into the graph in the step (1), the invention covers the content of the netlist as much as possible, and the meanings of the edge weight and the point weight can be changed along with the difference of the analysis and the design scenes, so the applicability is very wide;
(2) because the method of cutting off the ring in the step (4) is adopted, the influence of analyzing and designing the original netlist is very low, and new isolated points cannot be generated;
(3) because the method for synthesizing the weak connection graph in the step (5) is adopted, the finally obtained DAG graph can be ensured to contain all nodes of the original graph except for the isolated points, and the design of the pseudo source points can not bring adverse topological influence to the graph;
(4) the invention has the advantages of simple realization, high execution speed and good execution result effect.
Drawings
FIG. 1 is a flow diagram of a method of the present invention for converting a very large netlist to a DAG diagram;
FIG. 2 is a schematic representation of the conversion of a netlist into a graph in step (1) of the method of the present invention;
FIG. 3 is a schematic diagram of the synthesis of a weakly connected graph from the unidirectional connected subgraphs in step (5) of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The basic idea of the invention is to read in the complete net list, convert it into the form of graph according to the complete net list, then preprocess the graph, eliminate all isolated points therein, then extract the strongly connected components in the graph, judge whether each strongly connected component is a ring, cut the edge in each ring which meets the predetermined condition, and finally synthesize all the obtained subgraphs into a weakly connected graph. The weak connection graph is a target DAG graph and comprises all nodes except isolated points in the original graph.
As shown in FIG. 1, the present invention provides a method for converting a very large netlist into a DAG graph, comprising the steps of:
(1) acquiring a netlist, extracting circuit units and connection information thereof from the netlist to generate a graph, and storing the graph by using an incoming side adjacency list and an outgoing side adjacency list;
the method comprises the following steps of firstly obtaining a netlist, converting circuit units and connection information thereof in the netlist into a graph form, neglecting input and output connection between the outside and a circuit module, and recording the circuit units and the connection information between the inside of the circuit units in the netlist.
The process of preliminarily converting the netlist into the graph is shown in fig. 2, wherein a circuit unit is abstracted into a node, a type identifier is used for representing the type of the circuit unit mapped by the node, parameters such as the area or the capacity of the circuit unit are abstracted into point weights, the communication time among the circuit units is abstracted into edge weights, and then topology information of the graph is stored by using an edge-entering adjacency table and an edge-exiting adjacency table respectively.
The edge-entering adjacency list is a linked list, wherein the entry of each node comprises the serial number of the node in the graph, the serial numbers of all edges pointing to the node, the weight (namely the edge weight) of each edge, the serial number of another node corresponding to the edge, and a pointer pointing to the node corresponding to the another node; the entry of each node in the outgoing edge adjacency list comprises the serial number of the node, the serial numbers of all edges pointed by the node, the edge weight of each edge, the serial number of another node corresponding to the edge, and a pointer pointing to the node corresponding to the another node.
With respect to fig. 2, it can be seen that element a in the netlist is abstracted to node 1 with point weight 9 in the figure, and is ignored because the input connecting line of element a in the netlist is an external input; the line from element a to element c in the netlist is abstracted to an edge with point weight 2 in the figure.
The step (1) has the advantages that the circuit unit content and the topological structure in the netlist are abstracted by using the node, the edge and the point form, the information of the netlist is covered as much as possible, the significance of the edge and the point can be changed according to different analysis and design scenes, and the applicability is very wide;
(2) preprocessing the graph obtained in the step (1) to obtain a preprocessed graph;
the method comprises the following specific steps: and (2) sequentially accessing each node in the edge-entering adjacency list and the edge-exiting adjacency list in the graph obtained in the step (1), finding all isolated points (namely nodes without edges entering and exiting), deleting the isolated points from the graph obtained in the step (1), reordering the sequence numbers of the rest points, and filling the nodes with large sequence numbers forwards to ensure that the sequence numbers of the nodes are still continuous, thereby obtaining the preprocessed graph. And updating the deletion and the point sequence of the nodes in the incoming adjacency list and the outgoing adjacency list respectively.
(3) Detecting all the strongly connected components in the graph preprocessed in the step (2), identifying a plurality of rings according to all the strongly connected components, and extracting the node serial number in each ring and the serial numbers of the edges connected with each node in the ring in an edge-entering adjacency list and an edge-exiting adjacency list;
the method specifically comprises the following substeps:
(3-1) setting a counter i to 1;
(3-2) judging whether i is larger than the total number of the nodes in the graph preprocessed in the step (2), if so, turning to the step (3-5), otherwise, turning to the step (3-3);
(3-3) processing the graph preprocessed in the step (2) according to a Depth First Search (DFS) algorithm, reading in the ith node, setting the access sequence number value p of the node as i, and placing the node on the stack top;
(3-4) setting i ═ i +1, and returning to step (3-2);
(3-5) setting a counter j equal to 1;
(3-6) judging whether j is larger than the total number of the nodes in the graph preprocessed in the step (2), if so, turning to the step (3-9), otherwise, turning to the step (3-7);
(3-7) acquiring the jth node A from the stack obtained in the step (3-3) according to the sequence from top to bottom, acquiring the node B with the smallest access sequence number value p which can be reached by the node A through an outgoing edge according to an outgoing edge adjacency list, setting the farthest backtracking value q of the node A as the sequence number of the node B, and taking the path from the node A to the node B as the farthest backtracking path of the node A;
(3-8) setting j ═ j +1, and returning to step (3-6);
(3-9) setting a counter k equal to 1;
(3-10) judging whether k is larger than the total number of the nodes in the graph preprocessed in the step (2), if so, turning to the step (3-13), otherwise, turning to the step (3-11);
(3-11) acquiring a kth node from the stack obtained in the step (3-7) according to the sequence from top to bottom, judging whether the access sequence number value p of the node is equal to a farthest backtracking value q, if so, popping all nodes (including a stack top node and the kth node) from the top of the stack to the kth node, extracting all node and edge sequence numbers on the farthest backtracking path of the kth node from an edge-entering adjacency list, wherein the nodes and edges form a strongly-connected component, and turning to the step (3-12), otherwise, turning to the step (3-12);
(3-12) setting k ═ k +1, and returning to step (3-10);
(3-13) identifying the strongly connected component with the number of nodes larger than 1 in the obtained strongly connected component as a ring;
(3-14) recording nodes corresponding to the nodes in the edge-in adjacency list and the edge-out adjacency list in the graph and edges corresponding to the nodes in the edge-in adjacency list and the edge-out adjacency list in the graph aiming at the nodes and the edges in each ring identified in the step (3-13), and ending the process.
(4) Cutting the incoming edges meeting the preset conditions in the ring according to the sequence numbers of the nodes and the edges in the incoming edge adjacency list in each ring obtained in the step (3) to obtain a plurality of unidirectionally communicated subgraphs;
specifically, step (4) includes the following substeps:
(4-1) storing the type identifications corresponding to all circuit units in the process of converting the netlist in the step (1) into the graph into a register list (which is specifically a set container in the invention);
for example, if there are three circuit units in the netlist in step (1): the device comprises a register, an arithmetic unit and a logic judger, wherein the identifier of the register is 1, the identifier of the arithmetic unit is 2, and the identifier of the logic register is 3;
the advantage of the above step (4-1) is that the set container is used to store the register list, and all subsequent matching of the circuit unit type identifier of the node with the register list will be very fast;
(4-2) setting a counter m to 1;
(4-3) judging whether m is larger than the total number of the rings identified in the step (3), if so, ending the process, otherwise, turning to the step (4-4);
(4-4) setting a counter n to 1;
(4-5) judging whether n is larger than the total number of the nodes in the mth ring identified in the step (3), if so, turning to the step (4-11), otherwise, turning to the step (4-6);
(4-6) obtaining a type identifier corresponding to the nth node C in the mth ring, judging whether the type identifier exists in the register list in the step (4-1), if so, turning to the step (4-7), otherwise, turning to the step (4-10);
(4-7) acquiring a node corresponding to the node C in the incoming edge adjacency list and an edge bar of the node C in the mth ring (which is recorded in the step (3-14)) corresponding to the node in the incoming edge adjacency list, acquiring a type identifier corresponding to the node D at the other end of the edge, judging whether the type identifier exists in the register list, if so, turning to the step (4-8), otherwise, turning to the step (4-9);
(4-8) according to the node C and the corresponding node in the edge entering adjacency list and the edge exiting adjacency list obtained by the node D in the step (1), judging whether the number of the edge entering of the node C is larger than 1 or an edge exists or not, and whether the number of the edge exiting of the node C is larger than 1 or an edge entering exists or not, if so, deleting all the edge entering of the node C in the mth ring in the preprocessed graph obtained in the step (2), deleting the corresponding data of the edge entering in the edge entering adjacency list and the edge exiting adjacency list, then turning to the step (4-10), otherwise, turning to the step (4-10).
(4-9) judging whether the number of incoming edges of the node C is larger than 1 or an outgoing edge exists according to the corresponding node of the node C in the incoming edge adjacency list and the outgoing edge adjacency list obtained in the step (1), deleting all incoming edges of the node C in the mth ring in the preprocessed graph obtained in the step (2) if the number of incoming edges of the node C is larger than 1 or the outgoing edge exists, deleting data of the edges in the incoming edge adjacency list and the outgoing edge adjacency list corresponding to the edges, turning to the step (4-10), and otherwise, turning to the step (4-10);
(4-10) setting n ═ n +1, and returning to step (4-5);
(4-11) setting m ═ m +1, and returning to the step (4-3);
the step (4) has the advantages that all rings in the graph can be accurately cut off, new isolated points cannot be generated, information in the netlist is kept as much as possible, and a cushion is made for the finally generated DAG graph. The data originally transmitted to the register node with the deleted edge can be written in a set mode, so that the adverse effect on the operation of the whole circuit is not great. If the netlist has circuit units without the register type, the equivalent netlist with the register type can be generated through an instruction, so that the method is still applicable;
(5) and (4) associating the plurality of unidirectional connected graphs obtained in the step (4) by using the virtual nodes, so as to obtain a target DAG graph.
The method comprises the following specific steps: and (4) for each single unidirectional connected graph obtained in the step (4), finding a node with the degree of entry of 0 of the unidirectional connected graph at the head of the exit adjacency list. And constructing a node with a point weight of 0, wherein the node is called a pseudo source point, setting the serial number of the pseudo source point as the maximum node serial number and adding 1, connecting the pseudo source point with the node with the degree of entry of 0 of each sub-graph obtained in the last step through a directed edge with an edge weight of 0, and adding the pseudo source point and the edge associated with the pseudo source point into an edge entry adjacent table and an edge exit adjacent table. The weakly connected graph synthesized from these subgraphs in this way is the final target DAG graph. The DAG graph contains all nodes except isolated points in the original graph and an artificially constructed pseudo-source point.
As shown in fig. 3, in this example, 3 unidirectionally-connected subgraphs are obtained through step (4), which are subgraphs including nodes 1, 2, and 3, respectively, subgraphs including nodes 4, 5, 6, 7, and 8, and subgraphs including nodes 9, 10, 11, 12, 13, and 14, the node with the first unidirectionally-connected graph whose degree of entry is 0 is node No. 1, the node with the second unidirectionally-connected graph whose degree of entry is 0 is node No. 4, the node with the third degree of entry being 0 is node No. 9, then node No. 15 with a point weight of 0 is newly added, and node No. 15 is connected to node No. 1, node No. 4, and node No. 9 through three directed edges with the point weight of 0, and finally a weakly-connected graph is obtained, which is the final target DAG graph.
The step (5) has the advantages that all the subgraphs obtained in the step (4) can be quickly synthesized into a weakly connected graph, all the nodes except isolated points in the original graph are included, and the topological structure in the original graph cannot be adversely affected because the weights of the pseudo source points and the edges output by the pseudo source points are 0.
As can be seen, the invention can realize modeling of an ultra-large-scale netlist into a DAG graph at one time, and the information of the original netlist is kept as much as possible, so that the design or the time sequence analysis of the netlist can be carried out more smoothly. The invention has very fast running speed, and only needs a few minutes for a million-level transistor-scale netlist.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (5)
1. A method for converting a very large netlist to a DAG graph, comprising the steps of:
(1) obtaining a netlist, extracting circuit units and connection information thereof from the netlist to generate a graph, and storing the graph by using an incoming side adjacency list and an outgoing side adjacency list; the method comprises the following steps that (1) a netlist is obtained firstly, circuit units and connection information thereof in the netlist are converted into a form of a graph, input and output connection lines between the outside and circuit modules are omitted, and the circuit units and the connection information between the inside and the outside in the netlist are recorded;
in the conversion process, abstracting a circuit unit into nodes, representing the type of the circuit unit mapped by the nodes by using a type identifier, abstracting area or capacity parameters of the circuit unit into point weights, abstracting communication time among the circuit units into edge weights, and then storing topology information of a graph by using an edge-in adjacency list and an edge-out adjacency list respectively;
(2) preprocessing the graph obtained in the step (1) to obtain a preprocessed graph;
(3) detecting all the strongly connected components in the graph preprocessed in the step (2), identifying a plurality of rings according to all the strongly connected components, and extracting the node serial number in each ring and the serial numbers of the edges connected with each node in the ring in an edge-entering adjacency list and an edge-exiting adjacency list; the step (3) specifically comprises the following substeps:
(3-1) setting a counter i to 1;
(3-2) judging whether i is larger than the total number of the nodes in the graph preprocessed in the step (2), if so, turning to the step (3-5), otherwise, turning to the step (3-3);
(3-3) processing the graph preprocessed in the step (2) according to a depth-first search algorithm (DFS), reading in the ith node, setting the access sequence number value p of the node as i, and placing the node on the top of the stack;
(3-4) setting i ═ i +1, and returning to step (3-2);
(3-5) setting a counter j equal to 1;
(3-6) judging whether j is larger than the total number of the nodes in the graph preprocessed in the step (2), if so, turning to the step (3-9), otherwise, turning to the step (3-7);
(3-7) acquiring the jth node A from the stack obtained in the step (3-3) according to the sequence from top to bottom, acquiring the node B with the smallest access sequence number value p which can be reached by the node A through an outgoing edge according to an outgoing edge adjacency list, setting the farthest backtracking value q of the node A as the sequence number of the node B, and taking the path from the node A to the node B as the farthest backtracking path of the node A;
(3-8) setting j ═ j +1, and returning to step (3-6);
(3-9) setting a counter k equal to 1;
(3-10) judging whether k is larger than the total number of the nodes in the graph preprocessed in the step (2), if so, turning to the step (3-13), otherwise, turning to the step (3-11);
(3-11) acquiring the kth node from the stack obtained in the step (3-7) according to the sequence from top to bottom, judging whether the access sequence number value p of the node is equal to the farthest backtracking value q, if so, popping all nodes between the top of the stack and the kth node, extracting all nodes and edge sequence numbers on the farthest backtracking path of the kth node from an edge-entering adjacency list, wherein the nodes and the edges form a strongly-connected component, and turning to the step (3-12), otherwise, turning to the step (3-12);
(3-12) setting k ═ k +1, and returning to step (3-10);
(3-13) identifying the strongly connected component with the number of nodes larger than 1 in the obtained strongly connected component as a ring;
(3-14) recording nodes corresponding to the nodes in the edge-entering adjacency list and the edge-exiting adjacency list in the graph and edges corresponding to the edges in the edge-entering adjacency list and the edge-exiting adjacency list in the graph aiming at the nodes and the edges in each ring identified in the step (3-13), and ending the process;
(4) cutting the incoming edges meeting the preset conditions in the ring according to the sequence numbers of the nodes and the edges in the incoming edge adjacency list in each ring obtained in the step (3) to obtain a plurality of unidirectionally communicated subgraphs; the step (4) comprises the following substeps:
(4-1) storing the type identifications corresponding to all circuit units in the process of converting the netlist in the step (1) into the diagram into a register list;
(4-2) setting a counter m ═ 1;
(4-3) judging whether m is larger than the total number of the rings identified in the step (3), if so, ending the process, otherwise, turning to the step (4-4);
(4-4) setting a counter n to 1;
(4-5) judging whether n is larger than the total number of the nodes in the mth ring identified in the step (3), if so, turning to the step (4-11), otherwise, turning to the step (4-6);
(4-6) acquiring a type identifier corresponding to the nth node C in the mth ring, judging whether the type identifier exists in the register list in the step (4-1), if so, turning to the step (4-7), otherwise, turning to the step (4-10);
(4-7) acquiring a node corresponding to the node C in the incoming edge adjacency list and an edge list of the node C in the m-th ring corresponding to the node in the incoming edge adjacency list, acquiring a type identifier corresponding to a node D at the other end of the edge, judging whether the type identifier exists in the register list, if so, turning to the step (4-8), otherwise, turning to the step (4-9);
(4-8) according to the node C and the corresponding node in the edge entering adjacency list and the edge exiting adjacency list obtained by the node D in the step (1), judging whether the number of the edge entering of the node C is greater than 1 or an edge exists or not, and whether the number of the edge exiting of the node C is greater than 1 or an edge entering exists or not, if so, deleting all the edge entering of the node C in the mth ring in the preprocessed graph obtained in the step (2), deleting the corresponding data of the edge entering in the edge entering adjacency list and the edge exiting adjacency list, then turning to the step (4-10), otherwise, turning to the step (4-10);
(4-9) judging whether the number of the incoming edges of the node C is greater than 1 or an outgoing edge exists according to the corresponding node of the node C in the incoming edge adjacent table and the outgoing edge adjacent table obtained in the step (1), if so, deleting all the incoming edges of the node C in the mth ring in the preprocessed graph obtained in the step (2), deleting data of the edges corresponding to the incoming edge adjacent table and the outgoing edge adjacent table, turning to the step (4-10), and otherwise, turning to the step (4-10);
(4-10) setting n to n +1, and returning to the step (4-5);
(4-11) setting m ═ m +1, and returning to the step (4-3);
(5) and (4) associating the plurality of unidirectional connected graphs obtained in the step (4) by using the virtual nodes, so as to obtain a target DAG graph.
2. The method for converting a very large netlist to a DAG map as recited in claim 1,
the entry of each node in the edge adjacency list comprises the serial number of the node in the graph, the serial numbers of all edges pointing to the node and the weight of each edge, the serial number of another node corresponding to the edge and a pointer pointing to the node corresponding to the another node;
the entry of each node in the outgoing edge adjacency list comprises the serial number of the node, the serial numbers of all edges pointed by the node, the edge weight of each edge, the serial number of another node corresponding to the edge, and a pointer pointing to the node corresponding to the another node.
3. The method for converting the very-large-scale netlist into the DAG graph according to claim 2, wherein the step (2) is specifically configured to sequentially access each node in the edge-entering adjacency table and the edge-exiting adjacency table in the graph obtained in the step (1), find all outliers, delete the outliers from the graph obtained in the step (1), reorder the sequence numbers of the remaining points, and perform forward completion on the nodes with large sequence numbers so that the sequence numbers of the nodes are still continuous, thereby obtaining the preprocessed graph, wherein the outliers are nodes without edges entering or exiting.
4. The method for converting a very large netlist to a DAG graph as claimed in claim 3, wherein for each individual one-way connectivity graph obtained in step (4), a node with an in degree of 0 of the one-way connectivity graph is found at the head of the out-of-edge adjacency list; constructing a node with a point weight of 0, namely a pseudo source point, setting the serial number of the pseudo source point as the maximum node serial number plus 1, connecting the pseudo source point with the node with the degree of 0 of each sub-graph obtained in the last step through a directed edge with an edge weight of 0, and adding the pseudo source point and the edge associated with the pseudo source point into an edge-entering adjacent table and an edge-exiting adjacent table; the subgraphs are synthesized in this way into a weakly connected graph, forming the final target DAG graph, which contains all nodes and pseudo-source points in the original graph except for isolated points.
5. A system for converting a very large netlist to a DAG graph, comprising:
a first module for obtaining a netlist, extracting circuit units and connection information thereof from the netlist to generate a graph, which is stored with an incoming adjacency list and an outgoing adjacency list; the first module is specifically that firstly, a net list is obtained, circuit units and connection information thereof in the net list are converted into a form of a picture, input and output connection lines between the outside and the circuit modules are omitted, and the circuit units and the connection information between the inside and the outside in the net list are recorded;
in the conversion process, abstracting a circuit unit into nodes, representing the type of the circuit unit mapped by the nodes by using a type identifier, abstracting area or capacity parameters of the circuit unit into point weights, abstracting communication time among the circuit units into edge weights, and then storing topology information of a graph by using an edge-in adjacency list and an edge-out adjacency list respectively;
the second module is used for preprocessing the graph obtained by the first module to obtain a preprocessed graph;
a third module, configured to detect all strongly connected components in the graph preprocessed by the second module, identify multiple rings according to all strongly connected components, and extract a node number in each ring and sequence numbers of edges connected to each node in the ring in the edge entering adjacency table and the edge exiting adjacency table; the third module specifically includes the following sub-modules:
a first submodule for setting a counter i to 1;
the second sub-module is used for judging whether i is larger than the total number of the nodes in the graph pretreated by the second module, if so, switching to the fifth sub-module, and otherwise, switching to the third sub-module;
the third sub-module is used for processing the graph preprocessed by the second module according to a depth-first search algorithm DFS, reading in the ith node, setting the access sequence number value p of the node as i, and placing the node on the stack top;
the fourth submodule is used for setting i to i +1 and returning to the second submodule;
a fifth sub-module for setting the counter j to 1;
the sixth submodule is used for judging whether j is larger than the total number of nodes in the graph preprocessed by the second module, if so, switching to the ninth submodule, and otherwise, switching to the seventh submodule;
a seventh sub-module, configured to obtain a jth node a from a stack obtained by the third sub-module in an order from top to bottom, obtain, according to an outgoing adjacency list, a node B with a smallest access sequence number value p that the node a can reach through an outgoing edge, set a farthest backtracking value q of the node a as a sequence number of the node B, and use a path from the node a to the node B as a farthest backtracking path of the node a;
the eighth submodule is used for setting j to j +1 and returning to the sixth submodule;
a ninth sub-module for setting a counter k to 1;
the tenth submodule is used for judging whether k is larger than the total number of nodes in the graph preprocessed by the second module, if so, switching to the thirteenth submodule, and otherwise, switching to the eleventh submodule;
an eleventh sub-module, configured to obtain a kth node from a stack obtained by the seventh sub-module according to a sequence from top to bottom, determine whether an access sequence number value p of the node is equal to a farthest backtracking value q, if so, pop all nodes from the top of the stack to the kth node, and extract all nodes and edge sequence numbers on a farthest backtracking path of the kth node in an edge-entry adjacency table, where the nodes and edges form a strongly-connected component and are transferred to a twelfth sub-module, and otherwise, transfer to a twelfth sub-module;
the twelfth submodule is used for setting k to k +1 and returning to the tenth submodule;
a thirteenth submodule, configured to identify a strongly connected component with a node number greater than 1 in the obtained strongly connected component as a ring;
a fourteenth sub-module, configured to record, for a node and an edge in each ring identified in the thirteenth sub-module, a node of the entry adjacency table and a node of the exit adjacency table corresponding to the node in the graph and an edge of the node of the entry adjacency table and the exit adjacency table corresponding to the edge in the graph, where the process is ended;
a fourth module, configured to cut incoming edges meeting the predetermined condition in the ring according to sequence numbers, in the incoming edge adjacency table, of the nodes and edges in each ring obtained in the third module, so as to obtain multiple unidirectionally-communicated subgraphs; the fourth module comprises the sub-steps of:
the fifteenth submodule is used for storing the type identifications corresponding to all the circuit units in the process of converting the first module from the netlist into the graph into the register list;
a sixteenth sub-module for setting the counter m to 1;
a seventeenth sub-module for determining whether m is greater than the total number of rings identified in the third module, if so, ending the process, otherwise, turning to an eighteenth sub-module;
an eighteenth sub-module for setting the counter n to 1;
the nineteenth sub-module is used for judging whether n is larger than the total number of the nodes in the mth ring identified in the third module, if so, switching to the twenty-fifth sub-module, and otherwise, switching to the twentieth sub-module;
the twentieth sub-module is used for acquiring the type identifier corresponding to the nth node C in the mth ring, judging whether the type identifier exists in a register list of the fifteenth sub-module, if so, switching to the twenty-first sub-module, and otherwise, switching to the twenty-fourth sub-module;
a twenty-first sub-module, configured to obtain a node corresponding to the node C in the incoming edge adjacency list and a side entry of the node C in the m-th ring corresponding to the node in the incoming edge adjacency list, and then obtain a type identifier corresponding to a node D at the other end of the side, and determine whether the type identifier exists in the register list, if so, switch to a twenty-second sub-module, otherwise, switch to a twenty-third sub-module;
a twenty-second sub-module, configured to determine, according to nodes corresponding to the node C and the node D in the entry edge adjacency table and the exit edge adjacency table obtained by the first module, whether the number of entry edges of the node C is greater than 1 or an exit edge exists, and whether the number of exit edges of the node C is greater than 1 or an entry edge exists, if yes, delete all entry edges of the node C in the mth ring in the preprocessed graph obtained by the second module, delete corresponding data of the entry edges in the entry edge adjacency table and the exit edge adjacency table, and then switch to a twenty-fourth sub-module, otherwise switch to a twenty-fourth sub-module;
a twenty-third sub-module, configured to determine, according to a node corresponding to the node C in the entry adjacent table and the exit adjacent table obtained by the first module, whether the entry number of the node C is greater than 1 or an exit exists, if yes, delete all entries of the node C in the mth ring in the preprocessed graph obtained by the second module, delete data corresponding to the edges in the entry adjacent table and the exit adjacent table, and switch to a twenty-fourth sub-module, otherwise switch to a twenty-fourth sub-module;
the twenty-fourth sub-module is used for setting n to be n +1 and returning to the nineteenth sub-module;
the twenty-fifth sub-module is used for setting m to be m +1 and returning to the seventeenth sub-module;
and the fifth module is used for associating the plurality of unidirectional connected graphs obtained by the fourth module by using the virtual node so as to obtain the target DAG graph.
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