CN113064333A - Photoetching method of tiny wafer, wafer carrier and photoetching tool - Google Patents
Photoetching method of tiny wafer, wafer carrier and photoetching tool Download PDFInfo
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- CN113064333A CN113064333A CN202110295030.XA CN202110295030A CN113064333A CN 113064333 A CN113064333 A CN 113064333A CN 202110295030 A CN202110295030 A CN 202110295030A CN 113064333 A CN113064333 A CN 113064333A
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- wafer
- photoetched
- carrier
- clamping groove
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7073—Alignment marks and their environment
- G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/38—Treatment before imagewise removal, e.g. prebaking
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7073—Alignment marks and their environment
- G03F9/7084—Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
- H01L21/682—Mask-wafer alignment
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The invention discloses a photoetching method of a tiny wafer, which is characterized in that a wafer to be photoetched is embedded in a wafer loading clamping groove of a wafer carrier; the wafer slide comprises an alignment mark coplanar with the wafer loading clamping groove; gluing and baking the wafer to be photoetched; carrying out projection exposure on the baked wafer to be photoetched according to the alignment mark; and developing the exposed wafer to be photoetched to obtain the micro wafer with the graphical photoresist layer. In addition, the alignment mark arranged on the wafer carrier provides an alignment basis for the projection exposure step, and a projection photoetching machine can be used for automatic alignment, so that the alignment precision and the production efficiency of photoetching are greatly improved. The invention also provides a wafer carrier and a photoetching tool with the beneficial effects.
Description
Technical Field
The invention relates to the field of wafer photoetching, in particular to a photoetching method of a tiny wafer, a wafer carrier and a photoetching tool.
Background
The infrared detector manufacturing process part relates to the processing technology of a circular jewel or a ceramic wafer (hereinafter referred to as a wafer), the diameter of the wafer is different from several millimeters to dozens of millimeters, and corresponding pattern processing is needed to be carried out on the wafer to realize different optical or electrical effects. The most common patterning process is photolithography, which involves processes such as coating, exposing, and developing a wafer. The quality of the wafer patterning is an important factor affecting the quality of the final detector.
In the existing wafer processing process, a micro vacuum adsorption hole is generally adopted to directly adsorb a wafer, then a gluing process is carried out, and the wafer is generally circular, so that a clear reference edge or a reference pattern is not provided, a projection type photoetching machine cannot be used for alignment and photoetching, a contact type photoetching mode is generally utilized for manual alignment, the manual alignment precision is not difficult to know, the offset and the loss are easy to generate, and the process efficiency is low; in addition, the glue layer is larger at the edge of the wafer due to the edge effect, and the glue coating uniformity is poor.
In summary, how to improve the uniformity and the corresponding precision of the photoresist coating and improve the production efficiency at the same time is a problem to be solved urgently by those skilled in the art.
Disclosure of Invention
The invention aims to provide a photoetching method of a tiny wafer, a wafer carrier and a photoetching tool, and aims to solve the problems of poor gluing uniformity, low alignment precision and low production efficiency in photoetching in the prior art.
In order to solve the above technical problem, the present invention provides a photolithography method for a micro wafer, comprising:
embedding the wafer to be photoetched on a wafer loading clamping groove of a wafer carrier; the wafer slide comprises an alignment mark coplanar with the wafer loading clamping groove;
gluing and baking the wafer to be photoetched;
carrying out projection exposure on the baked wafer to be photoetched according to the alignment mark;
and developing the exposed wafer to be photoetched to obtain the micro wafer with the graphical photoresist layer.
Optionally, in the photolithography method for a micro wafer, the wafer carrier includes a plurality of wafer loading slots;
correspondingly, the projection exposure of the baked wafer to be photoetched according to the alignment mark comprises the following steps:
and carrying out step-by-step projection exposure on the baked wafers to be photoetched according to the alignment marks.
A wafer carrier is provided, the surface of the wafer carrier comprises a chip loading clamping groove and an alignment mark coplanar with the chip loading clamping groove;
the chip mounting clamping groove is used for embedding a chip to be photoetched;
the alignment mark is used as a positioning basis in the projection exposure process of the wafer to be photoetched.
Optionally, in the wafer carrier, the alignment mark is disposed at an edge and a center of the wafer carrier.
Optionally, in the wafer slide, the alignment marks are cross marks.
Optionally, in the wafer slide, a difference between a size of the wafer loading slot and a size of the wafer to be lithographed ranges from 5 micrometers to 10 micrometers inclusive.
Optionally, in the wafer slide, a difference between a depth of the wafer loading slot and a thickness of the wafer to be lithographed ranges from 0 micron to 30 microns, inclusive.
Optionally, in the wafer carrier, the wafer carrier is a corrosion-resistant carrier.
Optionally, in the wafer carrier, the wafer carrier is a silicon wafer.
A lithography tool comprising a wafer carrier as claimed in any one of the above.
The photoetching method of the tiny wafer provided by the invention is characterized in that the wafer to be photoetched is embedded in a wafer loading clamping groove of a wafer carrier; the wafer slide comprises an alignment mark coplanar with the wafer loading clamping groove; gluing and baking the wafer to be photoetched; carrying out projection exposure on the baked wafer to be photoetched according to the alignment mark; and developing the exposed wafer to be photoetched to obtain the micro wafer with the graphical photoresist layer. In addition, the alignment mark arranged on the wafer carrier provides an alignment basis for the projection exposure step, and a projection photoetching machine can be used for automatic alignment, so that the alignment precision and the production efficiency of photoetching are greatly improved. The invention also provides a wafer carrier and a photoetching tool with the beneficial effects.
Drawings
In order to more clearly illustrate the embodiments or technical solutions of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic diagram illustrating a position relationship of a wafer to be subjected to photolithography in a glue coating process in the prior art;
FIG. 2 is a schematic diagram of a structure of a wafer to be lithographed after glue spreading in the prior art;
FIG. 3 is a flow chart illustrating a photolithography method for a micro wafer according to an embodiment of the present invention;
FIG. 4 is a flow chart illustrating another embodiment of a photolithography method for a micro wafer according to the present invention;
fig. 5 is a schematic structural diagram of an embodiment of a wafer carrier according to the present invention.
Detailed Description
In the prior art, a wafer to be photoetched is placed on a glue coating disc in advance for rotary glue coating, a position relation diagram of the wafer to be photoetched and the glue coating disc is shown in fig. 1, the thickness of a glue layer at the center of a spin-coated photoresist layer is obviously smaller than that of the edge due to the edge effect, and as shown in fig. 2, the problem is solved by arranging the wafer to be photoetched in a wafer carrier.
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The core of the present invention is to provide a photolithography method for a micro wafer, a flow chart of one embodiment of which is shown in fig. 3, comprising:
s101: embedding the wafer to be photoetched on a wafer loading clamping groove of a wafer carrier; wherein the wafer slide comprises an alignment mark coplanar with the wafer loading slot.
The embedding finger is used for arranging the wafer to be photoetched in the wafer mounting clamping groove, and the wafer to be photoetched can be fixedly connected with the wafer mounting grass and also can be simply placed in the wafer mounting clamping groove.
S102: and gluing and baking the wafer to be photoetched.
Because the side wall of the wafer to be subjected to photoetching and the wafer loading clamping groove are difficult to completely fit, a small gap between the side wall of the wafer to be subjected to photoetching and the wafer loading clamping groove can attract a photoresist layer arranged in the gluing process, so that the edge effect of single-wafer gluing is avoided, and the gluing uniformity is greatly improved.
S103: and carrying out projection exposure on the baked wafer to be photoetched according to the alignment mark.
The projection exposure can be automatically exposed through a projection photoetching machine, the alignment mark is used for positioning, the wafer alignment precision is greatly improved, the alignment mark can be a coating arranged on a wafer carrier, a groove patterned in advance on the wafer carrier or other graphic patterns capable of being recognized by a machine, and specific means can be selected according to actual conditions.
S104: and developing the exposed wafer to be photoetched to obtain the micro wafer with the graphical photoresist layer.
The photoetching method of the tiny wafer provided by the invention is characterized in that the wafer to be photoetched is embedded in a wafer loading clamping groove of a wafer carrier; the wafer slide comprises an alignment mark coplanar with the wafer loading clamping groove; gluing and baking the wafer to be photoetched; carrying out projection exposure on the baked wafer to be photoetched according to the alignment mark; and developing the exposed wafer to be photoetched to obtain the micro wafer with the graphical photoresist layer. In addition, the alignment mark arranged on the wafer carrier provides an alignment basis for the projection exposure step, and a projection photoetching machine can be used for automatic alignment, so that the alignment precision and the production efficiency of photoetching are greatly improved.
On the basis of the first specific embodiment, the projection exposure step is further limited to obtain a second specific embodiment, a schematic flow chart of which is shown in fig. 4, and includes:
s201: embedding the wafer to be photoetched on a wafer loading clamping groove of a wafer carrier; wherein the wafer slide comprises an alignment mark coplanar with the wafer loading slot.
S202: and gluing and baking the wafer to be photoetched.
S203: the wafer slide comprises a plurality of wafer loading clamping grooves, and the baked wafers to be photoetched are subjected to stepping projection exposure according to the alignment marks.
The step-by-step projection exposure refers to sequentially carrying out projection exposure on a plurality of wafers to be photoetched on the same wafer carrier.
S204: and developing the exposed wafer to be photoetched to obtain the micro wafer with the graphical photoresist layer.
In the specific embodiment, the projection type photoetching machine is utilized to sequentially carry out projection exposure on a plurality of wafers to be photoetched on the same wafer carrier, compared with the prior art that the wafers are required to be replaced and recalibrated once one wafer is photoetched, the specific embodiment does not need to be recalibrated on the same wafer carrier before the wafers to be photoetched are photoetched, and the production efficiency is greatly improved.
An example of a complete process of microchip lithography is described in detail below, which includes:
step 1: coating photoresist on a silicon wafer serving as a carrier, and performing layout design and photoetching according to the structure shown in FIG. 2, wherein the graphic size of a chip loading slot is equivalent to the size of a wafer to be exposed;
step 2: etching the silicon wafer after photoetching is finished, and generating a wafer mounting clamping groove through the etching process; the diameter of the chip mounting clamping groove is controlled to be 5-10 mu m beyond the size of the wafer, and the depth of the clamping groove is within the range of +/-30 mu m of the thickness of the wafer;
and step 3: removing the photoresist on the silicon wafer, and cleaning; sequentially loading the wafers into the wafer loading clamping grooves;
and 4, step 4: carrying out a gluing process on the silicon wafer with the wafer, and baking;
and 5: projection exposure is carried out according to alignment marks on the silicon wafer, all wafers on the silicon wafer can be exposed at one time, the alignment deviation mainly comes from the wafer mounting deviation of 5-10 mu m and the alignment deviation within 1 mu m of a photoetching machine, and the requirement of the process on the alignment precision is better met.
The invention also provides a wafer carrier 10, a structural schematic diagram of one specific embodiment of which is shown in fig. 5 and is called as a second specific embodiment, wherein the surface of the wafer carrier 10 comprises a wafer loading clamping groove 11 and an alignment mark 12 coplanar with the wafer loading clamping groove 11;
the chip mounting clamping groove 11 is used for embedding a chip to be photoetched;
the alignment mark 12 is used as a positioning basis in the projection exposure process of the wafer to be photoetched.
In addition, the alignment mark 12 is disposed at the edge and the center of the wafer slide 10, so as to provide more alignment bases and improve the alignment accuracy; furthermore, the alignment mark 12 is a cross mark, and the cross mark not only can provide two-dimensional space positioning, but also can indicate the x direction and the y direction of the plane, i.e. provide coordinate system information, thereby further improving the lithography precision.
As a preferred embodiment, the difference between the size of the die-bonding card slot 11 and the size of the wafer to be lithographed is in a range of 5 microns to 10 microns, inclusive, such as any of 5.0 microns, 9.4 microns, or 10.0 microns; the difference between the depth of the wafer loading slot 11 and the thickness of the wafer to be photoetched ranges from 0 micron to 30 microns, including any one of end values such as 0.0 micron, 15.2 microns or 30.0 microns, of course, the difference between the depth of the wafer loading slot 11 and the thickness of the wafer to be photoetched can be positive or negative, that is, the upper surface of the wafer to be photoetched can be lower than the upper surface of the wafer carrier 10 or higher than the upper surface, and specific parameters can be changed according to actual conditions.
Furthermore, the wafer carrier 10 is an anti-corrosion carrier, which is used as a carrier of the wafer to be photoetched, and is soaked in the liquid medicine in the photoetching action, and is made of an anti-corrosion material, so that the wafer carrier 10 is not influenced by the liquid medicine, and is convenient for subsequent repeated utilization, and the production cost is obviously reduced; furthermore, the wafer carrier 10 is a silicon wafer, which has high yield and mature technology, and can further reduce the cost.
According to the wafer carrier 10 provided by the invention, the surface of the wafer carrier 10 comprises a chip loading clamping groove 11 and an alignment mark 12 coplanar with the chip loading clamping groove 11; the chip mounting clamping groove 11 is used for embedding a chip to be photoetched; the alignment mark 12 is used as a positioning basis in the projection exposure process of the wafer to be photoetched. In addition, the alignment mark 12 arranged on the wafer carrier 10 provides an alignment basis for the projection exposure step, a projection photoetching machine can be used for automatic alignment, and the alignment precision and the production efficiency of photoetching are greatly improved.
The invention also provides a photoetching tool which comprises the wafer carrier 10. According to the wafer carrier 10 provided by the invention, the surface of the wafer carrier 10 comprises a chip loading clamping groove 11 and an alignment mark 12 coplanar with the chip loading clamping groove 11; the chip mounting clamping groove 11 is used for embedding a chip to be photoetched; the alignment mark 12 is used as a positioning basis in the projection exposure process of the wafer to be photoetched. In addition, the alignment mark 12 arranged on the wafer carrier 10 provides an alignment basis for the projection exposure step, a projection photoetching machine can be used for automatic alignment, and the alignment precision and the production efficiency of photoetching are greatly improved.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
It is to be noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The photolithography method, the wafer carrier and the photolithography tool for the micro wafer provided by the invention are described in detail above. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (10)
1. A method of photolithography of a microwafer, comprising:
embedding the wafer to be photoetched on a wafer loading clamping groove of a wafer carrier; the wafer slide comprises an alignment mark coplanar with the wafer loading clamping groove;
gluing and baking the wafer to be photoetched;
carrying out projection exposure on the baked wafer to be photoetched according to the alignment mark;
and developing the exposed wafer to be photoetched to obtain the micro wafer with the graphical photoresist layer.
2. The method of claim 1, wherein the wafer carrier includes a plurality of the wafer loading slots;
correspondingly, the projection exposure of the baked wafer to be photoetched according to the alignment mark comprises the following steps:
and carrying out step-by-step projection exposure on the baked wafers to be photoetched according to the alignment marks.
3. A chip carrier is characterized in that the surface of the chip carrier comprises a chip loading clamping groove and an alignment mark coplanar with the chip loading clamping groove;
the chip mounting clamping groove is used for embedding a chip to be photoetched;
the alignment mark is used as a positioning basis in the projection exposure process of the wafer to be photoetched.
4. The wafer carrier as in claim 3, wherein the alignment marks are disposed at the edge and the center of the wafer carrier.
5. The wafer slide as recited in claim 3, wherein the alignment marks are cross marks.
6. The wafer slide as recited in claim 3, wherein the difference between the dimensions of the wafer loading pocket and the wafer to be lithographically printed is in a range from 5 microns to 10 microns, inclusive.
7. The wafer slide as recited in claim 3, wherein the difference between the depth of the loading pocket and the thickness of the wafer to be lithographically printed is in a range from 0 microns to 30 microns, inclusive.
8. The wafer carrier as in claim 3, wherein the wafer carrier is a corrosion resistant carrier.
9. The wafer carrier as recited in claim 8, wherein the wafer carrier is a silicon wafer.
10. A lithographic tool comprising a wafer carrier as claimed in any one of claims 3 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110295030.XA CN113064333A (en) | 2021-03-19 | 2021-03-19 | Photoetching method of tiny wafer, wafer carrier and photoetching tool |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110295030.XA CN113064333A (en) | 2021-03-19 | 2021-03-19 | Photoetching method of tiny wafer, wafer carrier and photoetching tool |
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| CN113064333A true CN113064333A (en) | 2021-07-02 |
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| CN202110295030.XA Pending CN113064333A (en) | 2021-03-19 | 2021-03-19 | Photoetching method of tiny wafer, wafer carrier and photoetching tool |
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| TW200939407A (en) * | 2008-03-13 | 2009-09-16 | Chipmos Technologies Inc | Multi-chip package structure and the method thereof |
| CN102130035A (en) * | 2009-12-30 | 2011-07-20 | 塔工程有限公司 | Integrated chip tray |
| US20120322174A1 (en) * | 2011-06-15 | 2012-12-20 | Eon-Jo Byun | Chip fixing apparatus and chip testing method using the same |
| CN103918074A (en) * | 2011-11-22 | 2014-07-09 | 德州仪器公司 | Micro surface mount device packaging |
| US20190333809A1 (en) * | 2017-01-17 | 2019-10-31 | Nepes Co., Ltd. | Method for producing semiconductor package |
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2021
- 2021-03-19 CN CN202110295030.XA patent/CN113064333A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200939407A (en) * | 2008-03-13 | 2009-09-16 | Chipmos Technologies Inc | Multi-chip package structure and the method thereof |
| CN102130035A (en) * | 2009-12-30 | 2011-07-20 | 塔工程有限公司 | Integrated chip tray |
| US20120322174A1 (en) * | 2011-06-15 | 2012-12-20 | Eon-Jo Byun | Chip fixing apparatus and chip testing method using the same |
| CN103918074A (en) * | 2011-11-22 | 2014-07-09 | 德州仪器公司 | Micro surface mount device packaging |
| US20190333809A1 (en) * | 2017-01-17 | 2019-10-31 | Nepes Co., Ltd. | Method for producing semiconductor package |
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