CN113060700B - High-precision nano-channel processing method based on graphene anisotropic etching principle and application thereof - Google Patents

High-precision nano-channel processing method based on graphene anisotropic etching principle and application thereof Download PDF

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CN113060700B
CN113060700B CN202110301444.9A CN202110301444A CN113060700B CN 113060700 B CN113060700 B CN 113060700B CN 202110301444 A CN202110301444 A CN 202110301444A CN 113060700 B CN113060700 B CN 113060700B
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CN113060700A (en
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王海东
周要洪
赵帅伊
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Tsinghua University
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Abstract

The invention discloses a high-precision nano-channel processing method based on a graphene anisotropic etching principle and application thereof. The method comprises the following steps: (1) Layer-by-layer formation of SiO on silicon substrate 2 Layers, single-layer graphene layers, and ribbon-like photoresist layers, wherein the shape and size control based on the nanochannel desired to be obtained: siO (SiO) 2 The thickness of the layer; the shape and size of the single graphene layer; the shape and size of the band-shaped photoresist layer; the position, shape and size of the overlapping area of the single-layer graphene layer and the strip-shaped photoresist layer; (2) Wet etching with hydrofluoric acid solution to eliminate SiO uncovered with the band photoresist layer on the silicon substrate 2 SiO of layer and overlap region 2 Layers to form nanochannels in the overlap region. The method is simple and convenient to operate, high in machining precision, controllable in three-dimensional size of the prepared nanochannel, good in uniformity, capable of being integrally formed, free of a bonding process, good in sealing performance and not prone to leakage when a fluid medium moves along the nanochannel.

Description

High-precision nano-channel processing method based on graphene anisotropic etching principle and application thereof
Technical Field
The invention belongs to the field of nano device research and development, and particularly relates to a nano channel high-precision processing method based on a graphene anisotropic etching principle and application thereof.
Background
The preparation technology of the three-dimensional micro/nano channel has wide application in various fields, such as heat dissipation of a high heat flux chip, single molecule detection, nano medicine research and development, microfluidic chips and the like. For the field of high heat flux heat dissipation, with the development of microelectronics industry and MEMS (MEMS: micro-electromechanical Systems) technology, the high heat flux density brought by the high integration of an electronic chip limits the further improvement of the chip performance, so how to realize the rapid and efficient heat dissipation of an electronic chip becomes a research hot spot, in many researches, the liquid cooling technology based on nanochannels is greatly focused, because the liquid cooling mode can provide larger heat dissipation capacity than the traditional air cooling mode (Schmidt, R, et al first International Conference on Microchannels and Minichannels, 2003.), meanwhile, people notice that different geometric shapes of nanochannels have different heat exchange effects, for example, for rectangular nanochannels (the nanochannels are rectangular in cross section along the length direction), and a larger aspect ratio can bring better heat exchange effect (Khan W A, et al Twory-Second Annual IEEE Semiconductor Thermal Measurement And Management Symphosium.IEEE, 2006.), so that in order to further explore the heat exchange effect of nanochannels with different geometric sizes and shapes, the preparation method of the nanochannels is particularly critical. For a single molecule detection technology based on a nano channel, the principle is that when a molecule to be detected passes through the nano channel, the change of the nano channel current in the process is monitored to analyze the information (M Tsutsui, et al scientific Reports, 2012.) of the structure of the molecule to be detected, the most important structure of the measuring device is the nano channel through which the molecule to be detected passes, and the uniformity (generally, the high uniformity along the length direction of the nano channel) and the tightness of the nano channel directly influence the signal to noise ratio of a detection signal, so that the development of an accurate and effective nano channel preparation technology has positive influence on the field. In the field of nano-drug research and development, people need to accurately deliver nano-drugs to affected parts, which is beneficial to rapid dissolution and absorption of drugs, and the use of nano-channels can realize accurate delivery of drugs and develop a nano-drug monitoring mechanism with higher specificity and sensitivity (Sprintz M, et al European Journal of Pain Supplements, 2011.). The nano channel technology has wide and important application prospect in the fields of nano drug development and accurate medical treatment. In addition, in recent years, intensive research has been conducted on flow and transport characteristics within nanoscale microchannels (Sofos F, et al microfluidics and nanofluidics, 2012.) different nanochannel interfaces, sizing, and effects in which specific electric double layer, superslip phenomena will affect ion transport and separation (Zhu Y, et al acs Nano, 2018.). In summary, developing a nano-channel preparation method which can precisely regulate and control the three-dimensional size of the nano-channel, has simple and convenient process and strong practicability is a key core technology of efficient heat dissipation, nano-medicine and nano-fluidic devices.
Currently, common nanochannel preparation methods include: direct bonding, high energy beam processing, nanoimprint lithography, and the like. The preparation of the nanochannel by the direct bonding method is generally divided into two steps, wherein the nanochannel is prepared by a reactive ion etching method (without a cover plate) in the first step, and the cover plate is bonded in the second step, and the cover plate can be made of glass, photoresist and other materials. The lateral dimensions of channels processed by the reactive ion etching method (Shaina a. Kelly, et al, lab on a chip, 2016.) are limited by the wavelength of UV (Ultraviolet Rays) light, the width of the channels is generally limited to the micrometer scale (Phan, et al, asme 2009 Second International Conference on Micro/Nanoscale Heat and Mass transfer.2009.), the method has severe requirements on the etching rate, the problem of uneven height of the nanochannels in the length direction is easily caused, and the problems of channel leakage, blockage and the like are easily caused in the bonding process of the second step. The nano-imprint lithography (NIL: nanoimprint lithography) is a preparation method combining nano-imprint with lithography, and the principle is as follows: a technique of patterning a micro-nano structure by imprinting a material to be processed using a mold containing the micro-nano structure with the aid of a polymer such as a photoresist (Chou, et al journal of vacuum science & technology B, 1996). The method generally comprises three steps: processing an imprinting template, transferring patterns, and processing a substrate, namely firstly processing a mold by means of etching and the like, then covering the surface of a material to be processed with a polymer such as photoresist and the like as a buffer layer, imprinting the mold on the surface of the material to be processed, causing mechanical deformation, then carrying out irradiation such as ultraviolet light and the like to solidify the mold, and finally removing the buffer layer to obtain the micro-nano structure material consistent with the mold structure. The high-energy beam processing method (high-energy beam refers to electron beam, proton beam, focused ion beam, femtosecond laser beam, etc.) uses direct irradiation of high-energy beam on material to make physical and chemical changes on the material, so as to manufacture nano channels (Choi S, et al applied Physics Letters, 2008.), and the method needs expensive processing equipment, is difficult to realize parallel processing of multiple nano channels, has high preparation cost and low efficiency, and also needs bonding cover plate after etching the channels.
Therefore, a simple and reliable nano-channel processing method is not available at present, and development of nano-channel related technology is limited.
Disclosure of Invention
The present application aims to solve at least one of the technical problems in the related art to some extent. Therefore, an object of the present application is to provide a high-precision nano-channel processing method based on the anisotropic etching principle of graphene and the application thereof. The method is simple and convenient to operate, high in machining precision, controllable in three-dimensional size of the prepared nanochannel, good in uniformity, capable of being integrally formed, free of a bonding process, good in sealing performance and not prone to leakage when a fluid medium moves along the nanochannel.
The present application is proposed based on the following findings of the inventors: the single-layer graphene can provide a high-speed transport channel for ions in a hydrofluoric acid solution, so that the chemical reaction rate at a graphene/silicon dioxide interface is obviously higher than that of a silicon dioxide interface without graphene coverage, the anisotropic etching characteristic is caused, silicon dioxide below a graphene layer is completely etched, etching surfaces are regular, and multiple experiments prove that the etching method is good in effect and has higher robustness.
To this end, according to a first aspect of the invention, the invention proposes a method of preparing nanochannels. According to an embodiment of the invention, the method comprises:
(1) Layer-by-layer formation of SiO on silicon substrate 2 Layers, single-layer graphene layers, and ribbon-like photoresist layers, wherein the shape and size control based on the nanochannel desired to be obtained:
the SiO is 2 The thickness of the layer;
the shape and size of the single graphene layer;
the shape and size of the ribbon photoresist layer;
the position, shape and size of the overlapping area of the single-layer graphene layer and the strip-shaped photoresist layer;
(2) Wet etching with hydrofluoric acid solution to eliminate SiO uncovered with the band photoresist layer on the silicon substrate 2 SiO of the layer and the overlap region 2 A layer to form nanochannels in the overlap region.
According to the method for preparing the nano channel, disclosed by the embodiment of the invention, the characteristic of anisotropically etching silicon dioxide when hydrofluoric acid is immersed in graphene is utilized, the preparation of the nano channel can be completed by only one-step wet etching, the operation is simple and convenient, and the processing precision is high. The height of the nano channel is determined by the thickness of the silicon dioxide layer etched by hydrofluoric acid, and the width and the length of the nano channel are determined by the overlapping area of the single-layer graphene layer and the strip photoresist layer; after wet etching, the photoresist layer forms a natural cover plate of the nano channel, and bonding is not needed to be carried out by additionally adding the cover plate, so that the problems of uneven channel depth, easiness in liquid leakage and blockage and the like caused by bonding of the cover plate in the existing nano channel preparation method can be effectively avoided, and the processing precision of the nano channel and the yield of the nano flow control chip are improved to a great extent; in addition, the method can design nano channel patterns with any shape according to requirements, greatly simplifies the design and processing process of nano channels, and has wide application prospects in the fields of high heat flux density chip heat dissipation, single molecule detection, nano drug research and development, microfluidic chips and the like. In conclusion, the method is simple and convenient to operate, high in machining precision, controllable in three-dimensional size of the prepared nanochannel, good in uniformity, capable of being integrally formed, free of a bonding process, good in sealing performance and not prone to leakage when a fluid medium moves along the nanochannel.
In addition, the method for preparing a nanochannel according to the above embodiment of the present invention may further have the following additional technical features:
in some embodiments of the present invention,at least one of the following conditions is satisfied: the SiO is 2 The thickness of the layer is uniform, the SiO 2 The thickness of the layer is 1-500 nm; the distance between the overlapping areas in the length direction and the width direction of the strip-shaped photoresist layer is respectively and independently 500 nm-10 mu m; the distance of the single-layer graphene layer in the width/length direction of the strip-shaped photoresist layer is not smaller than the width/length of the strip-shaped photoresist layer, and the distance of the single-layer graphene layer in the length/width direction of the strip-shaped photoresist layer is smaller than the length/width of the strip-shaped photoresist layer; the edges of the single-layer graphene layer and/or the ribbon-shaped photoresist layer respectively and independently comprise at least one selected from straight lines, curves, wavy lines or zigzag lines; the concentration of the hydrofluoric acid solution is 3-6wt%; the nanochannels are nanochannels with regular or irregular structures.
In some embodiments of the invention, step (1) further comprises at least one of: (1-1) subjecting the silicon substrate to thermal oxidation or chemical vapor deposition to form the SiO 2 A layer; (1-2) forming a single graphene layer on the copper foil by using a chemical vapor deposition method; forming a polymethyl methacrylate supporting layer on the single-layer graphene layer; removing the copper foil by adopting an etching method; transferring the single graphene layer to the SiO using the support layer 2 Removing the support layer from the layer; (1-3) controlling the shape and size of the ribbon-shaped photoresist layer using electron beam lithography, and/or controlling the shape and size of the single graphene layer using a photoresist layer and an oxygen plasma environment.
In some embodiments of the invention, step (1-3) further comprises: forming a first photoresist layer above the single-layer graphene layer, and developing the first photoresist layer into a first strip-shaped photoresist layer by using an electron beam lithography method; removing the graphene layer uncovered by the first strip photoresist by adopting an oxygen plasma environment so as to obtain a strip-shaped graphene layer; and removing the first strip-shaped photoresist layer, forming a second photoresist layer on the strip-shaped graphene layer, developing the second photoresist layer into the second strip-shaped photoresist layer by using an electron beam lithography method, and defining the position, the shape and the size of the nano channel by using the strip-shaped graphene layer and the second strip-shaped photoresist layer.
In some embodiments of the invention, at least one of the following conditions is met: the included angle between the second strip-shaped photoresist layer and the strip-shaped graphene layer is 1-90 degrees; the included angle between the second strip-shaped photoresist layer and the strip-shaped graphene layer is 45-90 degrees; the semiconductor device comprises one or more second strip-shaped photoresist layers, wherein the second strip-shaped photoresist layers are arranged at intervals in the length direction of the strip-shaped graphene layer and respectively and independently form an overlapping area with the strip-shaped graphene layer; edges of the ribbon-shaped graphene layer and/or the second ribbon-shaped photoresist layer each independently include at least one selected from a straight line, a curved line, a wavy line, or a meander line.
In some embodiments of the invention, at least one of the following conditions is met: the second strip-shaped photoresist layer is perpendicular to the strip-shaped graphene layer; the edges of the overlapping areas of the ribbon-shaped graphene layer and the second ribbon-shaped photoresist layer are all straight lines; the semiconductor device comprises a plurality of second strip-shaped photoresist layers, wherein the second strip-shaped photoresist layers and the strip-shaped graphene layers form a plurality of overlapping areas which are respectively spaced and have the same shape.
In some embodiments of the invention, there is provided: 1) SiO formation on silicon substrate 2 A layer; 2) Forming a single-layer graphene layer on the copper foil by using a chemical vapor deposition method; forming a polymethyl methacrylate supporting layer on the single-layer graphene layer; removing the copper foil by adopting an etching method; transferring the single graphene layer to the SiO using the support layer 2 Removing the support layer from the layer; 3) Forming a first photoresist layer above the single-layer graphene layer, and developing the first photoresist layer into a first strip-shaped photoresist layer by using an electron beam lithography method; removing the graphene layer which is not covered by the first strip photoresist layer by adopting an oxygen plasma environment so as to obtain a strip-shaped graphene layer; 4) Removing the first strip-shaped photoresist layer, forming a second photoresist layer on the strip-shaped graphene layer, developing the second photoresist layer into a second strip-shaped photoresist layer by using an electron beam lithography method, and using the strip-shaped graphene layer and the second strip-shaped lightThe photoresist layer defines the position, shape and size of the nano-channel; 5) And 4) placing the silicon substrate obtained in the step 4) in hydrofluoric acid solution for wet etching so as to form nano channels.
According to a second aspect of the invention, the invention proposes a nanochannel. According to an embodiment of the invention, the nanochannel is obtained by the method for preparing a nanochannel. Compared with the prior art, the nano channel has the advantages of high processing precision, controllable three-dimensional size, better uniformity, integrated forming, no need of a bonding process, better sealing performance and difficult liquid leakage when a fluid medium moves along the nano channel.
According to a third aspect of the present invention, the present invention proposes the use of the nanochannel and/or the preparation method described above in the fields of chip heat dissipation, single molecule detection, nano-drug development, microfluidic chips. Compared with the prior art, the nano channel and the method for preparing the nano channel are used in the fields of high heat flux density chip heat dissipation, single molecule detection, nano medicine research and development, microfluidic chips and the like, so that the problems of uneven channel depth, easiness in liquid leakage and blockage and the like caused by cover plate bonding in the existing nano channel preparation method can be effectively avoided, and the processing precision of the nano channel and the yield of products such as high-efficiency heat dissipation devices, nano medicines, nano fluidic chips and the like are greatly improved; in addition, the nano channel patterns with arbitrary shapes can be designed according to the requirements, so that the design and the processing process of the nano channel are greatly simplified, and the method has great advantages and wide application prospects.
According to a fourth aspect of the present invention, a nano-device is presented. According to an embodiment of the present invention, the nano device has the above-mentioned nano channel and/or the nano channel obtained by the above-mentioned preparation method. Compared with the prior art, the nano channel in the nano device has higher precision, better uniformity and sealing performance, is not easy to leak liquid when a fluid medium moves along the nano channel, and has more excellent product performance.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 is a flow chart of a method of preparing nanochannels according to one embodiment of the invention.
FIGS. 2-9 are process flow diagrams for preparing nanochannels in accordance with one embodiment of the invention, wherein FIG. 2 is a process flow diagram for forming SiO on a silicon substrate 2 Schematic diagrams of three-dimensional layered structures of layers and single-layer graphene layers; FIG. 3 is a schematic view of a three-dimensional layered structure in which a first photoresist layer is formed on a single graphene layer; FIG. 4 is a schematic diagram of a three-dimensional layered structure in which a first photoresist layer is developed into a first belt-like photoresist layer; FIG. 5 is a schematic view of a three-dimensional layered structure of a ribbon-shaped graphene layer obtained after a single-layer graphene layer is treated in an oxygen plasma environment; FIG. 6 is a schematic view of a three-dimensional layered structure with a first strip photoresist layer removed; FIG. 7 is a schematic view of a three-dimensional layered structure in which a second photoresist layer is formed on a ribbon-shaped graphene layer; FIG. 8 is a schematic diagram of a three-dimensional layered structure of developing a second photoresist layer into a second ribbon-like photoresist layer; fig. 9 is a schematic diagram of a three-dimensional structure of a nanochannel obtained after hydrofluoric acid etching.
Fig. 10 is a process flow diagram for preparing nanochannels according to yet another embodiment of the invention, wherein (a) in fig. 10 is a front view in the B direction and a side view in the a direction when a single graphene layer is transferred onto a silicon dioxide layer; fig. 10 (B) is a front view in the B direction and a side view in the a direction after forming a first band-shaped photoresist layer on a single graphene layer; fig. 10 (c) is a front view in the B direction and a side view in the a direction after removing the first band-shaped photoresist layer and forming a band-shaped graphene layer; fig. 10 (d) is a front view in the B direction and a side view in the a direction after forming a second band-shaped photoresist layer on the band-shaped graphene layer; fig. 10 (e) is a front view in the B direction and a side view in the a direction of the finished nanochannel product obtained by wet etching with a hydrofluoric acid solution.
Fig. 11 is a top view (image magnified by an optical microscope) of a finished nanochannel product prepared in accordance with one embodiment of the invention.
Reference numerals: 10-a silicon substrate; 20-SiO 2 A layer; 30-a monolayer graphene layer; 31-a ribbon graphene layer; 40-a band-shaped photoresist layer; 41-a first photoresist layer; 411-a first band-shaped photoresist layer; 42-a second photoresist layer; 421-a second band-shaped photoresist layer; 50-nanochannels; width of W-nanochannels; length of the L-nanochannel; height of H-nanochannels.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
In the description of the present invention, it should be understood that the terms "length," "width," "thickness," "upper," "lower," "front," "rear," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, and are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
According to a first aspect of the present invention, a method for preparing a nanochannel is provided, which is simple and convenient to operate, has high processing precision, and the prepared nanochannel has controllable three-dimensional size, can have good uniformity, can be integrally formed, does not need a bonding process, has good sealing performance, and is not easy to leak when a fluid medium moves along the nanochannel. The method of preparing nanochannels according to the above-described embodiment of the present invention will be described in detail with reference to fig. 1 to 11. According to an embodiment of the invention, the method comprises:
s100: layer-by-layer formation of SiO on silicon substrate 2 Layers, single-layer graphene layers, and ribbon-like photoresist layers, wherein the shape and size control based on the nanochannel desired to be obtained: siO (SiO) 2 The thickness of the layer; the shape and size of the single graphene layer; the shape and size of the band-shaped photoresist layer; position, shape and size of overlapping area of single-layer graphene layer and strip photoresist layer
According to an embodiment of the present invention, referring to fig. 8, siO may be formed layer by layer on a silicon substrate 10 2 Layer 20, single-layer graphene layer 30, and ribbon photoresist layer 40, the desired nanochannel is obtained by controlling the position, shape, and size of the overlapping region of single-layer graphene layer 30 and ribbon photoresist layer 40. As shown in FIG. 9, the height of the nanochannels 50 formed in the present invention can be defined by SiO etched with hydrofluoric acid 2 Layer thickness determination, referring to fig. 8 and 11, the shape, width W, and length L of the nanochannel may be determined by the overlap region of the single-layer graphene layer 30 and the ribbon-shaped photoresist layer 40; after wet etching, the photoresist layer 40 can form a natural cover plate of the nano channel, bonding is not needed to be carried out by adding the cover plate, the difficulties of uneven channel depth, easy liquid leakage and blockage and the like caused by bonding the cover plate in the existing nano channel preparation method can be effectively avoided, and the processing precision of the nano channel and the yield of the nano flow control chip are improved to a great extent.
According to a specific embodiment of the invention, in the invention SiO 2 The graphene layer formed on the layer 20 should be single-layer graphene, and the inventor finds that only single-layer graphene can better realize anisotropic etching, so that by forming the single-layer graphene layer, a high-speed transport channel can be provided for ions in the subsequent hydrofluoric acid etching process, the chemical reaction rate at a graphene/silicon dioxide interface is obviously higher than that of a silicon dioxide interface without graphene covering, anisotropic etching is realized, the shape and the size of a nano channel are more favorably controlled, and excessive occurrence of the boundary of the nano channel is avoided Etching conditions. The graphene layers in the present invention are all referred to as single-layer graphene layers. In addition, since the thickness of the single graphene layer is extremely small, the effect on the height H of the finally formed nanochannel is negligible.
According to one embodiment of the invention, siO with uniform thickness can be formed on a silicon substrate 2 Layer of SiO 2 The thickness of the layer determines the height of the finally formed nanochannels, siO 2 The uniformity of the thickness of the layer ensures the uniformity of the height of the nanochannels eventually formed. In the present invention, siO 2 The thickness of the layer is not particularly limited, and may be selected by those skilled in the art according to the intended use of the nanochannel to be obtained, the height, and the like, and preferably, siO 2 The thickness of the layer may be from a few nanometers to hundreds of nanometers, such as 1 to 500nm, for example, siO 2 The thickness of the layer may be 1nm, 10nm, 20nm, 30nm, 50nm, 80nm, 100nm, 150nm, 200nm, 300nm, 400nm or 500nm, etc., because if the thickness of the silicon dioxide layer is too large, the corresponding subsequent etching time is also long, and the geometry of the nanochannel may be affected due to the excessive etching time.
According to still another embodiment of the present invention, referring to fig. 8 and 9, the shape and size of the finally formed nanochannel may be controlled by controlling the shape and size of the overlapping region of the single-layer graphene layer and the ribbon-shaped photoresist layer, it should be noted that the shape and size of the overlapping region are not particularly limited, and those skilled in the art may select the shape and size according to the intended use, shape, size, etc. of the nanochannel to be obtained, so long as the nanochannel can be formed after hydrofluoric acid etching, for example, the distance between the overlapping region of the single-layer graphene layer 30 and the ribbon-shaped photoresist layer 40 in the length direction (e.g., the B direction in fig. 8) and the width direction (e.g., the a direction in fig. 8) of the ribbon-shaped photoresist layer may be several hundred nanometers to several micrometers, such as 500nm to 10 μm, and further for example, the length and width of the overlapping region may be 500nm, 600nm, 700nm, 800nm, 900nm, 1 μm, 3 μm, 5 μm, 7 μm, 9 μm, etc. respectively. Further toTo avoid SiO formation on both sides of the overlapping region or the nano-channels which cannot be formed due to incorrect position, shape and size of the overlapping region 2 Layers (SiO as shown at 21 and 22 in FIG. 9) 2 Layer) is also etched to prevent formation of SiO 2 In the case of the support layer and the nanochannels, the distance of the single-layer graphene layer 30 in the width/length direction of the band-shaped photoresist layer 40 may be made not smaller than the width/length of the band-shaped photoresist layer 40 and the distance in the length/width direction of the band-shaped photoresist layer 40 may be made smaller than the length/width of the band-shaped photoresist layer 40, for example, the distance of the single-layer graphene layer 30 in the width direction of the band-shaped photoresist layer 40 (direction a in fig. 8) may be made not smaller than the width of the band-shaped photoresist layer 40 and the distance in the length direction of the band-shaped photoresist layer 40 (direction B in fig. 8) may be made smaller than the length of the band-shaped photoresist layer 40, and more preferably, the single-layer graphene layer 30 may be made continuous in the width direction of the band-shaped photoresist layer 40.
According to still another embodiment of the present invention, the inventors found that the edge structures of the single-layer graphene layer 30 and the band-shaped photoresist layer 40 determine the edge structures of the overlapping region of the two and the edge structures of the nanochannels, and that the skilled person can control the edge structures of the single-layer graphene layer 30 and the band-shaped photoresist layer 40 according to the edge structures of the nanochannels that are expected to be obtained, for example, can make the edges of the single-layer graphene layer 30 and/or the band-shaped photoresist layer 40 independently include at least one selected from a straight line, a curved line, a wavy line, or a meander line, respectively, so as to obtain a nanochannel whose edge structure includes at least one selected from a straight line, an arc, a wave, a meander, or the like.
According to yet another embodiment of the present invention, siO is formed on a silicon substrate 2 The layer may comprise: thermal oxidation or chemical vapor deposition of a silicon substrate to form SiO 2 A layer in which SiO can be precisely controlled by changing the thermal oxidation time of the silicon substrate or controlling the parameter conditions of chemical vapor deposition 2 Thickness of the layer.
According to a further embodiment of the invention, in SiO 2 Forming the single-layer graphene layer 30 on the layer 20 may include: by chemical vapor depositionForming a single-layer graphene layer on the copper foil; forming a polymethyl methacrylate (PMMA) support layer on the single-layer graphene layer; removing the copper foil by adopting an etching method; transfer of a monolayer graphene layer to SiO with a support layer 2 The support layer is removed and the layer is over the layer. For example, a single-layer graphene can be prepared on a copper foil by a chemical vapor deposition method, then PMMA is spin-coated on the surface of the single-layer graphene as a supporting layer, then a copper etching solution is used for removing the copper foil substrate, and then the single-layer graphene is transferred onto a silicon substrate with a silicon dioxide layer with uniform thickness on the surface by the PMMA supporting layer, so that a layered structure shown in fig. 2 is obtained, and a front view in the B direction and a side view in the A direction of the layered structure are shown in fig. 10 (a).
According to an embodiment of the present invention, the shape and size of the band-shaped photoresist layer 40 may be controlled by using an electron beam lithography method, and/or the shape and size of the single-layer graphene layer 30 may be controlled by using a photoresist layer and an oxygen plasma environment, and in order to obtain a higher-precision nano-channel, the shape and size of the single-layer graphene layer 30 and the band-shaped photoresist layer 40 may be strictly controlled by using an electron beam lithography method and an oxygen plasma environment, so that the overlapping region of the two may be consistent with the nano-channel expected to be obtained. Specifically, referring to fig. 3 to 8 and 10, a first photoresist layer 41 (shown in fig. 3) may be formed in advance over the single graphene layer 30, and the first photoresist layer 41 may be developed into a first band-shaped photoresist layer 411 (shown in fig. 4) using an electron beam lithography method; removing the graphene layer uncovered by the first strip photoresist layer 411 by using an oxygen plasma environment so as to obtain a strip graphene layer 31 (as shown in fig. 5); thereafter, the first band-shaped photoresist layer 411 (shown in fig. 6) is removed and a second photoresist layer 42 (shown in fig. 7) is formed on the band-shaped graphene layer 31, the second photoresist layer 42 is developed into a second band-shaped photoresist layer 421 (shown in fig. 8) using an electron beam lithography method, and the position, shape and size of the nano-channels are defined using the band-shaped graphene layer 31 and the second band-shaped photoresist layer 421. Specifically:
As shown in fig. 2 to 6, a photoresist layer may be spin-coated over the single-layer graphene layer 30 (the model may be ZEP520, the photoresist may be the positive photoresist, the region exposed to ultraviolet rays will be dissolved in a developing solution), the photoresist is developed into a shape of a micrometer stripe by adopting an electron beam lithography technology, and then the graphene uncovered by the photoresist is etched to form a micrometer wide graphene stripe, where it should be pointed out that the width of the etched graphene stripe determines the width of the nanochannel (the width W as shown in (b) and (c) in fig. 10), so that the width of the nanochannel can be precisely controlled by changing the width of the photoresist that is not dissolved by the developing solution after exposure to ultraviolet rays in this step (the width of the etched graphene stripe); the photoresist is then removed and diced (the sample typically contains multiple repeating units prior to the dicing step) to give a layered structure as shown in fig. 6, which is shown in front view in the B-direction and in side view in the a-direction as shown in fig. 10 (c). Further, as shown in fig. 7 to 8, a photoresist may be spin-coated on the surface of the graphene ribbon of the layered structure shown in fig. 6, and the photoresist may be developed into a shape of a micrometer ribbon by using an electron beam lithography technique (for example, when the ribbon is in a vertical relationship with the overlapping area of the graphene ribbon, a cross-sectional view of the finally prepared nanochannel along the height direction is rectangular), where it should be pointed out that the width of the developed photoresist determines the length of the nanochannel (length L as shown in fig. 10 (d)), so that the length of the nanochannel may be precisely controlled by changing the width of the photoresist that is not dissolved by the developer after being exposed to ultraviolet rays in this step, to obtain the layered structure shown in fig. 8, and a front view thereof in the B direction and a side view thereof in the a direction are shown in fig. 10 (d).
According to still another embodiment of the present invention, the shape of the overlapping region of the photoresist layer and the graphene layer can be controlled by controlling the angle between the second strip-shaped photoresist layer 421 and the strip-shaped graphene layer 31, and it should be noted that, in the present invention, the angle between the second strip-shaped photoresist layer 421 and the strip-shaped graphene layer 31 is not particularly limited, and a person skilled in the art may select the angle according to actual needs, for example, the angle may be 1-90 degrees, specifically, may be 20 degrees, 30 degrees, 50 degrees, 60 degrees, 80 degrees, or 90 degrees, etc., and further, the angle may be 45-90 degrees, for example.
According to still another embodiment of the present invention, referring to fig. 8 and 11, one or more second band-shaped photoresist layers 421 may be included, wherein the plurality of second band-shaped photoresist layers 421 may be spaced apart in a length direction of the band-shaped graphene layers and respectively independently form overlapping regions with the band-shaped graphene layers, whereby a plurality of spaced-apart nano-channels may be simultaneously formed during a subsequent hydrofluoric acid etching process, as shown in fig. 11, two nano-channels 50 may be simultaneously formed.
According to yet another embodiment of the present invention, the edge structures of the ribbon graphene layer 31 and the second ribbon photoresist layer 421 determine the edge structures of the overlapping region of the two and the edge structures of the nanochannels, and a person skilled in the art may control the edge structures of the ribbon graphene layer 31 and the second ribbon photoresist layer 421 according to the edge structures of the nanochannels that are expected to be obtained, for example, the edges of the ribbon graphene layer and/or the second ribbon photoresist layer may be made to independently include at least one selected from a straight line, a curved line, a wavy line, or a meander line, respectively, so as to obtain a nanochannel whose edge structure includes at least one selected from a straight line, an arc, a wave, a meander, or the like.
According to another embodiment of the present invention, the nanochannel is different in use and different in shape, for example, when the nanochannel is used for high heat flux density heat dissipation of an electronic chip, a nanochannel with a rectangular geometry can be selected, and at this time, the second ribbon-shaped photoresist layer can be perpendicular to the ribbon-shaped graphene layer, and edges of overlapping areas of the ribbon-shaped graphene layer and the second ribbon-shaped photoresist layer are both straight lines, so as to obtain a rectangular overlapping area and a nanochannel; in addition, depending on the actual requirements of the application and the like, the overlapping region may be shaped like a trapezoid based on the fact that the second band-shaped photoresist layer is perpendicular to the band-shaped graphene layer and the edges of the overlapping region are all straight lines. Further, the semiconductor device includes a plurality of second strip-shaped photoresist layers 421, and the plurality of second strip-shaped photoresist layers 421 and the strip-shaped graphene layers 31 form a plurality of overlapping regions with the same shape and the respective intervals, so that a plurality of nano channels with the same three-dimensional size and the same interval distribution can be formed simultaneously through subsequent etching.
S200: by usingWet etching with hydrofluoric acid solution to eliminate SiO uncovered with band photoresist layer on silicon substrate 2 SiO of layer and overlap region 2 A layer forming nanochannels in the overlap region
According to an embodiment of the invention, referring to fig. 8 and 9, when wet etching is performed using a hydrofluoric acid solution, the SiO on the silicon substrate is not covered by the strip photoresist layer 2 SiO of overlapping area of layer and graphene layer under photoresist layer 2 The layers are removed and only the areas 21 and 22 under the photoresist layer where no graphene layer is formed remain with SiO 2 Layer, siO remaining on both sides of the overlap region 2 The layer serves as a support region for the nanochannels and photoresist cover plate. The nano channel prepared by the method is integrally formed, namely, the photoresist above the graphene forms a natural closed cover plate of the nano channel, and the photoresist/graphene interface is firmly bonded, so that bonding between the cover plate and a channel substrate is not needed, namely, the photoresist layer and a channel formed by etching below form a complete closed nano channel, the tightness is good, and the problems of uneven channel depth, easiness in liquid leakage, blockage and the like caused by bonding of the cover plate in the traditional nano channel preparation method can be effectively avoided.
According to one embodiment of the present invention, the concentration of the hydrofluoric acid solution and the etching time are not particularly limited, and may be selected according to practical needs by a person skilled in the art, for example, the concentration of the hydrofluoric acid solution and the etching time may be determined according to the size of the nano channel to be obtained, and further, for example, the concentration of the hydrofluoric acid solution may be 3 to 6wt%, specifically 3wt%, 3.5wt%, 4wt%, 4.5wt%, 5wt%, 5.5wt%, or 6wt%, etc., and the etching time may be 1 to 60 minutes, specifically 5 minutes, 10 minutes, 15 minutes, 30 minutes, etc.
According to yet another embodiment of the present invention, the nanochannels finally formed in the present invention may be nanochannels with regular or irregular structures, for example, the nanochannels may be rectangular, trapezoidal, S-shaped, drum-shaped, etc. in plan view, and may be selected by those skilled in the art according to actual needs.
According to another embodiment of the present invention, a hydrofluoric acid wet etching method may be used to etch the silicon dioxide layer exposed in the surface (the portion not covered by the photoresist strip) and the silicon dioxide layer under the graphene strip in the layered structure as shown in fig. 8, and it should be noted that the successful implementation of this step is based on the characteristic of anisotropically etching silicon dioxide in hydrofluoric acid, where the anisotropic principle is that the graphene strip provides a high-speed transport channel for ions in the hydrofluoric acid solution, resulting in a significantly higher chemical reaction rate at the graphene/silicon dioxide interface than at the silicon dioxide interface without the graphene, so that the silicon dioxide layer under the graphene will be completely etched, the silicon dioxide layer under the photoresist not covered by the graphene is hardly etched, and in addition, the photoresist layer above the graphene is preserved intact, and at this time, it may be noted that the photoresist layer already forms a natural closed cover plate and forms a complete closed nano-channel with the channel formed by the etching. It should also be noted here that the thickness of the etched silicon dioxide layer determines the height of the nanochannels, so that the height of the nanochannels can be precisely controlled by varying the thickness of the silicon dioxide layer. Finally, the nano-channel structure is exposed to an oxygen plasma environment to etch redundant graphene strips at two ends of the nano-channel, so that the nano-channel structure shown in fig. 9 is obtained, and a front view in the direction B and a side view in the direction A are shown in fig. 10 (e).
According to yet another embodiment of the present invention, a method of preparing a nanochannel may comprise: 1) SiO formation on silicon substrate 2 A layer; 2) Forming a single-layer graphene layer on the copper foil by using a chemical vapor deposition method; forming a polymethyl methacrylate supporting layer on the single-layer graphene layer; removing the copper foil by adopting an etching method; transfer of a monolayer graphene layer to SiO with a support layer 2 Removing the support layer from the layer; 3) Forming a first photoresist layer above the single-layer graphene layer, and developing the first photoresist layer into a first strip-shaped photoresist layer by using an electron beam lithography method; removing the graphene layer which is not covered by the first strip photoresist by adopting an oxygen plasma environment so as to obtain a strip-shaped graphene layer; 4) Removing the first strip photoresist layer and forming a second photoresist on the strip graphene layerDeveloping the second photoresist layer into a second strip photoresist layer by using an electron beam lithography method, and defining the position, shape and size of the nano channel by using the strip graphene layer and the second strip photoresist layer; 5) And 4) placing the silicon substrate obtained in the step 4) in hydrofluoric acid solution for wet etching so as to form nano channels.
In summary, the method for preparing a nanochannel according to the above embodiment of the present invention has at least the following advantages: 1) The preparation of the nano channel can be completed by utilizing the characteristic of anisotropically etching silicon dioxide when hydrofluoric acid is immersed in graphene and only one-step wet etching, and the preparation method is simple and convenient to operate and high in processing precision; 2) The three-dimensional size of the nano channel can be accurately regulated and controlled, wherein the height of the nano channel is determined by the thickness of the silicon dioxide layer etched by hydrofluoric acid, and the width and the length of the nano channel are determined by the overlapping area of the single-layer graphene layer and the strip photoresist layer; 3) After wet etching, the photoresist layer forms a natural cover plate of the nano channel, the photoresist/graphene interface is firmly bonded, the cover plate is not required to be additionally arranged for bonding, the sealing performance is good, the problems of uneven channel depth, easiness in liquid leakage and blockage and the like caused by cover plate bonding in the existing nano channel preparation method can be effectively avoided, and the processing precision of the nano channel and the yield of the nano flow control chip are improved to a great extent; 4) The method can design nano channel patterns with arbitrary shapes according to requirements, greatly simplifies the design and processing process of nano channels, and has wide application prospects in the fields of high heat flux density chip heat dissipation, single molecule detection, nano drug research and development, microfluidic chips and the like. In conclusion, the method is simple and convenient to operate, high in machining precision, controllable in three-dimensional size of the prepared nanochannel, good in uniformity, capable of being integrally formed, free of a bonding process, good in sealing performance and not prone to leakage when a fluid medium moves along the nanochannel.
According to a second aspect of the invention, the invention proposes a nanochannel. According to an embodiment of the invention, the nanochannel is obtained by the method for preparing a nanochannel. Compared with the prior art, the nano channel has the advantages of high processing precision, controllable three-dimensional size, better uniformity, integrated forming, no need of a bonding process, better sealing performance and difficult liquid leakage when a fluid medium moves along the nano channel. It should be noted that the features and effects described in the above method for preparing a nanochannel are also applicable to the nanochannel, and are not described in detail herein.
According to a third aspect of the present invention, the present invention proposes the use of the nanochannel and/or the preparation method described above in the fields of chip heat dissipation, single molecule detection, nano-drug development, microfluidic chips. Compared with the prior art, the nano channel and the method for preparing the nano channel are used in the fields of high heat flux density chip heat dissipation, single molecule detection, nano medicine research and development, microfluidic chips and the like, so that the problems of uneven channel depth, easiness in liquid leakage and blockage and the like caused by cover plate bonding in the existing nano channel preparation method can be effectively avoided, and the processing precision of the nano channel and the yield of products such as high-efficiency heat dissipation devices, nano medicines, nano fluidic chips and the like are greatly improved; in addition, the nano channel patterns with arbitrary shapes can be designed according to the requirements, so that the design and the processing process of the nano channel are greatly simplified, and the method has great advantages and wide application prospects. It should be noted that the features and effects described in the above nanochannel and the method for preparing the nanochannel are also applicable to the application, and are not described in detail herein.
According to a fourth aspect of the present invention, a nano-device is presented. According to an embodiment of the present invention, the nano device has the above-mentioned nano channel and/or the nano channel obtained by the above-mentioned preparation method. Compared with the prior art, the nano channel in the nano device has higher precision, better uniformity and sealing performance, is not easy to leak liquid when a fluid medium moves along the nano channel, and has more excellent product performance. It should be noted that the type of the nano device is not particularly limited, and those skilled in the art may select the nano device according to actual needs, for example, the nano device may be a chip, a biosensor, a nanofluidic device, etc. In addition, it should be further noted that the features and effects described with respect to the nanochannel and the method for preparing the nanochannel are also applicable to the nanochannel device, and are not described in detail herein.
The scheme of the present invention will be explained below with reference to examples. It will be appreciated by those skilled in the art that the following examples are illustrative of the present invention and should not be construed as limiting the scope of the invention. The examples are not to be construed as limiting the specific techniques or conditions described in the literature in this field or as per the specifications of the product. The reagents or apparatus used were conventional products commercially available without the manufacturer's attention.
Example 1
(1) Preparing single-layer graphene on a copper foil by adopting a traditional chemical vapor deposition method, spin-coating PMMA (PMMA: polymethyl methacrylate, polymethyl methacrylate, a high molecular polymer) on the surface of the single-layer graphene as a supporting layer (for transferring graphene), removing a copper foil substrate by using a copper etching solution (wherein the etching solution is a mixed solution of copper sulfate, hydrochloric acid and water, and the concentrations of the copper sulfate and the hydrochloric acid are 0.5 mol/L), and transferring the single-layer graphene onto a silicon substrate with a silicon dioxide layer with uniform thickness on the surface, wherein the thickness of the silicon dioxide layer is 100nm, and the whole silicon wafer is 10mm multiplied by 10mm square; a chip 1 is obtained as shown in fig. 10 (a).
(2) Then spin coating a photoresist layer with the thickness of 300nm (model: ZEP520, the photoresist layer below is positive photoresist, the area exposed by ultraviolet rays is dissolved in developing solution), the spin coating rotating speed is 6000 rpm, and the spin coating time is about 40 seconds; developing the photoresist into a shape of a micrometer stripe after ultraviolet exposure by adopting an electron beam lithography technology, wherein the electron beam exposure equipment model in the process is JBX-6300FS, the exposure current is 2000pA, the size of an exposure area is 500 mu m multiplied by 500 mu m, the exposure time is about 1.5 minutes, and then the photoresist in the exposure area needs to be dissolved by a special developing solution (model: ZED-N50), so as to form a micrometer wide photoresist stripe, as shown in (b) in fig. 10; and then exposing the graphene which is not covered by the photoresist to an oxygen plasma environment, and etching away the graphene, so as to form a micrometer-wide graphene strip, wherein it is pointed out that the width W of the etched graphene strip determines the width of the nano channel. Thereafter, the photoresist is removed and diced to obtain chips 2, as shown in fig. 10 (c).
(3) Spin-coating photoresist on the surface of the graphene strip of the chip 2, and then continuing to develop the photoresist into a micrometer strip shape by adopting an electron beam lithography technology, referring to fig. 8, when the strip pattern is in a vertical relationship with the strip pattern in the step (2), the cross section of the finally prepared nano channel along the height direction is rectangular, and it is pointed out that the width of the developed photoresist determines the length L of the nano channel, and the relevant parameters of the step are consistent with those of the step (2). A chip 3 is obtained as shown in fig. 10 (d).
(4) Etching the silicon dioxide layer exposed on the surface of the chip 3 (the part not covered by the photoresist strip) and the silicon dioxide layer below the graphene strip by adopting a hydrofluoric acid wet etching method, wherein the concentration of hydrofluoric acid used in the process is 4.5wt%, and immersing etching is required for 10 minutes; after etching, the silicon dioxide layer which is not covered by the photoresist and the silicon dioxide layer below the graphene are completely etched, the silicon dioxide layer which is not covered by the graphene below the photoresist is hardly etched, in addition, the photoresist layer above the single-layer graphene is well preserved in the process, the photoresist layer forms a natural closed cover plate, and a complete closed nano channel is formed by the photoresist layer and a channel formed by etching below the photoresist layer. It is also noted here that the thickness of the etched silicon dioxide layer determines the height of the nanochannels. Finally, the wafer is exposed to an oxygen plasma environment to etch off redundant graphene strips at two ends of the nano channel, so as to obtain a chip 4, as shown in (e) of fig. 10. And after the etching process is finished, cleaning the chip by using deionized water, and drying by using dry nitrogen after the cleaning is finished, so that a final nano-channel sample can be obtained.
The image of the final sample obtained by the embodiment after being amplified by the optical microscope is shown in fig. 11, the upper and lower framed areas in the image are two nano channels which are successfully prepared, and the uniformity of the nano channels prepared by the method is good; the leak tightness of the nano channel is also good through the test.
It should be noted that, the present invention is not limited to the above specific embodiments, and the nano-channel high-precision processing method based on the anisotropic etching principle of graphene provided by the present invention can be widely applied to the field and other fields related thereto, and can be implemented by adopting other specific embodiments, for example, by combining with other preparation processes to further improve the processing precision, etc., so that, in the design concept of the present invention, the nano-channel preparation is performed by making some simple changes, modifications or mashing designs, which all fall within the scope of the present invention.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.

Claims (11)

1. A method of preparing a nanochannel comprising:
(1) Layer-by-layer formation of SiO on silicon substrate 2 Layers, single-layer graphene layers, and ribbon-like photoresist layers, wherein the shape and size control based on the nanochannel desired to be obtained:
the SiO is 2 The thickness of the layer;
the shape and size of the single graphene layer;
the shape and size of the ribbon photoresist layer;
the position, shape and size of the overlapping area of the single-layer graphene layer and the strip-shaped photoresist layer;
(2) Wet etching with hydrofluoric acid solution to eliminate SiO uncovered with the band photoresist layer on the silicon substrate 2 SiO of the layer and the overlap region 2 A layer to form nanochannels in the overlap region,
wherein: the SiO is 2 The thickness of the layer is uniform, the SiO 2 The thickness of the layer is 1-500 nm;
the distance between the overlapping area in the length direction and the width direction of the strip-shaped photoresist layer is 500 nm-10 mu m respectively and independently;
The distance of the single-layer graphene layer in the width direction of the strip-shaped photoresist layer is not smaller than the width of the strip-shaped photoresist layer, the distance of the single-layer graphene layer in the length direction of the strip-shaped photoresist layer is smaller than the length of the strip-shaped photoresist layer, and the single-layer graphene layer is continuous in the width direction of the strip-shaped photoresist layer;
the concentration of the hydrofluoric acid solution is 3-6wt%.
2. The method of claim 1, wherein at least one of the following conditions is satisfied:
the edges of the single-layer graphene layer and/or the strip-shaped photoresist layer respectively and independently comprise at least one selected from straight lines, curves and zigzag lines;
the nanochannels are nanochannels with regular or irregular structures.
3. The method according to any one of claims 1 or 2, wherein step (1) further comprises at least one of:
(1-1) subjecting the silicon substrate to thermal oxidation or chemical vapor deposition to form the SiO 2 A layer;
(1-2) forming a single graphene layer on the copper foil by using a chemical vapor deposition method; on the single-layer graphene layerForming a polymethyl methacrylate supporting layer; removing the copper foil by adopting an etching method; transferring the single graphene layer to the SiO using the support layer 2 Removing the support layer from the layer;
(1-3) controlling the shape and size of the ribbon-shaped photoresist layer using electron beam lithography, and/or controlling the shape and size of the single graphene layer using a photoresist layer and an oxygen plasma environment.
4. A method according to claim 3, wherein step (1-3) further comprises:
forming a first photoresist layer above the single-layer graphene layer, and developing the first photoresist layer into a first strip-shaped photoresist layer by using an electron beam lithography method; removing the graphene layer which is not covered by the first strip photoresist layer by adopting an oxygen plasma environment so as to obtain a strip-shaped graphene layer;
and removing the first strip-shaped photoresist layer, forming a second photoresist layer on the strip-shaped graphene layer, developing the second photoresist layer into the second strip-shaped photoresist layer by using an electron beam lithography method, and defining the position, the shape and the size of the nano channel by using the strip-shaped graphene layer and the second strip-shaped photoresist layer.
5. The method of claim 4, wherein at least one of the following conditions is satisfied:
the included angle between the second strip-shaped photoresist layer and the strip-shaped graphene layer is 1-90 degrees;
The semiconductor device comprises one or more second strip-shaped photoresist layers, wherein the second strip-shaped photoresist layers are arranged at intervals in the length direction of the strip-shaped graphene layer and respectively and independently form an overlapping area with the strip-shaped graphene layer;
the edges of the ribbon-shaped graphene layer and/or the second ribbon-shaped photoresist layer respectively and independently comprise at least one selected from straight lines, curved lines and zigzag lines.
6. The method of claim 5, wherein the second ribbon photoresist layer has an included angle of 45-90 degrees with the ribbon graphene layer.
7. The method of claim 5, wherein at least one of the following conditions is satisfied:
the second strip-shaped photoresist layer is perpendicular to the strip-shaped graphene layer;
the edges of the overlapping areas of the ribbon-shaped graphene layer and the second ribbon-shaped photoresist layer are all straight lines;
the semiconductor device comprises a plurality of second strip-shaped photoresist layers, wherein the second strip-shaped photoresist layers and the strip-shaped graphene layers form a plurality of overlapping areas which are respectively spaced and have the same shape.
8. The method according to any one of claims 4 to 7, comprising:
1) SiO formation on silicon substrate 2 A layer;
2) Forming a single-layer graphene layer on the copper foil by using a chemical vapor deposition method; forming a polymethyl methacrylate supporting layer on the single-layer graphene layer; removing the copper foil by adopting an etching method; transferring the single graphene layer to the SiO using the support layer 2 Removing the support layer from the layer;
3) Forming a first photoresist layer above the single-layer graphene layer, and developing the first photoresist layer into a first strip-shaped photoresist layer by using an electron beam lithography method; removing the graphene layer uncovered by the first strip photoresist by adopting an oxygen plasma environment so as to obtain a strip-shaped graphene layer;
4) Removing the first strip-shaped photoresist layer and forming a second photoresist layer on the strip-shaped graphene layer, developing the second photoresist layer into a second strip-shaped photoresist layer by using an electron beam lithography method, and defining the position, the shape and the size of a nano channel by using the strip-shaped graphene layer and the second strip-shaped photoresist layer;
5) And 4) placing the silicon substrate obtained in the step 4) in hydrofluoric acid solution for wet etching so as to form nano channels.
9. A nanochannel obtained by the method of any one of claims 1 to 8.
10. Use of the nanochannel of claim 9 and/or the method of any one of claims 1 to 8 in the fields of chip heat dissipation, single molecule detection, nano-drug development, microfluidic chips.
11. A nano-device characterized in that it has a nano-channel according to claim 9 and/or a nano-channel obtained by the method according to any one of claims 1 to 8.
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