CN113054860A

CN113054860A - Inversion system

Info

Publication number: CN113054860A
Application number: CN201911369448.XA
Authority: CN
Inventors: 黄伟; 张飞; 孙嘉品; 尹雪芹; 曹虎
Original assignee: BYD Co Ltd
Current assignee: BYD Co Ltd
Priority date: 2019-12-26
Filing date: 2019-12-26
Publication date: 2021-06-29
Anticipated expiration: 2039-12-26
Also published as: CN113054860B

Abstract

The present invention provides an inverter system comprising: the power supply part, the inverter circuit and the filter circuit; the inverter circuit comprises a first bridge arm and a second bridge arm, wherein the first bridge arm is provided with a first output end, and the second bridge arm is provided with a second output end; the first bridge arm comprises a first switch, a fifth switch and a third switch; the second bridge arm comprises a second switch and a fourth switch; the inverter system further comprises a sixth switch; in the last half period, the first switch is in a closed state in a partial period, high-frequency modulation is adopted in the partial period, the fifth switch is in an open state, high-frequency modulation is adopted in the fourth switch, in the next half period, the sixth switch is in an open state, high-frequency modulation is adopted in the second switch, the third switch is in a closed state in the partial period, and high-frequency modulation is adopted in the partial period. The loss and the harmonic content of an inverter system are reduced, the loss and the heating of devices are effectively balanced, and the over-high temperature of local devices is prevented.

Description

Inversion system

Technical Field

The present disclosure relates to inverter circuits, and particularly to an inverter circuit.

Background

The inverter is a key component for converting direct current electric energy (batteries and storage batteries) into alternating current (generally 220V,50Hz sine wave). The multifunctional grinding wheel is widely applied to systems such as automobiles, air conditioners, home theaters, electric grinding wheels, electric tools, sewing machines, DVDs, VCDs, computers, televisions, washing machines, smoke exhaust ventilators, refrigerators, video recorders, massagers, fans, lighting and the like. Especially in charge and discharge systems. The performance of the inverter will directly affect the stability, reliability, efficiency and cost of the whole system.

The inverter in the prior art usually has a high requirement on the inductance of the rear-end filter inductor, so that the loss of the inductor is high, and meanwhile, the switching loss on the switching tube is high.

In some multi-level schemes adopted to solve the above problems, the improvement of efficiency is limited because the number of devices in the control loop is large and the conduction loss is increased.

Disclosure of Invention

The present invention has been made to solve the above problems. The present invention provides an inverter system, and more details will be described in the following detailed description with reference to the accompanying drawings.

The present invention provides an inverter system comprising: the power supply part, the inverter circuit and the filter circuit; the inverter circuit comprises a first bridge arm and a second bridge arm, wherein the first bridge arm is provided with a first output end, and the second bridge arm is provided with a second output end; the first bridge arm comprises a first switch, a fifth switch and a third switch; the second bridge arm comprises a second switch and a fourth switch; the inverter system further comprises a sixth switch; one end of the sixth switch is arranged between the fifth switch and the third switch, and the other end of the sixth switch is arranged between the second switch and the fourth switch; in the last half period, the first switch is in a closed state in a partial period, high-frequency modulation is adopted in the partial period, the fifth switch is in an open state, high-frequency modulation is adopted in the fourth switch, in the next half period, the sixth switch is in an open state, high-frequency modulation is adopted in the second switch, the third switch is in a closed state in the partial period, and high-frequency modulation is adopted in the partial period.

In one embodiment of the invention, the power supply section comprises a direct current power supply and a first capacitor and/or a second capacitor.

In one embodiment of the invention, the filter circuit comprises a first and/or a second inductance and a third capacitance, the third capacitance being connected in parallel with the load.

In an embodiment of the invention, the first output terminal and the second output terminal are respectively connected to two ends of the filter circuit.

In one embodiment of the present invention, the inverter circuit further includes a first diode, a second diode, a third diode and a fourth diode, the first diode is connected to the first capacitor and the common terminal of the first switch and the fifth switch, the second diode is connected to the sixth switch and the second capacitor, the third diode is connected to the common terminal of the first switch and the fifth switch and the common terminal of the second switch and the fourth switch, and the fourth diode is connected to the common terminal of the second switch and the fourth switch and the sixth switch.

In one embodiment of the present invention,

when omega is more than 0 and less than 30 degrees, the fifth switch is continuously conducted, and the fourth switch is subjected to high-frequency modulation; when the fourth switch is switched on, the current passes through the first diode, the fifth switch, the first inductor, the second inductor and the fourth switch to form a loop, the second capacitor discharges, and the first capacitor charges; when the fourth switch is turned off, the load current passes through the first inductor, the second inductor, the third diode and the fifth switch to form a loop;

when the angle is more than 30 degrees and less than omega and less than 150 degrees, the fifth switch is continuously conducted, and the first switch and the fourth switch are synchronously modulated at high frequency; when the first switch and the fourth switch are switched on, the load current passes through the first switch, the fifth switch, the first inductor, the second inductor and the fourth switch to form a loop; when the first switch and the fourth switch are turned off, the load current passes through the first inductor, the second inductor, the third diode and the fifth switch to form a loop;

when the angle is more than 150 degrees and less than omega and less than 180 degrees, repeating the working process of more than 0 and less than omega and less than 30 degrees; the fifth switch is continuously conducted, and the fourth switch is subjected to high-frequency modulation; when the fourth switch is switched on, the current passes through the first diode, the fifth switch, the first inductor, the second inductor and the fourth switch to form a loop, the second capacitor discharges, and the first capacitor charges; when the fourth switch is turned off, the load current passes through the first inductor, the second inductor, the third diode and the fifth switch to form a loop;

when the angle is more than 180 degrees and less than omega and less than 210 degrees, the sixth switch is continuously conducted, and the second switch is modulated in high frequency; when the second switch is switched on, the current forms a loop through the second switch, the second inductor, the first inductor, the sixth switch and the second diode, the first capacitor discharges, and the second capacitor charges; when the second switch is turned off, current passes through the second inductor, the first inductor, the sixth switch and the fourth diode to form a freewheeling loop;

when the angle is 210 degrees < omega < 330 degrees, the sixth switch is continuously conducted, and the second switch and the third switch are synchronously modulated in high frequency; when the second switch and the third switch are switched on, the load current passes through the second switch, the second inductor, the first inductor and the third switch to form a loop; when the second switch and the third switch are turned off, the load current forms a freewheeling loop through the second inductor, the first inductor, the sixth switch and the fourth diode;

when the angle is more than 330 degrees and less than omega and less than 360 degrees, repeating the working process of more than 180 degrees and less than omega and less than 210 degrees; the sixth switch is continuously conducted, the second switch is subjected to high-frequency modulation, when the second switch is turned on, current passes through the second switch, the second inductor, the first inductor, the sixth switch and the second diode to form a loop, the first capacitor discharges, and the second capacitor charges; when the second switch is turned off, the current forms a freewheeling loop through the second inductor, the first inductor, the sixth switch and the fourth diode.

According to the embodiment of the invention, the multi-level pulse chopping is introduced, so that the switching loss of the switching tube is reduced, the inductance of the filter inductor can be effectively reduced, the loss and the size of the inductor can be reduced, the number of main current loop devices is small, the conduction loss of the switching device can be effectively reduced, the half-cycle separation of the current loop is realized, the loss and the heating of the device are effectively balanced, and the over-high temperature of a local device is prevented.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail embodiments of the present invention with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings, like reference numbers generally represent like parts or steps.

FIG. 1 shows a schematic diagram of a single-phase full-bridge inverter topology;

FIG. 2 shows a schematic diagram of a multilevel inversion topology;

FIG. 3 shows a schematic diagram of an inversion topology according to an embodiment of the invention;

FIG. 4 is a schematic diagram illustrating the flow of the opening current at 0 < ω < 30 for an inversion topology according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a freewheeling loop with an inversion topology according to an embodiment of the present invention at 0 < ω <180 °;

FIG. 6 is a schematic diagram illustrating the flow of the turn-on current at 30 ° < ω < 150 ° for an inversion topology according to an embodiment of the present invention;

FIG. 7 shows a schematic diagram of the flow of the turn-on current at 180 < ω < 210 for an inversion topology according to an embodiment of the present invention;

FIG. 8 shows a freewheeling loop diagram for an inversion topology at 180 < ω < 360 in accordance with an embodiment of the present invention;

FIG. 9 is a schematic diagram illustrating the flow of the on current at 210 < ω < 330 for an inversion topology according to an embodiment of the present invention; and

FIG. 10 illustrates a topology control timing diagram in accordance with an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, exemplary embodiments according to the present invention will be described in detail below with reference to the accompanying drawings. It is to be understood that the described embodiments are merely a subset of embodiments of the invention and not all embodiments of the invention, with the understanding that the invention is not limited to the example embodiments described herein. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the invention described herein without inventive step, shall fall within the scope of protection of the invention.

The pulse chopping is that in the process of alternating current inversion, direct current is adjusted in high frequency through a switching tube, generated SPWM pulse chopping is conducted, namely the voltage of UAB, and the frequency of the pulse chopping is the control frequency.

First, a schematic diagram of an inversion topology described with reference to fig. 1 and 2, wherein fig. 1 shows a schematic diagram of a single-phase full-bridge inversion topology; fig. 2 shows a schematic diagram of a multilevel inversion topology.

As shown in fig. 1, a topological diagram of a single-phase full-bridge inverter system is shown, wherein Q1 and Q3 form a pair of bridge arms, Q2 and Q4 form another pair of bridge arms, a pair of opposite control pulses are applied to the bases Q1 and Q2, the control pulse phases of the bases Q3 and Q4 are also opposite, and the control pulse phase of the base Q3 lags behind Q1 by an angle θ, where θ < 0 ° < θ <180 °.

The circuit operation is explained as follows:

during the period from 0 to t1, the base control pulses of Q1 and Q4 are all at high level, Q1 and Q4 are both turned on, point a is connected to the positive terminal of the power source Ud through Q1, point B is connected to the negative terminal of the power source Ud through Q4, so the voltage U across A, B is equal to the power source terminal voltage Ud in magnitude and positive right and left (positive) in polarity, and the direction of the flowing current is: ud + → Q1 → L1, L2 → Q4 → Ud-.

As can be seen, in the period from 0 to t1, the upper arm Q1 of the first arm and the lower arm Q4 of the second arm are electrically connected to form a current.

In the period from t1 to t2, the base control pulses of Q2 and Q3 are both high level, and in the beginning of the period, Q1 is cut off because the base becomes low level, the electromotive force of L is changed to charge the DC side capacitor C1 through a diode at the end of Q3 and a diode at Q2, and the charging current path is as follows: l2 → diode at Q2 → C1 → diode at Q3 → L1, and Q2 and Q3 are turned on to make Q2 and Q3 not conductive, point a is connected to the negative terminal of power supply Ud through the diode at Q3, point B is connected to the positive terminal of power supply Ud through the diode at Q3, so voltage U at A, B is equal to Ud, the polarity is positive (negative) from left to right, when electromotive force on L1 and L2 is reduced to equal to Ud, C cannot be charged continuously, the diode at Q2 and the diode at Q3 are turned off, Q2 and Q3 are turned on immediately, current flows through L1 and L2, and the direction of current is: ud + → Q2 → L2, L1 → Q3 → Ud-.

As can be seen, in the period from t1 to t2, the lower arm Q3 of the first arm and the upper arm Q2 of the second arm are electrically connected to form a current.

After time t2, the circuit repeats the above operation.

The phase difference between the control pulses Q1 and Q3 and the control pulses Q2 and Q4 of the full-bridge inverter circuit is theta, and the pulse width of the voltage U at the two ends of the loads L1 and L2 can be adjusted (the positive width and the negative width are changed simultaneously) by changing the value of theta. In addition, the voltage amplitude of the two ends of the load of the full-bridge inverter circuit is twice that of the voltage amplitude of the load of the half-bridge inverter circuit.

The above circuit operation is only exemplary and not limiting.

According to the above description, the alternating turn-on of Q1 and Q4, and the alternating turn-on of Q2 and Q3 obtain high-frequency chopping, and then the high-frequency chopping is passed through a filter circuit to obtain alternating current which can be connected to a power grid.

Fig. 2 is a schematic diagram of a multi-level single-phase inversion system, and Q5, Q6, D1 and D2 are added to the topology shown in fig. 1.

Assuming that a power grid cycle is 360 degrees, in 0-180 degrees of a power grid half cycle, a loop consisting of D1, Q1, L1, L2, Q4 and Q6 can generate pulse chopping of a Udc/2 voltage, a loop consisting of Q5, Q1, L1, L2, Q4 and Q6 can generate pulse chopping of a Udc voltage, in two intervals of 0-30 degrees and 150-180 degrees, pulse chopping filtering of Udc/2 can generate alternating current, and 30-150 degrees can generate alternating current by pulse chopping filtering of Udc.

In the other half cycle of 180-360 degrees, a loop consisting of Q5, Q2, L2, L1, Q4 and D2 can generate pulse chopping of-Udc/2 voltage, a loop consisting of Q5, Q2, L2, L1, Q3 and Q6 can generate pulse chopping of-Udc voltage, the pulse chopping of-Udc/2 voltage is controlled at 180-210 degrees and 330-360 degrees in the same way, and the pulse chopping of-Udc voltage is controlled at 210-330 degrees.

Fig. 1 shows a schematic diagram of a single-phase full-bridge inverter topology, where Q1 and Q3 are a set of bridge arms, and Q2 and Q4 are a set of bridge arms, which respectively generate pulse chopping for generating Udc and pulse chopping for-Udc, so as to implement dc-ac inversion, however, the two pulse chopping have a relatively high requirement on the inductance of the rear-end filter inductor, which results in relatively large loss of the inductor, and for the switching tube, at any time, when the switching tube is turned on or off, the switching tube realizes the conversion from 0 to Udc or from 0 to-Udc, which results in relatively large switching loss on the switching tube.

Fig. 2 shows a schematic diagram of a multilevel inverter topology, which can increase pulse chopping of Udc/2 and-Udc/2 voltages, and can reduce the loss of the switching tube, but in all control loops, the number of loop devices is large, the conduction loss is increased, and thus the improvement of efficiency is limited.

To address at least some of the above-described deficiencies, pulse chopping of Udc/2 and-Udc/2 voltages is increased while reducing the number of devices in the loop, reducing switching and conduction losses of the switching devices, and reducing losses in the inductor, improving overall conversion efficiency and cost.

Illustratively, the inverter system comprises a direct current power supply part, an inverter circuit and a filter circuit.

In the schematic diagram of the inverter topology shown in fig. 3, for example, Udc, C1, and C2 are dc power supply parts, D1, D2, D3, D4, Q1, Q2, Q3, Q4, Q5, and Q6 constitute an inverter circuit, and L1, L2, and C3 constitute a filter circuit.

Wherein D1, D2, D3 and D4 are diodes; q1, Q2, Q3, Q4, Q5 and Q6 are switching tubes.

The schematic of the inversion topology shown in fig. 3 adds pulse chopping of Udc/2 and-Udc/2 compared to the schematic of the single-phase full-bridge inversion topology shown in fig. 1;

compared with other multilevel technologies, the number of devices through which the main current loop flows is reduced, conduction loss generated on the devices is reduced, and meanwhile, the loops of the positive and negative half cycles do not have shared device loops, so that device loss can be effectively and uniformly distributed, and local device temperature rise is prevented from being too high.

In particular, the main features of the inversion topology shown in fig. 3 are:

pulse chopping of Udc/2 and-Udc/2 is introduced, the voltage of the device is half of the bus voltage, and the switching loss of the switching tube is reduced;

the introduction of pulse chopping of Udc/2 and-Udc/2 can effectively reduce the inductance of the filter inductor and the loss and size of the inductor;

the current main loop devices are few, so that the conduction loss of the switching device can be effectively reduced;

the half-cycle separation of the current loop effectively balances the loss and heating of the device and prevents the temperature of the local device from being raised too high.

Based on the above features, the embodiments of the present invention can exemplarily obtain the following technical effects: firstly, the loss of a switching tube is reduced by introducing multiple levels, the ripple current is reduced, the loss of a filter inductor is also reduced, the conduction loss is reduced, and the efficiency is obviously improved;

secondly, the harmonic content of the output voltage is obviously reduced, and the quality of the output electric energy is improved;

and the device heating is relatively balanced;

in addition, the size of the filter inductor is smaller, and the size of the whole machine can be correspondingly reduced;

and, the control device is few, reduces control complexity.

To fully illustrate the above features and technical effects, the schematic diagram of the inversion topology shown in fig. 3 is described in detail with reference to fig. 4 to 10;

in the following description, the angle of one period of the power grid is defined as ω, and the switching tubes not mentioned are in the off state unless otherwise specified.

According to the magnitude of the voltage of the power grid, one inversion period is divided into the following parts:

(1) when the angle is more than 0 and less than 30 degrees, the switch tube Q5 is continuously conducted, and Q4 is modulated in high frequency.

When Q4 is turned on, current flows through D1, Q5, L1, L2, Q4 to form a loop, capacitor C2 discharges, and capacitor C1 charges, as shown in fig. 4.

When Q4 is off, the load current loops through L1, L2, D3 and Q5 as shown in fig. 5.

(2) When the angle is less than 30 degrees and less than 150 degrees, the switch tube Q5 is continuously conducted, and Q1 and Q4 are synchronously modulated at high frequency.

When Q1 and Q4 are on, the load current forms a loop through Q1, Q5, L1, L2, Q4 as shown in fig. 6.

When Q1 and Q4 are off, the load current loops through L1, L2, D3 and Q5 as shown in fig. 5.

(3) When the angle is more than 150 degrees and less than omega and less than 180 degrees, the working process of 0 and less than omega and less than 30 degrees is repeated.

Specifically, the switching tube Q5 is continuously conducted, and Q4 is modulated at high frequency.

(4) When the angle is more than 180 degrees and less than 210 degrees, the switch tube Q6 is continuously conducted, and Q2 is modulated in high frequency.

When Q2 is turned on, current flows through Q2, L2, L1, Q6, and D2 to form a loop, the capacitor C1 discharges, and the capacitor C2 charges, as shown in fig. 7.

When Q2 is off, current flows through L2, L1, Q6, and D4 forming a freewheeling loop, as shown in fig. 8.

(5) When 210 degrees < omega < 330 degrees, the switching tube Q6 is continuously conducted, and Q2 and Q3 are synchronously modulated at high frequency.

When Q2 and Q3 are on, the load current loops through Q2, L2, L1, Q3, as shown in fig. 9.

When Q2 and Q3 are turned off, the load current forms a freewheeling loop through L2, L1, Q6 and D4, as shown in fig. 8.

(6) When 330 deg. < omega < 360 deg., repeating the working process of 180 deg. < omega < 210 deg..

Specifically, the switching tube Q6 is continuously conducted, and Q2 is modulated at high frequency.

According to one embodiment described in the foregoing, Q5 is continuously turned on within 0 ° to 180 °, Q4 is high-frequency modulated in a full angle range, Q1 is high-frequency modulated in different angle ranges, 0 ° to 30 ° and 150 ° to 180 ° are high-frequency modulated by Q4, and 30 ° to 150 ° are synchronously high-frequency modulated by Q1 and Q4. Pulse chopping of Udc/2 is generated by Q5 and Q4, and a current main loop mainly comprises D1, Q5 and Q4; the Q1 and the Q4 generate pulse chopping of Udc, and the main current loops are mainly Q1 and Q4. D3 and Q5 form a freewheel loop.

As described in connection with fig. 4-9 and 10, the first leg includes Q1, Q5, and Q3, and the second leg includes Q2, Q4. The combined action of upper arm Q1, Q5 of the first arm and lower arm Q4 of the second arm forms current waveforms within 0 to 180 as shown in fig. 10 within 0 to 180.

In 180-360 degrees, Q6 is continuously conducted, Q2 full-angle section high-frequency modulation is carried out, Q3 is carried out with high-frequency modulation in a partial angle section, 180-210 degrees and 330-360 degrees are carried out in the angle section, Q2 and Q6 generate-Udc/2 pulse chopping, and a current main loop is Q2, L2, L1, Q6 and D2; in the angle section of 210-330 degrees, Q2 and Q3 generate-Udc pulse chopping, and the main current loops are Q2, L2, L1 and Q3. Q6 and D4 form a freewheel loop.

As described in connection with fig. 4-9 and 10, the first leg includes Q1, Q5, and Q3, and the second leg includes Q2, Q4. The current waveforms within 180-360 shown in fig. 10 are formed by the combined action of the lower arm Q3 of the first arm, the upper arm Q2 of the second arm, and the switch Q6 within 180-360.

In the previous embodiment, Q5 and Q4 generate pulse chopping of Udc/2, Q2 and Q6 generate pulse chopping of-Udc/2, and by introducing the pulse chopping of Udc/2 and-Udc/2, the voltage of the device is half of the bus voltage, and the switching loss of the switching tube is reduced; the introduction of pulse chopping of Udc/2 and-Udc/2 can effectively reduce the inductance of the filter inductor and the loss and size of the inductor;

within 0-180 degrees, Q5 is continuously conducted, Q4 full-angle section high-frequency modulation is conducted, and Q1 is conducted with high-frequency modulation in different angle sections. Pulse chopping of Udc/2 is generated by Q5 and Q4, and a current main loop mainly comprises D1, Q5 and Q4; the Q1 and the Q4 generate pulse chopping of Udc, and the main current loops are mainly Q1 and Q4. In the range of 180-360 degrees, Q6 is continuously conducted, Q2 is subjected to full-angle section high-frequency modulation, pulse chopping of-Udc/2 is generated by Q2 and Q6, and a main current loop is Q2, L2, L1, Q6 and D2; in the angle section of 210-330 degrees, Q2 and Q3 generate-Udc pulse chopping, and the main current loops are Q2, L2, L1 and Q3. Therefore, in each section in one period, the current main loop devices are few, and the conduction loss of the switching device can be effectively reduced;

and, according to the above description, the half cycle of the current loop is separated, and the current loop overlaps little or not in two half cycles, thereby effectively balancing the loss and heat generation of the device and preventing the local device from over-temperature rise.

Therefore, by introducing the pulse chopping of the Udc/2 and-Udc/2, the voltage of the device is half of the bus voltage, and the switching loss of the switching tube is reduced; the introduction of pulse chopping of Udc/2 and-Udc/2 can effectively reduce the inductance of a filter inductor and reduce the loss and size of the inductor, and the introduction of the multi-level can reduce the loss of a switching tube, reduce ripple current, reduce the loss of the filter inductor, reduce conduction loss and obviously improve the efficiency; the harmonic content of the output voltage is obviously reduced, and the output electric energy quality is improved; in each section in one period, the current main loop devices are few, so that the conduction loss of the switching device can be effectively reduced; and, according to the above description, the half cycle of the current loop is separated, and the current loop overlaps little or not in two half cycles, thereby effectively balancing the loss and heat generation of the device and preventing the local device from over-temperature rise. The heating of the device is relatively balanced; the size of the filter inductor is small, and the size of the whole machine can be correspondingly reduced; and the number of control devices is small, and the control complexity is reduced.

Although the illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the foregoing illustrative embodiments are merely exemplary and are not intended to limit the scope of the invention thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present invention. All such changes and modifications are intended to be included within the scope of the present invention as set forth in the appended claims.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another device, or some features may be omitted, or not executed.

In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the invention and aiding in the understanding of one or more of the various inventive aspects. However, the method of the present invention should not be construed to reflect the intent: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

It will be understood by those skilled in the art that all of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where such features are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.

The various component embodiments of the invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that a microprocessor or Digital Signal Processor (DSP) may be used in practice to implement some or all of the functionality of some of the modules according to embodiments of the present invention. The present invention may also be embodied as apparatus programs (e.g., computer programs and computer program products) for performing a portion or all of the methods described herein. Such programs implementing the present invention may be stored on computer-readable media or may be in the form of one or more signals. Such a signal may be downloaded from an internet website or provided on a carrier signal or in any other form.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

The above description is only for the specific embodiment of the present invention or the description thereof, and the protection scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and the changes or substitutions should be covered within the protection scope of the present invention. The protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. An inversion system, comprising: the power supply part, the inverter circuit and the filter circuit;

the inverter circuit comprises a first bridge arm and a second bridge arm, wherein the first bridge arm is provided with a first output end, and the second bridge arm is provided with a second output end;

the first bridge arm comprises a first switch, a fifth switch and a third switch;

the second bridge arm comprises a second switch and a fourth switch;

the inverter system further comprises a sixth switch; one end of the sixth switch is arranged between the fifth switch and the third switch, and the other end of the sixth switch is arranged between the second switch and the fourth switch;

in the last half period, the first switch is in a closed state in a partial time period, high-frequency modulation is adopted in the partial time period, the fifth switch is in an open state, and high-frequency modulation is adopted in the fourth switch;

in the next half period, the sixth switch is in an open state, the second switch adopts high-frequency modulation, the third switch is in a closed state in a partial period, and high-frequency modulation is adopted in a partial period.

2. The inverter system according to claim 1, wherein the power supply part includes a direct current power source and a first capacitor and/or a second capacitor.

3. The inverter system according to claim 1, wherein the filter circuit comprises a first inductor and/or a second inductor and a third capacitor, the third capacitor being connected in parallel with the load.

4. The inverter system according to claim 1, wherein the first output terminal and the second output terminal are connected to both ends of the filter circuit, respectively.

5. The inverter system of claim 2, wherein the inverter circuit further comprises a first diode connected to the first capacitor and the common terminal of the first switch and the fifth switch, a second diode connected to the sixth switch and the second capacitor, a second diode connected to the common terminal of the first switch and the fifth switch and the common terminal of the second switch and the fourth switch, and a fourth diode connected to the common terminal of the second switch and the fourth switch and the sixth switch.

6. The inverter system of claim 5,