CN113053882A

CN113053882A - Integrated circuit device and method of forming the same

Info

Publication number: CN113053882A
Application number: CN202110151249.2A
Authority: CN
Inventors: 许智育; 陈建豪; 陈嘉伟; 廖善美; 陈蕙祺; 梁育嘉; 林士豪; 林揆伦; 游国丰; 杨丰诚; 陈燕铭
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2020-03-31
Filing date: 2021-02-03
Publication date: 2021-06-29
Also published as: US20220384454A1; DE102020126060A1; TW202141799A; US20230389256A1

Abstract

A transistor includes a gate structure having a first gate dielectric layer and a second gate dielectric layer. A first gate dielectric layer is disposed over the substrate. The first gate dielectric layer includes a first type of dielectric material having a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer comprises a second type of dielectric material having a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than the dielectric constant of silicon oxide. Embodiments of the invention also relate to semiconductor devices and methods of forming the same.

Description

Integrated circuit device and method of forming the same

Technical Field

Embodiments of the invention relate to integrated circuit devices and methods of forming the same.

Background

The semiconductor Integrated Circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each of which is smaller and more complex than the previous generation. In the course of IC evolution, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometry (i.e., the smallest component (or line) that can be fabricated using a fabrication process) has decreased. Such a scale-down process generally results in benefits by improving production efficiency and reducing associated costs. This scaling down also increases the complexity of processing and manufacturing the IC.

For example, gate leakage can become a problem as the gate size of transistors continues to scale down at each technology node. Gate leakage is undesirable because it degrades device performance such as speed and/or power consumption. Conventional semiconductor fabrication methods have not designed a satisfactory solution to this problem. Thus, while conventional methods of fabricating semiconductor devices are generally adequate, they are not satisfactory in all respects.

Disclosure of Invention

According to an aspect of an embodiment of the present invention, there is provided an integrated circuit device including: a substrate; a first gate dielectric layer disposed over the substrate, wherein the first gate dielectric layer has a first material composition; and a second gate dielectric layer disposed over the first gate dielectric layer, wherein the second gate dielectric layer has a second material composition; wherein: the first material composition is different from the second material composition; and the first material component and the second material component each have a dielectric constant greater than that of silicon oxide.

According to another aspect of an embodiment of the present invention, there is provided an integrated circuit device including: a source region and a drain region disposed in the substrate; a channel region disposed between the source region and the drain region; and a gate structure disposed over the channel region, wherein the gate structure includes a gate dielectric component and a metal-containing gate electrode component; wherein: the gate dielectric element includes a plurality of different dielectric layers each having a dielectric constant greater than that of silicon oxide; and the different dielectric layers have dielectric constants different from each other.

According to yet another aspect of embodiments of the present invention, there is provided a method of forming an integrated circuit, including: forming an interfacial layer over a channel region of a substrate; depositing a first type of dielectric material over the interfacial layer as a first portion of the gate dielectric using a first atomic layer deposition process, wherein the first type of dielectric material has a first dielectric constant that is greater than a dielectric constant of silicon oxide, depositing a second type of dielectric material over the first type of dielectric material as a second portion of the gate dielectric using a second atomic layer deposition process, wherein the second type of dielectric material has a second dielectric constant that is greater than the first dielectric constant; and forming a metal-containing gate electrode over the second type of dielectric material.

Drawings

Aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that in accordance with standard practice in the industry, the various components are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1A is a perspective view of an IC device according to various aspects of the present invention.

Fig. 1B is a top plan view of an IC device in accordance with various aspects of the present invention.

Fig. 2-13 are cross-sectional views of an IC device at various stages of manufacture in accordance with various aspects of the invention.

Fig. 14 is a cross-sectional view of a portion of an IC device and a graph indicating material concentration levels alongside the IC device, in accordance with various aspects of the present invention.

Fig. 15-16 are cross-sectional views of an IC device at a stage of fabrication in accordance with various aspects of the invention.

Fig. 17 is a cross-sectional view of a portion of an IC device and a graph indicating material concentration levels alongside the IC device in accordance with various aspects of the invention.

FIG. 18 is a schematic diagram of an SRAM circuit cell in accordance with various aspects of the present invention.

FIG. 19 is a block diagram of a semiconductor manufacturing system in accordance with various aspects of the present invention.

Fig. 20 is a flow chart of a method of fabricating a semiconductor device in accordance with various aspects of the present invention.

Fig. 21 is a flow diagram of a method of fabricating a multi-gate device or portion provided in accordance with one or more aspects disclosed in U.S. patent No.9,887,269 and including an isolation region under the gate.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation. Still further, when a number or range of numbers is described with "about," "approximately," etc., the term is intended to encompass numbers within a reasonable range including the number described (such as within +/-10% of the number described or other value), as understood by those of skill in the art. For example, the term "about 5 nm" encompasses a size range from 4.5nm to 5.5 nm.

The present invention relates generally to semiconductor devices, and more particularly to Field Effect Transistors (FETs) such as planar FETs or three-dimensional fin-line FETs (finfets). One aspect of the invention relates to forming a multi-layer high-k gate dielectric. In this regard, a conventional Metal Oxide Semiconductor Field Effect Transistor (MOSFET) includes a source element, a drain component, a channel element located between the source element and the drain element, and a gate element located above the channel element. The gate element may include a gate dielectric and a gate electrode. The gate dielectric serves as an electrically insulating pad. Transistor performance can be improved by reducing the thickness of the gate dielectric.

However, because the thickness of the gate dielectric becomes thinner as the scaling process continues, the transistor may suffer from current leakage and excessive heat, which may be referred to as gate leakage. Gate leakage can cause problems such as excessive power consumption, poorer reliability, and/or reduced device performance. Recent implementation of gate dielectrics using high-k materials has enabled the gate dielectric to be significantly thicker while achieving the same equivalent Capacitance Equivalent Thickness (CET) of the entire gate structure as a much thinner conventional silicon oxide gate dielectric. In this regard, the use of a high-k gate dielectric may be beneficial relative to an Equivalent Oxide Thickness (EOT). In this regard, the equivalent oxide thickness is a distance typically given in nanometers (nm) that indicates how thick the silicon oxide film will need to be to produce the same effect as the high-k material being used. Materials with larger dielectric constants enable thicker films (still having low equivalent oxide thicknesses) to be used while maintaining fast transistor switching. As such, high-k dielectric materials have become good candidates for implementing the gate dielectric of transistors. Unfortunately, high-k dielectric materials also have a lower bandgap, which is associated with higher gate leakage. As semiconductor technology nodes evolve to 7 nm generations or smaller, the problems discussed above become more severe.

To overcome the problems discussed above, the present invention forms a gate structure that includes not only one gate dielectric layer, but also a plurality of different gate dielectric layers having different material compositions. In a dual layer gate dielectric embodiment, the gate dielectric includes a bottom gate dielectric layer implemented closer to the channel of the transistor and a top gate dielectric layer on top of the bottom gate dielectric layer. The bottom gate dielectric layer and the top gate dielectric layer have different properties and/or physical characteristics from each other. For example, the top gate dielectric layer may have a larger dielectric constant than the bottom gate dielectric layer (despite their both having a high-k material composition) in order to ensure that the overall dielectric constant of the gate structure is still sufficiently high so that the equivalent oxide thickness may be kept low. The top gate dielectric layer also has fewer traps than the bottom gate dielectric layer, which can result in lower noise levels and faster speed. At the same time, the bottom gate dielectric layer has a material composition configured to achieve a better interface (or better integration) with layers disposed below the gate structure, such as an interfacial oxide layer. The thickness and material composition of the top and bottom gate dielectric layers are configured such that a desired high-k dielectric value can be obtained for the gate structure to increase speed without causing too much gate leakage.

In a tri-layer gate dielectric embodiment, the gate dielectric includes a bottom gate dielectric layer (e.g., similar to the bottom layer of a dual-layer gate dielectric scheme) that can form a good interface with an underlying interfacial layer, an intermediate layer (e.g., similar to the top layer of a dual-layer gate dielectric scheme) that can achieve a high dielectric constant and/or fewer traps, and a top layer that can form a good interface with an overlying metal gate electrode and/or can help tune the threshold voltage. Details of the gate structure are discussed below with reference to fig. 1-20.

Fig. 1A and 1B illustrate a three-dimensional perspective view and a top view, respectively, of a portion of an Integrated Circuit (IC) device 90. The IC device 90 may be an intermediate device or portion thereof during IC processing and may include Static Random Access Memory (SRAM) and/or logic circuitry, passive elements such as resistors, capacitors, and inductors, and active elements such as p-type fets (pfets), n-type fets (nfets), finfets, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Complementary Metal Oxide Semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, and/or other memory cells. The present invention is not limited to any particular number of devices or device regions or any particular device configuration unless otherwise required. For example, although the illustrated IC device 90 is a three-dimensional FinFET device, the concepts of the present invention may also be applied to planar FET devices.

Referring to fig. 1A, an IC device 90 includes a substrate 110. Substrate 110 may include a base (single element) semiconductor such as silicon, germanium, and/or other suitable materials; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, and/or other suitable materials; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and/or other suitable materials. The substrate 110 may be a single layer of material having a uniform composition. Alternatively, the substrate 110 may include multiple layers of materials having similar or different compositions suitable for IC device fabrication. In one example, the substrate 110 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 110 may include conductive layers, semiconductor layers, dielectric layers, other layers, or a combination thereof. Various doped regions, such as source/drain regions, may be formed in the substrate 110 or on the substrate 110. The doped regions may be doped with an n-type dopant, such as phosphorus or arsenic, and/or a p-type dopant, such as boron, depending on design requirements. The doped region may be formed directly on the substrate 110 in a p-well structure, an n-well structure, a double-well structure, or using a raised structure. The doped regions may be formed by implantation of dopant atoms, epitaxial growth with in-situ doping, and/or other suitable techniques.

A three-dimensional active region 120 is formed on the substrate 110. The active region 120 is an elongated fin structure that protrudes upward out of the substrate 110. As such, the active region 120 is interchangeably referred to hereinafter as the fin structure 120. Fin structure 120 may be fabricated using suitable processes, including photolithography and etching processes. The photolithography process may include forming a photoresist layer covering the substrate 110, thereby exposing the photoresist to be patterned, performing a post-exposure bake process, and developing the photoresist to form a shielding member (not shown) including the photoresist. A recess is then etched in the substrate 110 using the shielding element, leaving the fin structure 120 on the substrate 110. The etching process may include dry etching, wet etching, Reactive Ion Etching (RIE), and/or other suitable processes. In some embodiments, the fin structure 120 may be formed by a double patterning or multiple patterning process. Typically, a double or multiple patterning process combines a photolithography process with a self-aligned process to enable the formation of patterns having, for example, a smaller pitch than would otherwise be obtainable using a single direct photolithography process. As an example, a layer may be formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the pattern layer using a self-aligned process. This layer is then removed and the remaining spacers or mandrels may then be used to pattern the fin structure 120.

The IC device 90 also includes source/drain features 122 formed over the fin structure 120. Source/drain features 122 may include an epitaxial layer epitaxially grown on fin structure 120.

The IC device 90 also includes an isolation structure 130 formed over the substrate 110. Isolation structures 130 electrically separate the various elements of IC device 90. Isolation structures 130 may comprise silicon oxide, silicon nitride, silicon oxynitride, doped fluorosilicate glass (FSG), low-k dielectric materials, and/or other suitable materials. In some embodiments, the isolation structure 130 may include a Shallow Trench Isolation (STI) feature. In one embodiment, the isolation structures 130 are formed by etching trenches into the substrate 110 during the formation of the fin structures 120. The trench may then be filled with the above-described isolation material, followed by a Chemical Mechanical Planarization (CMP) process. Other isolation structures such as field oxide, local oxidation of silicon (LOCOS), and/or other suitable structures may also be implemented as isolation structures 130. Alternatively, the isolation structure 130 may comprise a multi-layer structure, for example, with one or more thermal oxide liner layers.

IC device 90 also includes gate structures 140, gate structures 140 formed over and bonded to three sides in the channel region of each fin structure 120. In some embodiments, the gate structure 140 may be an HKMG structure including a high-k gate dielectric and a metal gate electrode, wherein the HKMG structure is formed by replacing a dummy gate structure. Although not depicted herein, the gate structure 140 may include additional layers of materials such as an interface layer, a protective layer, other suitable layers, or combinations thereof over the fin structure 120.

Referring to fig. 1B, the plurality of fin structures 120 are longitudinally oriented along the X-direction, and the plurality of gate structures 140 are longitudinally oriented along the Y-direction (i.e., substantially perpendicular to the fin structures 120). In many embodiments, the IC device 90 includes additional features such as gate spacers disposed along sidewalls of the gate structure 40, a hard mask layer disposed over the gate structure 40, and numerous other features. For simplicity, the processing steps of the present invention are described in one embodiment with reference to cross-sectional views corresponding to fig. 2-15, wherein a cross-section of the IC device 90 is taken along dashed lines a-a 'and B-B' illustrated in fig. 1A-1B. Specifically, a cross-sectional view taken along dashed line A-A 'corresponds to a cutaway XZ section (e.g., a plane defined by the X and Z directions of FIG. 1A), and a cross-sectional view taken along dashed line B-B' corresponds to a cutaway YZ section (e.g., a plane defined by the Y and Z directions of FIG. 1A).

Referring now to fig. 2-3, IC device 90 at this stage of fabrication includes substrate 110 discussed above. The dummy gate structure 40 is formed over the substrate 110 in a Z-direction orthogonal to a horizontal plane defined by the X-direction and the Y-direction. The dummy gate structures 40 each interpose a source region and a drain region (e.g., a source/drain region including the source/drain features 122), wherein a channel region is defined between the source region and the drain region in the substrate 110. The dummy gate structure 40 engages the channel region so that current can flow between the source/drain regions during operation. In some implementations, the dummy gate structures 40 are formed over fin structures (e.g., fin structures 120 of fig. 1A-1B) such that the dummy gate structures 40 each wrap around a portion of the fin structures 120. For example, dummy gate structure 40 wraps around the channel region of fin structure 120, thereby interposing the source and drain regions of fin structure 120.

The dummy gate structures 40 may each include a dummy gate dielectric and a dummy gate electrode formed over the dummy gate dielectric. In some embodiments, the dummy gate dielectric may comprise silicon oxide (SiO)₂) And the dummy gate electrode may include polysilicon. As shown in the Y-Z cross-sectional view of fig. 3, each dummy gate structure 40 may be at least partially wrapped over a plurality of fin structures 120.

Still referring to fig. 2, source/drain features 122 are formed in the source/drain regions of substrate 110. In some embodiments, an epitaxial process may be used to form source/drain features 122. For example, a semiconductor material is epitaxially grown on the substrate 110, thereby forming the source/drain features 122 as an epitaxially grown structure. In the depicted embodiment, the dummy gate structures 40 interpose the respective source/drain features 122 and define respective channel regions in the substrate 110 between the respective epitaxial source/drain features 122 under the respective dummy gate structures 40. Accordingly, the IC device 90 may be configured to include transistors including gate structures and their corresponding source/drain features 122 and channel regions to be subsequently formed in place of the dummy gate structures 40. In some implementations, the dummy gate structures 40 are each wrapped over source/drain regions of a fin structure (e.g., fin structure 120 of fig. 1A-1B), extending from the substrate 10, such that the transistor is configured as a FinFET.

The epitaxial process may implement CVD deposition techniques (e.g., Vapor Phase Epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and/or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The epitaxial process may use gaseous and/or liquid precursors that interact with the components of the substrate 110. Source/drain features 122 are doped with n-type dopants and/or p-type dopants. In some implementations, where the transistor is configured as an n-type device, the source/drain features 122 can be a silicon-containing epitaxial layer or a silicon-carbon-containing epitaxial layer doped with phosphorus, other n-type dopants, or a combination thereof (e.g., forming a Si: P epitaxial layer or a Si: C: P epitaxial layer). In some implementations, where the transistor is configured as a p-type device, the source/drain features 122 can be a silicon and germanium containing epitaxial layer (e.g., forming a Si: Ge: B epitaxial layer) doped with boron, other p-type dopants, or a combination thereof. In some implementations, the source/drain features 122 include materials and/or dopants that achieve a desired tensile and/or compressive stress in the channel region. In some implementations, the source/drain features 122 are doped by adding impurities to the source material of the epitaxial process during deposition. In some implementations, the source/drain features 122 are doped by an ion implantation process after the deposition process. In some implementations, an annealing process is performed to activate dopants in source/drain features 122 and/or other source/drain regions of IC device 90.

As shown in fig. 3, isolation structures 130 may also be formed over and/or within substrate 110 to isolate various regions of IC device 90. For example, the isolation structures 130 may define and electrically isolate active device regions and/or passive device regions from each other. In some implementations, the isolation structures 130 may be configured to isolate transistors (corresponding to transistors that are to be formed in place of the dummy gate structures 40 and/or the source/drain features 122) from other transistors, devices, and/or regions of the IC device 90. The isolation structure 130 comprises an isolation material such as silicon oxide, silicon nitride, silicon oxynitride, other suitable isolation materials (e.g., comprising silicon, oxygen, nitrogen, carbon, and/or other suitable isolation constituents), or combinations thereof. The isolation structure 130 may include different structures such as a Shallow Trench Isolation (STI) structure, a Deep Trench Isolation (DTI) structure, and/or a local oxidation of silicon (LOCOS) structure.

In some implementations, STI structures (as an example of isolation structures 130) can be formed by etching trenches into the substrate 110 (e.g., by using a dry etch process and/or a wet etch process) and filling the trenches with an insulator material (e.g., by using a chemical vapor deposition process or a spin on glass process). Chemical Mechanical Polishing (CMP) may be performed to remove excess insulator material and/or to planarize a top surface of the STI structure. In some implementations, STI structures can be formed by depositing an insulator material over the substrate 110 after forming the fins such that the insulator material layer fills gaps (features) between the fin structures and then etching back the insulator material layer. In some implementations, the isolation structure 130 can include a trench-filled multilayer structure such as a bulk dielectric layer disposed over a liner dielectric layer, where the bulk dielectric layer and the liner dielectric layer comprise materials that depend on design requirements (e.g., a bulk dielectric layer comprising silicon nitride disposed over a liner dielectric layer comprising thermal oxide). In some implementations, the isolation structure 130 can include a dielectric layer disposed over a doped liner layer (including, for example, borosilicate glass or phosphosilicate glass).

As shown in fig. 2, gate spacers 230 may be formed adjacent to gate structure 40, e.g., on sidewalls of gate structure 40 in the X-direction. The gate spacers 230 may be formed by depositing a dielectric material and patterning the dielectric material. The deposited dielectric material may include silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). For example, in the depicted embodiment, a dielectric layer, such as a silicon nitride layer, comprising silicon and nitrogen may be deposited over substrate 110 and subsequently anisotropically etched to form gate spacers 230.

Although not specifically illustrated herein for simplicity reasons, in some embodiments, the gate spacer 230 may comprise a multi-layer structure. For example, the gate spacers 230 may each include a first dielectric layer comprising silicon nitride and a second dielectric layer comprising silicon oxide. In some implementations, the gate spacers 230 can include more than one set of spacers, such as seal spacers, offset spacers, sacrificial spacers, dummy spacers, and/or main spacers, formed adjacent to the gate structure 40. In such implementations, the spacers of the respective groups may comprise materials having different etch rates. For example, a first dielectric layer comprising silicon and oxygen may be deposited over substrate 110 followed by anisotropically etching to form a first set of spacers adjacent to the gate stack, and a second dielectric layer comprising silicon and nitrogen may be deposited over substrate 110 followed by anisotropically etching to form a second set of spacers adjacent to the first set of spacers. Implantation, diffusion, and/or annealing processes may be performed to form lightly doped source and drain (LDD) features and/or heavily doped source and drain (HDD) features in the source/drain (S/D) regions 122 before and/or after forming the gate spacers 230.

An interlayer dielectric (ILD) layer 250 is disposed over the substrate 110 and the gate structure 40 in the Z-direction and laterally surrounds the dummy gate structure 40, e.g., in the X-direction. In some embodiments, ILD layer 250 may comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS formed oxide, PSG, BPSG, low-k dielectric material, other suitable dielectric material, or combinations thereof. Exemplary low-k dielectric materials include FSG, carbon-doped silicon oxide,

(California)Applied Materials, Inc. of Santa Clara, Nyya, Xerogel, Aerogel (Aerogel), amorphous fluorinated carbon, parylene, BCB, SiLK (Dow Chemical), polyimide, other low-k dielectric Materials, or combinations thereof. In some implementations, the ILD layer 250 may include a multilayer structure having a plurality of dielectric materials. The ILD layer 250 may be formed over the substrate 110 by a deposition process, such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable methods, or combinations thereof. In some implementations, the ILD layer 250 is formed by a Flowable Cvd (FCVD) process that includes, for example, depositing a flowable material (such as a liquid compound) over the substrate 110 and converting the flowable material into a solid material by a suitable technique such as thermal annealing and/or ultraviolet radiation processing. Even after ILD layer 250 is deposited, one or more CMP processes and/or other planarization processes may be performed such that ILD layer 250 has a substantially planar upper surface.

Referring now to fig. 4 and 5, one or more etching processes 270 are performed on the IC device 90 to remove the dummy gate structure 40. The one or more etching processes 270 may include a wet etching process or a dry etching process, and they may be performed with sufficient etch selectivity between the material of the dummy gate structure 40 and the remainder of the material of the IC device 90, such as the ILD layer 250, the gate spacer 230, and the fin structure 120. In other words, the one or more etch processes 270 may be able to etch away the dummy gate electrode (e.g., comprising polysilicon) and the dummy gate dielectric (e.g., comprising silicon oxide), while the ILD layer 250, gate spacers 230, and fin structure 120 remain substantially intact. As a result of the one or more etching processes 270, trenches 280 (or recesses) are formed in place of the removed dummy gate structures 40. For example, the trench 280 may expose an upper surface of the fin structure 120 and side surfaces of the gate spacer 230.

Referring now to fig. 6 and 7, a deposition process 290 is performed on the IC device 90 to form an interfacial layer 300 in the trench 280. The deposition process 290 may include various types of CVD, PVD, or ALD processes, or combinations thereof. An interfacial layer 300 is formed on the exposed surface of the fin structure 120. Portions of the interfacial layer 300 are also formed on the side surfaces of the gate spacers 230 and the upper surface of the ILD layer 250. As such, the portion of the interfacial layer 300 formed inside the trench 280 may have a U-shape. In some embodiments, the interfacial layer 300 comprises silicon oxide.

Referring now to fig. 8 and 9, a deposition process 310 is performed on the IC device 90 to form a gate dielectric layer 350 over the interfacial layer 300. The deposition process 290 may include an ALD process. Gate dielectric layer 350 comprises a high-K dielectric material. High-k dielectric materials generally refer to dielectric materials having a dielectric constant that is greater than the dielectric constant of silicon oxide (dielectric constant of about 3.9 or k ≈ 3.9). In the illustrated embodiment, the high-k dielectric material of the gate dielectric layer 350 is hafnium oxide (HfO) having a dielectric constant of about 22₂). Hafnium oxide is selected as the material component of the gate dielectric layer 350 due, at least in part, to its ability to form a good interface with the underlying interfacial layer 300. In other words, the hafnium oxide material composition of the gate dielectric layer 350 enables good integration with the interfacial layer 300 such that the interface is substantially defect free. In addition, the hafnium oxide material composition of the gate dielectric layer 350 has a higher bandgap than most other types of high-k dielectric materials. The band gap represents the minimum energy required to excite an electron to a state in the conduction band where it can participate in conduction. As such, the hafnium oxide material composition enables the overall gate dielectric structures herein to achieve a reasonably high dielectric constant (and thus help reduce the equivalent oxide thickness) without causing excessive gate leakage, as gate leakage often increases as the bandgap becomes lower.

Gate dielectric layer 350 is formed to have a thickness 360. The value of thickness 360 may be flexibly configured by tuning process parameters of deposition process 310 (e.g., by adjusting the process duration of deposition process 310). In some embodiments, thickness 360 is configured to be in a range between about 9 angstroms and about 14 angstroms. As will be discussed in more detail below, such a range of thickness 360 is not randomly selected, but rather is specifically configured to optimize performance of IC device 90. Such a range of values for thickness 360 helps optimize the trade-off between gate leakage and effective gate thickness, for example. If the thickness 360 is too high, the overall dielectric constant of the gate may not be high enough, thereby degrading device performance such as speed. If the thickness 360 is too small, the overall gate leakage may be too high because the gate dielectric layer to be formed over the gate dielectric layer 350 will have a higher dielectric constant (and thus higher gate leakage), as discussed in more detail below.

Referring now to fig. 10 and 11, a deposition process 380 is performed on IC device 90 to form a gate dielectric layer 390 over gate dielectric layer 350. The deposition process 380 may include another ALD process. In some embodiments, the ALD process of deposition process 380 and the ALD process of deposition process 290 may be performed within the same deposition chamber. Gate dielectric layer 390 comprises another type of high-k dielectric material that is different from the high-k dielectric material of gate dielectric layer 350. In other words, although both gate dielectric layer 350 and gate dielectric layer 390 may be high-k dielectric materials, they have different high-k material compositions. For example, gate dielectric layer 390 has a dielectric constant greater than that of gate dielectric layer 350. This enables the gate dielectric layer 390 to help raise the overall dielectric constant of the gate dielectric overall, which will achieve a lower equivalent oxide thickness without unduly increasing the overall thickness of the gate dielectric. With a larger dielectric constant, the IC device 90 can achieve faster speeds.

As another example, gate dielectric layer 390 has fewer traps than gate dielectric layer 350. Traps may be considered defects. Traps within the film may be caused by imperfections in the bonding of atoms to atoms of the film. If the trap captures an ion charger (e.g., electrons or holes), this can have adverse electrical effects on mobility/speed, noise, and/or threshold voltage. The trap levels within a given material can be measured using a variety of techniques (e.g., using a 1/f noise measurement method). Such techniques may be used to confirm the material composition of such layers via measurement of trap levels of such layers. Having a lower trap level enables the gate dielectric layer 390 to help reduce noise introduced by the gate structure, which in turn helps to enlarge the circuit design window or reduce the chip area.

However, the higher dielectric constant of the gate dielectric layer 390 may have a lower bandgap, which, as discussed above, may result in increased gate leakage. Thus, gate dielectric layer 390 should not be the only gate dielectric layer of the gate structure. Alternatively, gate dielectric layer 390 is used in conjunction with underlying gate dielectric layer 350 to optimize the performance of the overall gate dielectric structure. In other words, gate dielectric layer 350 and gate dielectric layer 390 are selected or configured for different purposes or roles. As a bottom layer in direct physical contact with the interfacial layer 300 (and also closer to the channel region of the transistor), it is more important that the gate dielectric layer 350 be able to form a good interface or have a good level of integration with the interfacial layer 300 and the channel region underneath it. In contrast, as a top layer farther from the interfacial layer 300 and the channel region of the transistor, it is less of a problem whether the gate dielectric layer 390 can form a good interface with the interfacial layer. Alternatively, and more importantly, the gate dielectric layer 350 has a greater dielectric constant (so as to raise the overall dielectric constant of the gate dielectric structure). Fewer traps for gate dielectric layer 390 also help reduce noise and may increase speed and enlarge the circuit design window. The greater gate leakage associated with the higher dielectric constant of gate dielectric layer 390 is offset by the lower gate leakage associated with the lower dielectric constant of the underlying gate dielectric layer 350 (but still greater than the dielectric constant of silicon oxide).

In some embodiments, gate dielectric layer 390 does not comprise hafnium oxide, but may comprise zirconium oxide (ZrO)_x) Titanium oxide (TiO)₂) Lanthanum oxide (La2O3), or a combination thereof. Zirconia has a dielectric constant of about 29, titania has a dielectric constant of about 80, and lanthana has a dielectric constant of about 30. In other words, the dielectric constant of all of these candidate materials for gate dielectric layer 390 has a dielectric constant that is greater than that of not only silicon oxide but also hafnium oxide (about 22). Also, such a high dielectric constant enables the gate dielectric layer 390 to raise the overall dielectric constant of the gate dielectric structure, thereby enabling a thinner equivalent oxide thickness and faster speed.

Gate dielectric layer 390 is formed to have a thickness 400. The value of the thickness 400 may be configured by tuning process parameters of the deposition process 380 (e.g., by tuning the process duration of the deposition process 380). According to an embodiment of the present invention, thickness 360 of gate dielectric layer 350 is substantially greater than thickness 400 of gate dielectric layer 390. For example, in some embodiments, thickness 360 is in a range between about 9 angstroms and about 14 angstroms, while thickness 400 is in a range between about 2.5 angstroms and about 7 angstroms. In some embodiments, the ratio of thickness 360 to thickness 400 is in a range between about 1.3:1 and about 5.6: 1. In some embodiments, the ratio of thickness 360 to thickness 400 is in a range between about 2:1 and about 3.6: 1. Again, these ranges of thickness 360 and thickness 400 and their ratios are not randomly selected, but are specifically configured to optimize the performance of IC device 90 in order to optimize the speed and/or gate leakage of IC device 90. Without sacrificing effective gate thickness. For example, if gate dielectric layer 350 is too thick relative to gate dielectric layer 390, the overall dielectric constant of the gate dielectric structure may be too large to achieve a low equivalent oxide thickness, meaning that the gate structure may not be able to be scaled down as much as desired. On the other hand, if gate dielectric layer 350 is too thin relative to gate dielectric layer 390, gate leakage may be greater than desired and/or the degree of integration between the overall dielectric structure and interface layer 300 may be degraded. The ranges discussed above ensure that the gate dielectric structure can still be well integrated with the underlying layers while still achieving a sufficient equivalent oxide thickness without necessarily making the gate dielectric thicker and without unduly increasing gate leakage.

Referring now to fig. 12 and 13, one or more deposition processes 420 are performed on IC device 90 to form a gate electrode 430 over gate dielectric layer 390. Gate electrode 430 comprises a metal and may include multiple layers such as one or more protective layers, work function layers, glue/barrier layers, and/or metal fill (or bulk) layers. The protective layer may comprise a material that prevents and/or eliminates diffusion and/or reaction of constituents between the gate

dielectric layers

350 and 390 and other layers of the gate electrode 430. In some implementations, the protective layer includes metal and nitrogen, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (W)₂N), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSi)N) or a combination thereof. The work function layer contains a conductive material, such as an n-type work function material and/or a p-type work function material, that is tuned to have a desired work function, such as an n-type work function or a p-type work function. The p-type work function material comprises TiN, TaN, Ru, Mo, Al, WN and ZrSi₂、MoSi₂、TaSi₂、NiSi₂WN, other p-type work function materials, or combinations thereof. The n-type work function material includes Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, other n-type work function materials, or combinations thereof. The glue/barrier layer may comprise materials that promote adhesion between adjacent layers, such as work function layers and metal fill layers, and/or materials that block and/or reduce diffusion between gate layers, such as work function layers and metal fill layers. For example, the glue/barrier layer comprises a metal (e.g., W, Al, Ta, Ti, Ni, Cu, Co, other suitable metals, or combinations thereof), a metal oxide, a metal nitride (e.g., TiN), or combinations thereof. The metal fill layer serves as the main conductive portion of gate electrode 430 and may comprise a suitable conductive material such as Al, W, and/or Cu. For simplicity, the various layers of gate electrode 430 are not illustrated in detail herein.

After all layers of gate electrode 430 have been deposited, a planarization process, such as a Chemical Mechanical Polishing (CMP) process, may be performed on IC device 90. The planarization process may remove excess portions of the interfacial layer 300, the gate dielectric layer 350, the gate dielectric layer 390, and the gate electrode 430 outside the trench 280 until the remaining portions of the interfacial layer 300, the gate dielectric layer 350, the gate dielectric layer 390, and the gate electrode 430 have upper surfaces that are substantially coplanar (e.g., horizontally flat) with the ILD layer 250. In this stage of fabrication, an HKMG structure is formed that includes the interfacial layer 300, the gate dielectric layer 350, the gate dielectric layer 390, and the remainder of the gate electrode 430 that fills the trench 280.

It should be understood that additional steps may be performed to complete the fabrication of the IC device 90. For example, a multilayer interconnect (MLI) structure may be formed. The MLI structure electrically couples various devices (e.g., transistors, resistors, capacitors, and/or inductors) and/or elements (e.g., gate structures and/or source/drain components) of the IC device 90 together such that the various devices and/or elements operate as specified by the design requirements of the IC device 90. MLI structures may include a combination of dielectric and conductive layers (e.g., metal lines, vias, and contacts) configured to form various interconnect structures. The conductive layers are configured to form vertical interconnect features such as contacts and/or vias (providing, for example, vertical connections and/or vertical electrical routing between the features) and/or horizontal interconnect features such as conductive lines (providing, for example, horizontal electrical routing). The vertical interconnect features typically connect the horizontal interconnect features in different layers (or different planes) of the MLI structure. During operation, the MLI structure routes signals between and/or distributes signals (e.g., clock signals, voltage signals, and/or ground signals) to devices and/or elements of the IC device 90.

Fig. 14 illustrates a portion of the IC device 90 and a plot 500 shown alongside the portion of the IC device 90. In this regard, a portion of the illustrated IC device 90 includes the fin structure 120, the interface layer 300, the gate dielectric layer 350, the gate dielectric layer 390, and a portion of the gate electrode 430. A portion of the IC device 90 shown in fig. 14 may also correspond to a cross-sectional view of the IC device 90, such as an X-Z cross-sectional view or a Y-Z cross-sectional view.

Meanwhile, the graph 500 includes an H axis as its horizontal axis and a Z axis as its vertical axis. The Z-axis corresponds to the same Z-axis (or Z-direction) of the IC device 90. In other words, up and down movement in the Z-axis in graph 500 corresponds to up and down vertical movement (e.g., into and out of different layers) of the IC device 90. The H-axis represents the concentration level of the material. Movement "left" along the H axis means that the concentration level of the material increases, and movement "right" along the H axis means that the concentration level of the material decreases.

Graph 500 includes a curve 510 and a curve 520. Curve 510 represents the concentration level of the material of gate dielectric layer 350 as a function of the position of gate dielectric layer 350 along the Z-axis and curve 520 represents the concentration level of the material of gate dielectric layer 390 as a function of the position of gate dielectric layer 390 along the Z-axis. For example, in an embodiment in which gate dielectric layer 350 has a hafnium oxide material composition and gate dielectric layer 390 has a zirconium oxide material composition (e.g., as merely a non-limiting example material of layer 390), curve 510 represents how the concentration level of hafnium oxide varies with vertical position within IC device 90 (i.e., up and down the Z-axis), and curve 520 represents how the concentration level of zirconium oxide varies with vertical position within IC device 90 (i.e., up and down the Z-axis). It should be appreciated that the vertical position along the Z-axis of plot 500 matches the vertical position along the Z-axis of IC device 90 in fig. 14. It is also noted that the hafnium oxide composition and the zirconium oxide composition used for

layers

350 and 390 are merely non-limiting examples, and that in alternative embodiments, other suitable materials may be used to implement

layers

350 and 390.

Based on plot 500, it can be seen that the concentration level of the material of gate dielectric layer 350 (e.g., hafnium oxide) starts at a negligibly low level of fin structure 120 (since fin structure 120 does not contain hafnium oxide or at least is assumed to contain no hafnium oxide) and gradually moves up into interface layer 300, penetrates sharply up into gate dielectric layer 350 until reaching a peak level 530 near the midpoint of gate dielectric layer 350, and then gradually ramps down back. In some embodiments, peak level 530 may vary with the thickness of layer 350. In other words, as layer 350 becomes thicker, peak level 530 may increase, and vice versa.

Furthermore, the concentration level of the material (e.g., zirconia) of gate dielectric layer 390 also starts from a negligibly low level of fin structure 120 (again, fin structure 120 is free of zirconia or at least assumed to contain no zirconia), remains relatively low in interface layer 300 and gate dielectric layer 350, penetrates up into gate dielectric layer 390 until reaching a peak level 540 near the midpoint of gate dielectric layer 390, and then gradually ramps down backwards. In some embodiments, the peak level 540 may vary as the thickness of the layer 390 varies. In other words, as layer 390 becomes thicker, peak level 540 may increase, and vice versa. In some embodiments, the ratio of peak level 530 to peak level 540 is in a range between about 6:1 and about 22: 1. It should be understood that the ranges and ratios related to peak level 530 and peak level 540 are not randomly selected, but are specifically configured to optimize the performance of IC device 90. For example, these ranges and ratios enable the gate dielectric layer 350 to effectively form a good interface with the underlying interface layer 300 and, at the same time, enable the gate dielectric layer 390 to raise the overall dielectric constant of the gate dielectric structure without contributing much to gate leakage.

The plot 500 may also reflect the condition or characteristics of the IC device 90 in the example real-world environment. For example, although the figures discussed above illustrate a distinct boundary between gate dielectric layer 350 and gate dielectric layer 390, an IC device 90 in the real world may lack such a distinct boundary. Alternatively, the materials of gate

dielectric layers

350 and 390 may slightly merge or diffuse into each other, thereby making any boundary between these two layers difficult to identify. However, using machines such as Transmission Electron Microscope (TEM) tools and/or energy dispersive X-ray spectroscopy (EDS or EDX) tools, the concentration levels of the different materials of gate dielectric layer 350 and gate dielectric layer 390 may be identified as varying with vertical position within IC device 90. As such, by reverse engineering the IC device using a TEM tool or an EDS tool, it can be determined that the IC device has achieved a multilayer gate dielectric scheme similar to embodiments of the present invention.

The above discussion relates to a dual layer gate dielectric scheme. However, the concepts of the present invention may also be applied to tri-layer gate dielectrics. One embodiment of a tri-layer gate dielectric scheme is illustrated in fig. 15-16, which are cross-sectional views in the X-Z plane and Y-Z plane of an IC device, respectively. For consistency and clarity, similar elements appearing in fig. 2-14 and 15-16 will be identically labeled.

The manufacturing stages shown in fig. 15 to 16 are the same manufacturing stages as shown in fig. 12 to 13. In addition to the gate

dielectric layers

350 and 390, the gate dielectric structure in this embodiment also includes a gate dielectric layer 450 formed by a deposition process 440 (e.g., an ALD process). Gate dielectric layer 450 is formed directly on gate dielectric layer 390 and directly below gate electrode 430. Gate dielectric layer 450 has a different material composition than gate

dielectric layers

350 and 390. In more detail, although the gate dielectric layer 350 is configured to be in contact withThe interfacial layer 300 forms a good interface or has good integration with the underlying channel, and the gate dielectric layer 390 is configured to raise the overall dielectric constant of the gate structure and reduce noise, but the gate dielectric layer 450 is configured to facilitate tuning of the gate electrode 430 to the threshold voltage. For example, the material composition of the gate dielectric layer 450 is selected to assist the workfunction metal layer of the gate electrode 430 in tuning the threshold voltage. In some embodiments, gate dielectric layer 350 has a hafnium oxide material composition, gate dielectric layer 390 has a zirconium oxide material composition, and gate dielectric layer 450 has aluminum oxide (Al)₂O₃) Material composition or lanthanum oxide (La)₂O₃) A material component.

Gate dielectric layer 450 is formed to have a thickness 460. Thickness 460 is less than thickness 400 of gate dielectric layer 390 and less than thickness 360 of gate dielectric layer 350. Likewise, the thickness 460 may be configured by adjusting a process parameter (e.g., deposition duration) of the deposition process 440. In some embodiments, thickness 460 is configured to be in a range between about 1.5 angstroms and about 2.5 angstroms, a ratio between thickness 360 and thickness 460 is in a range between about 5:1 and about 10:1, and a ratio between thickness 400 and thickness 460 is in a range between about 1:1 and about 4: 1. These ranges and ratios are not randomly selected, but are specifically configured to ensure that the gate dielectric layer 450 can sufficiently assist threshold voltage tuning without degrading the gate dielectric constant or noise level. Thus, each of the gate dielectric layers 350, 390 and 450 may fully and effectively perform its respective role, thereby forming a good interface with the interface layer 300, respectively, for example, raising the overall dielectric constant of the gate structure and reducing noise and facilitating tuning of the threshold voltage.

Fig. 17 illustrates a portion of the IC device 90 and a plot 600 shown alongside the portion of the IC device 90. While plot 500 in fig. 14 corresponds to the dual layer gate dielectric embodiment discussed above with reference to fig. 1-3, plot 600 corresponds to the tri-layer gate dielectric embodiment discussed above with reference to fig. 15-16. For the sake of clarity, similar elements appearing in fig. 14 will be labeled the same as in fig. 17.

As with plot 500, plot 600 also includes

curves

510 and 520,

curves

510 and 520 representing the variation of the concentration levels of gate dielectric layer 350 and gate dielectric layer 390 along vertical axis Z. Plot 600 also includes a curve 610, where curve 610 represents the variation of the concentration level of gate dielectric layer 450 along vertical axis Z.

Curve 610 indicates that the concentration level of the material (e.g., aluminum oxide or lanthanum oxide) of the gate dielectric layer 450 also starts from a negligibly low level of the fin structure 120 (again, the fin structure 120 does not contain aluminum oxide or lanthanum oxide or at least is assumed not to contain aluminum oxide or lanthanum oxide), remains relatively low in the interface layer 300 and the gate

dielectric layers

350 and 390, penetrates up into the gate dielectric layer 450 until reaching a peak level 620 near the midpoint of the gate dielectric layer 450, and then gradually ramps down back. Likewise, peak level 620 may vary with the thickness of the gate dielectric layer. Peak level 620 is less than

peak levels

540 and 530. In some embodiments, the ratio of peak level 620 to peak level 530 is in a range between about 1:19 and about 1: 40. It should be understood that the ranges and ratios related to peak level 620 and peak level 530 are not randomly selected, but are specifically configured to optimize the performance of IC device 90. For example, these ranges and ratios make the gate dielectric layer 450 thick enough to adequately assist the workfunction metal in tuning the threshold voltage, but not so thick as to reduce the dielectric constant of the overall gate dielectric structure or introduce too much noise.

The multi-layer gate dielectric structure of the present invention may be applied to various types of IC applications. For example, the multi-layer gate dielectric structure may be implemented in a Static Random Access Memory (SRAM) device. An SRAM device is a semiconductor memory that uses bi-stable latch circuits (e.g., flip-flops) to store binary bits of information. A typical SRAM cell may include a pull-up (PU) transistor, a pull-down (PD) transistor, and a Pass Gate (PG) transistor. As semiconductor technology nodes continue to evolve into smaller generations (e.g., less than 10 nanometer nodes), the write and read margins of SRAMs may become more important. The alpha ratio of the SRAM, defined as Id of PU, can be tuned_sat(saturation current) divided by Id of PG_satTo achieve the desired write and/or read margins of the SRAM. ByIn Id_satIs an inverse function of the threshold voltage (Vt), so the threshold voltage can be tuned to the desired Id_sat。

FIG. 18 illustrates an example circuit schematic of a single-ported SRAM cell (e.g., a 1-bit SRAM cell) 800. The single-port SRAM cell 800 includes pull-up transistors PU1, PU 2; pull-down transistors PD1, PD 2; and pass-gate transistors PG1, PG 2. As shown in the circuit diagram, the transistors PU1 and PU2 are p-type transistors, and the transistors PG1, PG2, PD1, and PD2 are n-type transistors. Since the SRAM cell 800 includes six transistors in the illustrated embodiment, it may also be referred to as a 6T SRAM cell.

The drains of pull-up transistor PU1 and pull-down transistor PD1 are coupled together, and the drains of pull-up transistor PU2 and pull-down transistor PD2 are coupled together. Transistors PU1 and PD1 are cross-coupled with transistors PU2 and PD2 to form a first data latch. The gates of transistors PU2 and PD2 are coupled together and with the drains of transistors PU1 and PD1 to form a first storage node SN1, and the gates of transistors PU1 and PD1 are coupled together and with the drains of transistors PU2 and PD2 to form a complementary first storage node SNB 1. The sources of pull-up transistors PU1 and PU2 are coupled to a supply voltage Vcc (also referred to as Vdd), and the sources of pull-down transistors PD1 and PD2 are coupled to a voltage Vss, which in some embodiments may be electrical ground.

The first storage node SN1 of the first data latch is coupled to the bit line BL through a pass-gate transistor PG1, and the complementary first storage node SNB1 is coupled to the complementary bit line BLB through a pass-gate transistor PG 2. The first storage node N1 and the complementary first storage node SNB1 are complementary nodes that are typically at opposite logic levels (logic high or logic low). The gates of pass gate transistors PG1 and PG2 are coupled to word line WL.

Also, according to various aspects of the present invention, each of the transistors PU1, PU2, PD1, PD2, PG1, and PG2 may be implemented using the dual or tri-layer gate dielectric structures discussed above. Doing so will improve the gate leakage problem and also the performance of the SRAM device with respect to speed and power dissipation, for example. It should also be understood that while SRAM devices are used as non-limiting examples of IC applications in which aspects of the present invention may be implemented, other types of IC applications may also implement aspects of the present invention. For example, the multi-layer gate dielectric scheme herein may be applied to peripheral logic circuit devices in an SRAM device (such as row decoders, column decoders, read/write circuits) or other circuit devices such as ring oscillators, Radio Frequency (RF) devices, amplifiers, mixers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and the like.

FIG. 19 illustrates an integrated circuit manufacturing system 900 according to an embodiment of the present invention. The manufacturing system 900 includes a plurality of

entities

902, 904, 906, 908, 910, 912, 914, 916 …, N connected by a communication network 918. The network 918 may be a single network or may be a variety of different networks, such as an intranet and the internet, and may include both wired and wireless communication channels.

In an embodiment, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user such as a product engineer monitoring a product of interest; entity 906 represents a process engineer such as a process engineer that controls the process and associated recipe or an engineer that monitors or tunes the conditions and settings of the process tool; entity 908 represents a metrology tool for IC testing and measurement; entity 910 represents a semiconductor processing tool such as an EUV tool for performing a photolithography process; entity 912 represents a virtual metrology module associated with the processing tool 910; entity 914 represents a high-level process control module associated with process tool 910 and another other process tool; and entity 916 represents a sampling module associated with processing tool 910.

Each entity may interact with other entities and may provide integrated circuit fabrication, process control, and/or computing capabilities to receive such capabilities from the other entities. Each entity may also include one or more computer systems for performing calculations and performing automation. For example, the high-level process control module of entity 914 may include a plurality of computer hardware having software instructions encoded therein. The computer hardware may include hard drives, flash drives, CD-ROMs, RAM memory, display devices (e.g., monitors), input/output devices (e.g., mice and keyboards). The software instructions may be written in any suitable programming language and may be designed to perform specific tasks.

The integrated circuit manufacturing system 900 enables interaction between entities for the purpose of Integrated Circuit (IC) manufacturing and advanced process control of IC manufacturing. In an embodiment, advanced process control includes adjusting process conditions, settings, and/or recipes for one process tool for an associated wafer based on metrology results.

In another embodiment, metrology results are measured from a subset of processed wafers according to an optimal sampling rate determined based on process quality and/or product quality. In yet another embodiment, metrology results are measured from selected fields and points of a subset of processed wafers according to an optimal sampling field/point determined based on various characteristics of process quality and/or product quality.

One of the capabilities provided by the IC manufacturing system 900 may enable collaboration and information access in areas such as design, fabrication and processing, metrology, and advanced process control. Another capability provided by the IC manufacturing system 900 may enable system integration between facilities, such as between metrology tools and process tools. Such integration enables the facility to coordinate its activities. For example, integrating metrology tools and process tools may enable more efficient incorporation of manufacturing information into a manufacturing process or APC module, and may enable wafer data from online or in-situ measurements with metrology tools integrated into associated process tools.

Fig. 20 is a flow chart showing a method 1000 of manufacturing a semiconductor device according to another embodiment of the present invention. The method 1000 includes a step 1010 of forming an interfacial layer over a channel region of a substrate.

The method 1000 includes a step 1020 of depositing a first type of dielectric material over the interfacial layer as a first portion of the gate dielectric using a first Atomic Layer Deposition (ALD) process. The first type of dielectric material has a first dielectric constant that is greater than the dielectric constant of silicon oxide.

The method 1000 includes a step 1030 of depositing a second type of dielectric material over the first type of dielectric material as a second portion of the gate dielectric using a second ALD process. The second type of dielectric material has a second dielectric constant that is greater than the first dielectric constant.

The method 1000 includes a step 1040 of forming a metal-containing gate electrode over the second type of dielectric material.

In some embodiments, the first ALD process and the second ALD process are performed in the same ALD chamber, and the first ALD process is performed with a longer process duration than the second ALD process. In some embodiments, the process duration of the first and second ALD processes is configured such that the first type of dielectric material is between about 1.3 times and about 5.6 times thicker than the second type of dielectric material.

In some embodiments, forming the metal-containing gate electrode comprises: a work function metal component of the gate electrode is deposited directly on the second type of dielectric material, and also a fill metal component of the gate electrode is deposited over the work function metal component.

It should be understood that additional steps may be performed before, during, or after steps 1010-1040. For example, after performing the second ALD process but before forming the metal-containing gate electrode, the method may include the steps of: a third type of dielectric material is deposited over the second type of dielectric material as a third portion of the gate dielectric via a third ALD process. The third type of dielectric material is different from the first type of dielectric material and the second type of dielectric material. In some embodiments, depositing the first type of dielectric material includes depositing hafnium oxide directly on an upper surface of the interfacial layer. In some embodiments, depositing the second type of dielectric material includes depositing zirconia directly on an upper surface of the first type of dielectric material. In some embodiments, depositing the third type of dielectric material includes depositing lanthanum oxide or aluminum oxide directly on the upper surface of the second type of dielectric material. Additional steps may include forming additional interconnect features, packaging, or testing processes.

In summary, the present invention relates to forming a multi-layer gate dielectric structure, rather than a single layer gate dielectric structure. The multi-layer gate dielectric structure implements different types of materials for the respective gate dielectric layers, wherein each type of material (and its corresponding thickness) is selected to achieve a particular goal. For example, in a dual layer gate dielectric scheme, the bottom gate dielectric layer has a material and thickness configured to form a good interface and/or integration with the underlying interfacial layer and/or channel, and the top gate dielectric layer has a material and thickness configured to raise the overall dielectric constant and reduce the noise level. In a tri-layer gate dielectric scheme, the bottom gate dielectric layer has a material and thickness configured to form a good interface and/or integration with the underlying interfacial layer and/or channel, the middle gate dielectric layer has a material and thickness configured to raise the overall dielectric constant and reduce noise levels, and the top gate dielectric layer has a material and thickness configured to facilitate tuning of the threshold voltage.

Based on the above discussion, it can be seen that the present invention provides advantages over conventional source/drain vias. However, it is to be understood that not all advantages are discussed herein, that different embodiments may provide different advantages, and that a particular advantage is not required for any embodiment. One advantage is that the present invention enables the scale-down process to continue. Conventional single layer gate dielectric structures may become impracticable or may suffer performance degradation when device scaling reaches 7 nanometer technology nodes or higher. For example, when implementing the gate dielectric using a silicon oxide material, the gate dielectric must be very thin. On the other hand, when a gate dielectric is implemented using a high-k material such as hafnium oxide, it cannot achieve a high dielectric constant required to meet performance requirements such as speed. When gate dielectrics are implemented using high-k materials having a dielectric constant even greater than that of hafnium oxide, the lower band gap associated with such high-k dielectric materials may cause excessive gate leakage, thereby increasing power consumption and decreasing reliability of the IC device.

In contrast, a multi-layer gate dielectric scheme utilizes multiple gate dielectric layers to achieve different objectives simultaneously. In some embodiments, the bottom layer of the gate dielectric structure is configured to form a good interface and/or have good integration with the underlying layers (e.g., interface layer or channel) in order to prevent formation of defects at the bottom of the substrate. The bottom layer has a relatively high bandgap among the high-k dielectric materials, which helps to reduce gate leakage. At the same time, the top layer (in a dual layer gate dielectric scheme) or the middle layer (in a triple layer gate dielectric scheme) has a different material composition than the bottom layer, e.g., it may have a material composition associated with a greater dielectric constant and/or fewer traps than the bottom layer. In this manner, the top/middle layer may raise the overall dielectric constant of the gate dielectric structure, which enables the gate dielectric structure to achieve the thin thickness required for advanced technology nodes. The high k dielectric constant helps to increase the speed of the IC device. Fewer traps in the intermediate layer also helps to reduce noise levels, which enlarges the circuit design window and enables shrinking of chip area. Furthermore, in a three layer scheme implementing a top layer, such top layer has a material composition specifically configured to enable it to promote the gate electrode when tuning the threshold voltage. Based on the above, the multi-layer gate dielectric structure can achieve a low equivalent oxide thickness while still remaining thin, and it can also reduce gate leakage (or at least not increase gate leakage) and improve device performance such as speed, power consumption, noise and reliability. Other advantages may include compatibility with existing manufacturing processes and ease and low cost of implementation.

The advanced photolithography processes, methods, and materials described above may be used in many applications, including fin field effect transistors (finfets). For example, the fins may be patterned to create relatively close spacing between features, which the above disclosure is well suited to. Additionally, the spacers used to form the fins of the FinFET, also referred to as mandrels, may be processed in accordance with the above disclosure.

It should also be understood that the multi-layer gate dielectric structure of the present invention discussed above may also be applied to multi-channel devices such as a fully-around-Gate (GAA) device. In this regard, GAA devices have fin structures like those discussed above, and they have multi-channel structures such as nano-sheets, nano-wires or nanotubes formed over the fin structures and wrapped by gates. A gate dielectric structure (e.g., a bi-layer or tri-layer structure) may circumferentially surround each channel 360 degrees (e.g., in the form of a nanostructure such as a nanosheet or nanowire). Additional details regarding GAA Device fabrication are disclosed in U.S. patent No. 10,164,012 entitled "Semiconductor Device and Manufacturing Method of" published on 12/25 2018 and U.S. patent No. 10,361,278 entitled "Method of Manufacturing a Semiconductor Device and a Semiconductor Device" published on 23/7/2019, as well as U.S. patent No.9,887,269 entitled "Multi-Gate Device and Method of Manufacturing of" published on 6/2/2018, the disclosures of each U.S. patent being hereby incorporated by reference in their respective entireties. To the extent the present invention relates to fin structures or FinFET devices, such discussion is equally applicable to GAA devices.

In one embodiment, the fabrication of GAA devices is described below (see U.S. patent No. 10,164,012). And forming a first semiconductor layer on the substrate along the first direction and sandwiched between the second semiconductor layers. The first semiconductor layer and the second semiconductor layer are patterned to form a fin structure, so that the fin structure comprises a sacrificial layer formed by the second semiconductor layer and a channel layer formed by the first semiconductor layer. A sacrificial gate structure is formed over the fin structure such that the sacrificial gate structure covers a portion of the fin structure and remains exposed for a remaining portion of the fin structure. The remaining portions of the fin structure not covered by the sacrificial gate structure are removed. The sacrificial layer is recessed horizontally so that the edges of the sacrificial layer are below the sides of the sacrificial gate structure. A liner epitaxial layer is formed on at least the recessed surface of the sacrificial layer. Source/drain regions are formed. The sacrificial gate structure is removed. After removing the sacrificial gate structure, the sacrificial layer in the fin structure is removed, leaving the channel layer exposed. Forming a gate dielectric layer and a gate electrode layer around the exposed channel layer.

In one embodiment, the fabrication of GAA devices is described below (see U.S. patent No. 10,361,278). Forming a fin structure, wherein the fin structure comprises a first semiconductor layer and a second semiconductor layer which are alternately stacked. A sacrificial gate structure is formed over the fin structure. The source/drain regions of the fin structure not covered by the sacrificial gate structure are etched, thereby forming source/drain spacers. The first semiconductor layer is laterally etched through the source/drain spacers. A first insulating layer is formed on at least the etched first semiconductor layer in the source/drain spacers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming an air gap between the source/drain epitaxial layer and the first insulating layer. In another embodiment, a fin structure of alternately stacked first and second semiconductor layers is formed. A sacrificial gate structure is formed over the fin structure. The first semiconductor layer is removed from the source/drain regions of the fin structure not covered by the sacrificial gate structure. A first insulating layer is formed around the second semiconductor layer in the source/drain regions and on lateral ends of the first semiconductor layer. The first insulating layer is partially removed from the second semiconductor layer in the source/drain regions. A source/drain epitaxial layer is formed on the source/drain region, thereby forming an air gap between the source/drain epitaxial layer and a lateral end of the first semiconductor layer.

In one embodiment, the fabrication of a GAA device is described below with reference to fig. 21 (see U.S. patent No.9,887,269). The method 2200 begins with applying an anti-punch through (APT) implant to the substrate at the beginning of step 2202. The method 2200 then proceeds to 2204 where an epitaxial stack is formed on the APT implanted substrate. The epitaxial stack includes a first epitaxial layer of a first composition interposed by a second epitaxial layer of a second composition. The method 2200 proceeds to 2206 where a plurality of fins extending from the substrate are formed. The method 2200 proceeds to 2208 where an oxidation process is performed to form isolation regions in the fin feature. The method 2200 proceeds to step 2210 where Shallow Trench Isolation (STI) features are formed between the fins. The method 2200 proceeds to step 2212 where the STI features are recessed to form STI features and fins are inserted to provide fins extending over the recessed STI features. The method 2200 proceeds to step 2214 where a dummy dielectric layer is formed over the fin. The method 2200 proceeds to step 2216 where a dummy gate stack is formed. The dummy gate stack may also define Source/Drain (S/D) regions of the fin. Method of fabricating 2200 proceeds to step 2218 where a spacer layer is formed on the substrate. The method 2200 proceeds to step 2220 where the spacer layer is etched back. The method 2200 proceeds to step 2222 where the first epitaxial layer is removed from the S/D region. The method 2200 proceeds to step 2224 where an inner spacer layer is formed on the substrate, including surrounding each of the second epitaxial layers in the S/D region. The method 2200 proceeds to 2226 where the inner spacer is etched back. The method 2200 proceeds to step 2228 where S/D features are formed in the S/D regions. The method 2200 proceeds to step 2230 where a Contact Etch Stop Layer (CESL) is formed on the substrate. The method 2200 proceeds to step 2232 where an inter-layer dielectric (ILD) layer is formed over the substrate. The method 100 proceeds to step 2234 where the remaining dummy gate stacks previously formed are removed to form gate trenches in the channel region. The method 2200 proceeds to step 2236 by removing the dummy dielectric layer and the first epitaxial layer from the fin in the gate trench. The method 2200 proceeds to step 2238 where a final gate stack is formed within the gate trench, including surrounding the nanowire. The method 2200 proceeds to step 2240 where a patterned hard mask is formed over the substrate. The method 2200 proceeds to step 2242 where the ILD layer is removed through the openings and portions of the S/D features to form Source/Drain (S/D) contact trenches. The method 2200 proceeds to step 2244 where a conductive layer is deposited in the common S/D contact trench to form a Source/Drain (S/D) conductive metal.

One aspect of the present invention relates to a semiconductor device. The semiconductor device includes a substrate. A first gate dielectric layer is disposed over the substrate. The first gate dielectric layer has a first material composition. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer has a second material composition. The first material composition is different from the second material composition. The first material component and the second material component each have a dielectric constant greater than that of silicon oxide.

In the above semiconductor device, the second material composition has a dielectric constant larger than that of the first material composition.

In the above semiconductor device, the second material composition has fewer traps than the first material composition.

In the above semiconductor device, the first material component includes hafnium oxide; and the second material component comprises zirconium oxide, titanium oxide, or lanthanum oxide.

In the above semiconductor device, the first gate dielectric layer has a first thickness; the second gate dielectric layer has a second thickness; and the first thickness is greater than the second thickness.

In the above semiconductor device, a ratio of the first thickness to the second thickness is in a range between about 1.3:1 and about 5.6: 1.

In the above semiconductor device, a ratio of the first thickness to the second thickness is in a range between about 2:1 and about 3.6: 1.

In the above semiconductor device, further comprising a third gate dielectric layer disposed over the second gate dielectric layer, wherein the third gate dielectric layer has a third material composition different from the first material composition and the second material composition.

In the above semiconductor device, the first material component includes hafnium oxide; the second material component comprises zirconia; and the third material component comprises lanthanum oxide or aluminum oxide.

In the above semiconductor device, an interface layer disposed between the substrate and the first gate dielectric layer is further included.

One aspect of the present invention relates to a semiconductor device. The semiconductor device includes source and drain regions disposed in a substrate, a channel region disposed between the source and drain regions, and a gate structure disposed over the channel region. The gate structure includes a gate dielectric assembly and a metal-containing gate electrode assembly. The gate dielectric device includes a plurality of different dielectric layers, each having a dielectric constant greater than that of silicon oxide. The different dielectric layers have different dielectric constants from each other.

In the above semiconductor device, the plurality of different dielectric layers include a first dielectric layer disposed over the channel region and a second dielectric layer disposed over the first dielectric layer; the first dielectric layer is thicker than the second dielectric layer; and the second dielectric layer has a dielectric constant greater than the first dielectric layer.

In the above semiconductor device, the plurality of different dielectric layers further includes a third dielectric layer disposed over the second dielectric layer; the first dielectric layer comprises hafnium oxide; the second dielectric layer comprises zirconium oxide; and the third dielectric layer comprises lanthanum oxide or aluminum oxide.

In the above semiconductor device, different levels of traps are present in different dielectric layers.

Still another aspect of the present invention relates to a method of manufacturing a semiconductor device. An interfacial layer is formed over a channel region of a substrate. A first type of dielectric material is deposited over the interfacial layer as a first portion of the gate dielectric using a first Atomic Layer Deposition (ALD) process. The first type of dielectric material has a first dielectric constant that is greater than the dielectric constant of silicon oxide. A second type of dielectric material is deposited over the first type of dielectric material as a second portion of the gate dielectric using a second ALD process. The second type of dielectric material has a second dielectric constant that is greater than the first dielectric constant. A metal-containing gate electrode is formed over the second type of dielectric material.

In the method, the first atomic layer deposition process and the second atomic layer deposition process are performed in the same atomic layer deposition chamber; and performing the first atomic layer deposition process for a longer process duration than the second atomic layer deposition process.

In the above method, the process duration of the first atomic layer deposition process and the second atomic layer deposition process is configured such that the first type of dielectric material is between about 1.3 times and about 5.6 times thicker than the second type of dielectric material.

In the above method, further comprising: depositing a third type of dielectric material as a third portion of the gate dielectric over the second type of dielectric material via a third atomic layer deposition process, wherein the third type of dielectric material is different from the first type of dielectric material and the second type of dielectric material.

In the above method, depositing the first type of dielectric material comprises depositing hafnium oxide directly on the upper surface of the interfacial layer; depositing the second type of dielectric material comprises depositing zirconia directly on the upper surface of the first type of dielectric material; and depositing the third type of dielectric material comprises depositing lanthanum oxide or aluminum oxide directly on the upper surface of the second type of dielectric material.

In the above method, forming the metal-containing gate electrode includes: depositing a work function metal component of the gate electrode directly on the second type of dielectric material; and depositing a fill metal component of the gate electrode over the workfunction metal element.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising:

a substrate;

a first gate dielectric layer disposed over the substrate, wherein the first gate dielectric layer has a first material composition; and

a second gate dielectric layer disposed over the first gate dielectric layer, wherein the second gate dielectric layer has a second material composition;

wherein:

the first material composition is different from the second material composition; and

the first material component and the second material component each have a dielectric constant greater than that of silicon oxide.

2. The semiconductor device of claim 1, wherein the second material composition has a dielectric constant greater than the first material composition.

3. The semiconductor device of claim 1, wherein the second material composition has fewer traps than the first material composition.

4. The semiconductor device of claim 1, wherein:

the first material composition comprises hafnium oxide; and

the second material component includes zirconia, titania, or lanthana.

5. The semiconductor device of claim 1, wherein:

the first gate dielectric layer has a first thickness;

the second gate dielectric layer has a second thickness; and

the first thickness is greater than the second thickness.

6. The semiconductor device of claim 5, wherein a ratio of the first thickness to the second thickness is in a range between about 1.3:1 and about 5.6: 1.

7. The semiconductor device of claim 6, wherein a ratio of the first thickness to the second thickness is in a range between about 2:1 and about 3.6: 1.

8. The semiconductor device of claim 1, further comprising a third gate dielectric layer disposed over the second gate dielectric layer, wherein the third gate dielectric layer has a third material composition different from the first material composition and the second material composition.

9. A semiconductor device, comprising:

a source region and a drain region disposed in the substrate;

a channel region disposed between the source region and the drain region; and

a gate structure disposed over the channel region, wherein the gate structure includes a gate dielectric component and a metal-containing gate electrode component;

wherein:

the gate dielectric element comprises a plurality of different dielectric layers each having a dielectric constant greater than that of silicon oxide; and

the different dielectric layers have dielectric constants different from each other.

10. A method of forming a semiconductor device, comprising:

forming an interfacial layer over a channel region of a substrate;

depositing a first type of dielectric material as a first portion of a gate dielectric over the interfacial layer using a first atomic layer deposition process, wherein the first type of dielectric material has a first dielectric constant that is greater than a dielectric constant of silicon oxide;

depositing a second type of dielectric material as a second portion of the gate dielectric over the first type of dielectric material using a second atomic layer deposition process, wherein the second type of dielectric material has a second dielectric constant that is greater than the first dielectric constant; and

a metal-containing gate electrode is formed over the second type of dielectric material.