CN113053815A - Semiconductor device and forming method - Google Patents

Semiconductor device and forming method Download PDF

Info

Publication number
CN113053815A
CN113053815A CN201911368429.5A CN201911368429A CN113053815A CN 113053815 A CN113053815 A CN 113053815A CN 201911368429 A CN201911368429 A CN 201911368429A CN 113053815 A CN113053815 A CN 113053815A
Authority
CN
China
Prior art keywords
layer
dielectric layer
semiconductor
forming
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201911368429.5A
Other languages
Chinese (zh)
Inventor
周飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201911368429.5A priority Critical patent/CN113053815A/en
Publication of CN113053815A publication Critical patent/CN113053815A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

In an embodiment of the invention, a method for forming a semiconductor device with a vertical gate structure is provided. A method of forming a semiconductor device, the method comprising: providing a semiconductor substrate; forming a channel column on the semiconductor substrate; forming an isolation layer covering partial side walls of the channel column on the semiconductor substrate at the side part of the channel column; forming a grid stacking layer and a first dielectric layer on the isolation layer, wherein the grid stacking layer covers the side wall of the channel column, and the first dielectric layer covers the grid stacking layer; etching the grid stacking layer on the side wall of the top of the channel column to form a grid structure, and forming a groove positioned on the grid structure between the first dielectric layer and the channel column; forming a second dielectric layer in the groove; after the second dielectric layer is formed, the second semiconductor layer is formed on the top of the channel column, so that source-drain breakdown can be avoided, and the reliability of the semiconductor device is improved.

Description

Semiconductor device and forming method
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for forming the same.
Background
With the continuous development of semiconductor manufacturing processes, the integration level of semiconductor devices is higher and higher, and the feature size of semiconductor devices is also gradually reduced. However, the performance of semiconductor devices is also in need of improvement.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor device and a method for forming the same, so as to improve the performance of the semiconductor device.
The embodiment of the invention provides a method for forming a semiconductor device, which comprises the following steps: providing a semiconductor substrate; forming a channel column on the semiconductor substrate; forming an isolation layer covering partial side walls of the channel column on the semiconductor substrate at the side part of the channel column; forming a grid stacking layer and a first dielectric layer on the isolation layer, wherein the grid stacking layer covers the side wall of the channel column, and the first dielectric layer covers the grid stacking layer; etching the grid stacking layer on the side wall of the top area of the channel column to form a grid structure, and forming a groove positioned on the grid structure between the first dielectric layer and the channel column; forming a second dielectric layer in the groove; and after forming the second dielectric layer, forming a second semiconductor layer on the top of the channel column.
Optionally, before forming the second dielectric layer, a mask layer is disposed on the top of the channel pillar, and the material of the mask layer is different from the material of the first dielectric layer and the material of the second dielectric layer; the method for forming the semiconductor device further comprises the following steps: and after the second dielectric layer is formed and before the second semiconductor layer is formed, removing the mask layer.
Optionally, the second semiconductor layer is formed by an epitaxial growth process, and conductive ions are doped in situ in the process of forming the second semiconductor layer.
Optionally, the method further includes: before forming the channel column, forming a first semiconductor layer on the semiconductor substrate; after the channel column is formed, the channel column is positioned on the first semiconductor layer; the isolation layer is located on the first semiconductor layer at the side of the channel pillar.
Optionally, the gate structure height occupies 30% to 80% of the depth of the channel pillar.
Optionally, the gate stack layer includes a gate dielectric material layer, a work function material layer and a gate electrode material layer stacked from inside to outside; the gate stack layer for etching the sidewall at the top of the channel pillar comprises: and etching the work function material layer and the gate electrode material layer on the side wall of the top of the channel column.
Optionally, the material of the second dielectric layer is the same as or different from the material of the first dielectric layer.
Optionally, the method for forming the second dielectric layer includes: forming a second dielectric material layer in the groove, on the first dielectric layer and the grid structure; and flattening the second dielectric material layer until the top surface of the first dielectric layer is exposed.
Optionally, the process for forming the second dielectric material layer includes: low temperature chemical vapor deposition, plasma chemical vapor deposition processes, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma enhanced chemical vapor deposition, and fluid chemical vapor deposition processes.
Optionally, a top surface of the gate structure is lower than a top surface of the channel pillar.
Optionally, the gate structure further covers a portion of the isolation layer on one side of the channel pillar.
Optionally, the method further includes: forming a third dielectric layer, wherein the third dielectric layer covers the first dielectric layer, the second dielectric layer and the second semiconductor layer; forming a first connection structure, a second connection structure and a third connection structure, the first connection structure penetrating through the first dielectric layer, the third dielectric layer and the isolation layer and electrically connected to the first semiconductor layer, the second connection structure located on the second semiconductor layer and electrically connected to the second semiconductor layer, the third connection structure penetrating through the first dielectric layer and the third dielectric layer, and the third connection structure electrically connected to the first gate structure or the second gate structure.
The present invention also provides a semiconductor device including: a semiconductor substrate; a plurality of mutually discrete channel columns located on the semiconductor substrate; the isolation layer is positioned on the semiconductor substrate at the side part of the channel column, and the isolation layer covers partial side wall of the channel column; the grid structure is positioned on the isolation layer, surrounds the channel column and covers part of the side wall of the channel column; the second dielectric layer is formed on the grid structure and surrounds the top area of the channel column; the first dielectric layer is formed on the isolation layer and covers the side walls of the grid structure and the second dielectric layer; and the second semiconductor layer is positioned on the top of the channel column.
Optionally, the semiconductor device further includes: and the first semiconductor layer is positioned between the semiconductor substrate and the isolation layer and between the semiconductor substrate and the channel column.
Optionally, the material of the second dielectric layer is the same as or different from the material of the first dielectric layer.
Optionally, the semiconductor device further includes: a third dielectric layer covering the first dielectric layer, the second dielectric layer and the second semiconductor layer; a first connection structure penetrating through the first dielectric layer, the third dielectric layer and the isolation layer and electrically connected to the first semiconductor layer, a second connection structure located on the second semiconductor layer and electrically connected to the second semiconductor layer, and a third connection structure penetrating through the first dielectric layer and the third dielectric layer and electrically connected to the gate structure.
Optionally, the gate structure further covers a portion of the isolation layer on one side of the channel pillar.
Optionally, a top surface of the gate structure is lower than a top surface of the channel pillar.
Optionally, the height of the second semiconductor layer occupies 10% to 25% of the height of the gate structure.
In an embodiment of the invention, a method for forming a semiconductor device with a vertical gate structure is provided. According to the embodiment of the invention, the second semiconductor layer is formed in the groove by forming the groove surrounded by the second dielectric layer and the top of the channel column, and the outline of the second semiconductor layer is controlled by using the shape of the groove. Because the distance between the second semiconductor layer and the channel column is very close, the short channel effect is easy to form, and the embodiment of the invention can avoid the charge concentration caused by the poor shape (such as a sharp corner and the like) of the second semiconductor layer by controlling the good outline of the second semiconductor layer, further avoid the formation of the short channel effect and avoid source-drain breakdown. Therefore, the forming method of the embodiment of the invention can improve the reliability of the semiconductor device.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 is a flow chart of a method of forming a semiconductor device of an embodiment of the present invention;
fig. 2-13 are schematic views of structures formed at various steps of a method of forming a semiconductor device according to an embodiment of the present invention;
fig. 14 is a schematic structural view of a semiconductor device of an embodiment of the present invention.
Detailed Description
The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.
The reliability of the semiconductor device is improved in order to avoid short circuit between the source region or the drain region of the metal oxide field effect transistor and the grid structure. The embodiment of the invention provides a method for forming a semiconductor device, which can improve the performance of the semiconductor device by controlling the outline of a source region or a drain region of a metal oxide field effect transistor. In the embodiments of the present invention, the formation of a metal oxide field effect transistor is taken as an example for explanation.
Fig. 1 is a flow chart of a method of forming a semiconductor device of an embodiment of the present invention. As shown in fig. 1, a method for forming a semiconductor device according to an embodiment of the present invention includes the steps of:
step S100, providing a semiconductor substrate;
step S200, forming a channel column on the semiconductor substrate;
step S300, forming an isolation layer covering partial side walls of the channel column on the semiconductor substrate at the side part of the channel column;
step S400, forming a grid stacking layer and a first dielectric layer on the isolation layer, wherein the grid stacking layer covers the side wall of the channel column, and the first dielectric layer covers the grid stacking layer;
step S500, etching the grid stacking layer on the side wall of the top of the channel column to form a grid structure, and forming a groove positioned on the grid structure between the first dielectric layer and the channel column;
step S600, forming a second dielectric layer in the groove;
and S700, forming a second semiconductor layer on the top of the channel column after forming a second dielectric layer.
Fig. 2 to 14 are schematic views of structures formed at respective steps of a method of forming a semiconductor device according to an embodiment of the present invention.
Referring to fig. 2, in step S100, a semiconductor substrate 10 is provided.
The semiconductor substrate 10 may be a silicon single crystal substrate, a germanium single crystal substrate, or a silicon germanium single crystal substrate, among others. Alternatively, the semiconductor substrate may also be a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator-stacked-germanium (S-SiGeOI), a silicon-on-insulator-germanium (SiGeOI), a germanium-on-insulator (GeOI), a substrate of an epitaxial layer structure on silicon, a compound substrate, or an alloy substrate. The compound substrate comprises silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium, the alloy substrate comprises SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof, and the SOI substrate comprises a semiconductor layer (e.g., a silicon layer, a silicon germanium layer, a carbon silicon layer, or a germanium layer) disposed on a layer of insulating material.
Referring to fig. 3 to 5, in step S200, a channel column 30 is formed on the semiconductor substrate 10.
Further, before forming the channel column 30, a first semiconductor layer 20 is also formed on the semiconductor substrate 10; after the channel pillar 30 is formed, the channel pillar 30 is located on the first semiconductor layer 20.
Referring to fig. 3, a first semiconductor layer 20 is formed on the semiconductor substrate 10.
The method of forming the first semiconductor layer 20 may include an epitaxial growth process. For example, vapor Phase Epitaxy (Vpor-Phase epitoxy, VPE), Liquid Phase Epitaxy (Liquid-Phase epitoxy), Molecular Beam Epitaxy (MBE), Ion Beam Epitaxy (Ion Beam epitoxy, IBE), and the like.
The first semiconductor layer 20 is formed on the semiconductor substrate 10 by epitaxial growth, so that the first semiconductor layer 20 and the semiconductor substrate 10 have good bonding performance, thereby reducing series resistance and improving driving current.
The material of the first semiconductor layer 20 is a conductive ion doped monocrystalline silicon or a conductive ion doped silicon germanium, and the conductive ions are P-type or N-type. The first semiconductor layer 20 is formed at the bottom of a channel pillar to be formed later, and serves as a source region or a drain region of the mosfet.
Further, the in-situ doping may be performed while the first semiconductor layer 20 is epitaxially grown. Further, ion implantation may be performed after the first semiconductor layer 20 is formed, so as to dope the first semiconductor layer 20 with conductive ions.
After the channel pillar 30 is formed, the channel pillar 30 is located on a portion of the first semiconductor layer 20. The channel is in the channel column, and carriers migrate in the axial direction (vertical direction) of the channel column.
Forming the channel column 30 on the semiconductor substrate 10 includes the steps of:
referring to fig. 3, in step S201, a channel pillar material layer 30A is formed on the semiconductor substrate 10.
Specifically, the material of the channel pillar material layer 30A may be single crystal silicon. In the present embodiment, the channel pillar material layer 30A is used to form the channel pillar 30 having a pillar structure in a subsequent process. In an alternative implementation, a mask material layer 30B is further formed above the channel pillar material layer 30A, and is used as a mask in a subsequent etching process and to protect a subsequently formed channel pillar. The material of the mask material layer 30B may be silicon nitride (Si)3N4)。
Referring to fig. 4 and 5, in step S202, a partial region of the channel pillar material layer 30A is etched to expose the first semiconductor layer 20, so as to form a plurality of mutually separated channel pillars 30.
Specifically, the channel pillar 30 has a mask layer 30b on top. The channel pillar material layer 30A is patterned by a photolithography process to form a channel pillar 30. The concrete mode is as follows: forming a photoresist pattern on the mask layer 30B, and transferring the photoresist pattern to the mask material layer 30B to form a patterned mask layer 30B; the channel pillar material layer 30A not covered by the mask layer 30b is then etched.
Specifically, an etching process may be used in which the etching rate of the channel pillar material layer 30A is greater than that of the first semiconductor layer. Further, a dry etching process or a wet etching process may be used, and further, the channel pillar material layer 30a is etched by using an anisotropic etching process.
In an optional implementation manner, the etching is performed by using a dry etching process, and the process parameters of the dry etching process are as follows: HBr flow rate is 50 sccm-500 sccm, NF3The flow rate is 0sccm to 50sccm, O2The flow rate is 0 sccm-50 sccm, the He flow rate is 0 sccm-200 sccm, the Ar flow rate is 0 sccm-500 sccm, the chamber pressure is 2 mTorr-100 mTorr, the source power is 200W-1000W, and the bias power is 0W-200W.
Fig. 4 is a perspective view of the structure formed after step S200. Fig. 5 is a schematic cross-sectional view taken along line XX of fig. 4. As shown in fig. 5, the channel pillar 30 has a width in a cross section along line XX of 5 nm to 20 nm. The pitch of each of the channel pillars 30 is 25 nm to 50 nm. The channel of the mosfet is formed in the channel pillar 30.
The method further comprises the following steps: before the subsequent isolation layer is formed, etching the first semiconductor layer between the adjacent channel columns to enable the first semiconductor layers around the channel columns to be mutually separated; in this case, the subsequently formed isolation layer also fills in the space between the first semiconductor layers around the adjacent channel pillars 30.
Or, the first semiconductor layer is not etched, and a plurality of metal oxide field effect transistors sharing the source region are formed.
Referring to fig. 6, in step S300, an isolation layer covering sidewalls of a portion of the channel pillar is formed on the semiconductor substrate at sides of the channel pillar. The top surface of the isolation layer 40 is lower than the top surface of the channel pillar 30.
Further, the isolation layer 40 is formed on the first semiconductor layer 20 at the side of the channel pillar 30.
The isolation layer 40 serves to isolate adjacent channel pillars 30. The material of the isolation layer 40 may be silicon oxide (SiO)2) Silicon nitride, silicon oxynitride (SiON), low K dielectric materials (dielectric constant greater than or equal to 2.5 and less than 3.9), or ultra low K dielectric materials (dielectric constant less than 2.5).
Specifically, an isolation material layer covering the trench pillar 30 is formed first, and the isolation material layer is planarized by a chemical mechanical polishing process. The isolation material layer is etched back until the upper surface of the isolation material layer is lower than the upper surface of the trench pillar 30 to form an isolation layer 40. In an alternative implementation, the spacer layer 40 is formed to a thickness of 500 to 3000 angstroms.
The method of forming the isolation material layer may be Chemical Vapor Deposition, such as Low Temperature Chemical Vapor Deposition (LTCVD), Plasma Chemical Vapor Deposition (PCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and Fluid Chemical Vapor Deposition (FCVD).
Referring to fig. 7 and 8, a gate stack layer 50a and a first dielectric layer 60 are formed on the isolation layer 40, the gate stack layer 50a covers sidewalls of the channel pillar 30, and the first dielectric layer 60 covers the gate stack layer 50 a.
In an alternative implementation, the gate stack layer 50a includes a gate dielectric material layer 51a, a work function material layer 52a, and a gate electrode material layer 53a stacked in this order. The gate dielectric material layer 51a, the work function material layer 52a and the gate electrode material layer 53a are sequentially stacked on the sidewall and the top end of the channel pillar from inside to outside, that is, the gate dielectric material layer 51a is in a thin film structure wrapping the sidewall and the top end of the channel pillar 30, the work function material layer 52a wraps the gate dielectric material layer 51a, and the gate electrode material layer 53a wraps the work function material layer 52 a. The subsequently formed gate structure is located on the sidewall of the channel pillar 30, and the stacking direction of the gate dielectric material layer 51a, the work function material layer 52a and the gate electrode material layer 53a on the sidewall of the channel pillar 30 is along the horizontal direction. The feature size of the subsequently formed gate structure is the height along the channel pillar. Therefore, increasing the feature size of the gate structure does not take up space in the horizontal direction, and the integration of the semiconductor device can be improved.
The gate dielectric material layer 51a may be a dielectric material having a dielectric constant greater than 3.9, 7.0, or 10.0. For example, an oxide, nitride, oxynitride, silicate (e.g., metal silicate), aluminate, titanate, nitride, or any combination thereof. The gate dielectric material layer 51a may also be a high-K dielectric material, which includes: hafnium oxide (HfO)2) Lanthanum oxide (La)2O3) Zirconium oxide (ZrO)2) Tantalum oxide (Ta)2O5) Titanium oxide (TiO)2) Barium strontium titanate (Ba)1-xSrxTiO3BST), barium titanium oxide (BaTiO)3) Strontium titanium oxide (SrTiO)3) Yttrium oxide (Y)2O3) Alumina (Al)2O3) At least one of (1). In this embodiment, the material of the gate dielectric material layer 51a is a high-K dielectric material, specifically, hafnium oxide.
The gate dielectric layer 51a functions to isolate the work-function material layer 52a from the channel pillar 30. And protects the channel post 30 during a subsequent etching process.
To form the gate dielectric material layer 51a by a suitable deposition process such as chemical vapor deposition, plasma enhanced chemical vapor deposition, Atomic Layer Deposition (ALD), evaporation, physical vapor deposition, chemical solution deposition, or other similar process. The thickness of the gate dielectric material layer 51a may vary depending on the deposition process and the composition and amount of high-K dielectric material used.
The work function material layer 52a may be disposed over the gate dielectric material layer 51 a. The work function material layer 52a is used to adjust the threshold voltage of the formed transistor. The material of the work function material layer 52a depends on the type of transistor and may vary between nFET and pFET devices. Non-limiting examples of suitable work function metals include P-type work function metal materials and N-type work function metal materials. The P-type work function material includes a composition such as ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal oxide, or any combination thereof. N-type metallic materials include compositions such as hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or any combination thereof. The workfunction metal may be deposited by a suitable deposition process such as chemical vapor deposition, electroplating, thermal or electron beam evaporation and sputtering.
The material of the gate electrode material layer 53a may include aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), nickel (Ni), titanium (Ti), cobalt (Co), thallium (Ti), tantalum (Ta), tungsten (W), tungsten silicide (WSi)2) Titanium nitride (TiN) and thallium nitride (TI)3N), in the present embodiment, the material of the gate electrode material layer 53a is tungsten (W).
Each gate stack layer 50a is discrete. Specifically, a photolithography process is used to remove a portion of the work function material layer 52a and a portion of the gate electrode material layer 53a between the channel pillars, so that the gate stack layers 50a are electrically isolated from each other. In an alternative implementation, the gate electrode material layer 53a covers the isolation layer 40 on one side of the channel pillar 30, so as to facilitate the electrical connection of a subsequently formed third connection structure with the gate structure.
Specifically, referring to fig. 8, forming the first dielectric layer 60 includes the steps of:
step S501, forming a first dielectric material layer, where the first dielectric material layer is formed above the isolation layer 40 and covers the gate stack layer 50 a.
Specifically, the first dielectric material layer is formed by using a chemical vapor deposition process or the like. The material of the first dielectric material layer can be silicon oxide, silicon nitride, silicon oxynitride or the like.
Step S502, the first dielectric material layer is planarized until the surface of the gate stack layer on the top of the channel pillar 30 is exposed.
Specifically, a chemical mechanical polishing process is used for carrying out planarization treatment on the first dielectric material layer.
The first dielectric layer 60 is used as a mask for etching the gate stack layer 50a in a subsequent process. The material of the first dielectric layer 60 may be silicon oxide, silicon nitride, silicon oxynitride, or the like. The material of the first dielectric layer 60 is silicon oxide in this embodiment.
In other embodiments, it may also be: the first dielectric material layer is planarized until the mask layer 30b on top of the channel pillar 30 is exposed or the top surface of the channel pillar 30 is exposed.
Referring to fig. 9, in step S500, the gate stack layer 50a on the sidewall of the top region of the channel pillar 30 is etched to form a gate structure 50, and a trench 60a on the gate structure 50 is formed between the first dielectric layer 60 and the channel pillar 30.
Specifically, the gate stack layer 50a is etched to a predetermined height using the first dielectric layer 60 as a mask.
Specifically, a higher etching rate for the work function material layer 52a and the gate electrode material layer 53a than for the gate dielectric material layer 51a and the first dielectric layer 60 may be used. In an alternative implementation, a dry etching process is used with boron trichloride (BCl)3) As an etching gas, the work function material layer 52a and the gate electrode material layer 53a are etched such that the top surface of the gate structure 50 is lower than the top surface of the channel pillar 30. Specifically, the top surface of the gate structure 50 is 500 to 3000 angstroms below the top surface of the channel pillar 30.
In this step, the gate dielectric layer 51 is substantially unchanged with respect to the gate dielectric material layer 51a to ensure the isolation effect of the gate dielectric layer 51 from the gate electrode layer 53 and the channel pillar 30, thereby avoiding a short circuit. In other embodiments, after etching to remove the gate stack material layer 50a not covered by the first dielectric layer 60, the work function layer 52, the gate electrode layer 53 and the gate dielectric layer 51 are flush with each other on top surfaces.
The top surface of the gate structure 50 is defined by the top surfaces of the work function layer 52 and the gate electrode layer 53.
In this embodiment, the gate structure 50 wraps the sidewall of the channel pillar 30, and the contact area between the gate structure 50 and the channel pillar 30 is relatively large, so that the control capability of the gate structure 50 can be improved, and the problem of short channel effect and the like caused by the reduction of the gate pitch size can be avoided.
Referring to fig. 10, in step S600, a second dielectric layer 70 is formed in the trench 60 a.
The material of the second dielectric layer 70 may be silicon oxide, silicon nitride, silicon oxynitride, or the like. The material of the second dielectric layer 70 in this embodiment is silicon oxide. The second dielectric layer 70 serves to isolate the gate structure 50 from a subsequently formed second semiconductor layer.
The formation process of the second dielectric layer 70 may be a chemical vapor deposition process, such as a low temperature chemical vapor deposition, a plasma chemical vapor deposition process, a low pressure chemical vapor deposition, a rapid thermal chemical vapor deposition, a plasma enhanced chemical vapor deposition, and a fluid chemical vapor deposition process. In the present embodiment, the second dielectric layer 70 is formed by a fluid chemical vapor deposition process.
Specifically, a second dielectric material layer is formed in the groove 60a formed in the gate stack structure etched and removed in step S500 and on the first dielectric layer, and then the second dielectric material layer higher than the mask layer 30b is removed by grinding using a chemical mechanical grinding process to form the second dielectric layer 70.
In this embodiment, in the process of grinding and removing the second dielectric material layer higher than the mask layer 30b, the gate dielectric layer 51 above the mask layer 30b is ground and removed until the top surface of the mask layer 30b is exposed.
The material of the mask layer 30b is different from the materials of the first dielectric layer 60 and the second dielectric layer 70, respectively.
Referring to fig. 11 and 12, after forming the second dielectric layer 70, a second semiconductor layer 80 is formed on top of the channel pillar 30 in step S700.
Referring to fig. 11, in the present embodiment, the mask layer 30b is removed before the second semiconductor layer 80 is formed.
Because the mask layer 30b and the channel layer 30a are made of different materials, the mask layer 30b is etched by using an etching process having a high etching ratio to the channel layer 30a, so that the etching depth can be accurately controlled, and the etching loss of the channel layer 30a is avoided. Meanwhile, the materials of the mask layer 30b and the second dielectric layer 70 are also different, so that the second dielectric layer 70 is prevented from being etched to be damaged, and the gate structure 50 and the second semiconductor layer 80 can be well isolated. And the relative positions of the gate structures of the finally formed transistors and the second semiconductor layer 80 are also made to have good consistency. The reliability of the semiconductor device can be improved.
In this step, the mask layer 30b is removed by a dry etching process, and the etching gas used may be fluoromethane (CH)3F) Difluoromethane (CH)2F2) And trifluoromethane (CHF)3) And oxygen is mixed and used as an auxiliary gas in the etching gas. The flow rate of the etching gas is in the range of 20 ml/min to 50 ml/min.
Referring to fig. 12, after forming the second dielectric layer, the second semiconductor layer 80 is formed on the top of the channel pillar 30 by using an epitaxial growth process, and conductive ions are doped in situ during the formation of the second semiconductor layer 80. Further, after the mask layer 30b is removed, the second semiconductor layer 80 is formed by using an epitaxial growth process.
The second semiconductor layer 80 serves as another source region or drain region of the mosfet. The material of the second semiconductor layer 80 is monocrystalline silicon doped with conductive ions or silicon germanium doped with conductive ions, and the conductive ions are P-type or N-type. The material of the second semiconductor layer 80 is the same as the doping type of the material of the first semiconductor layer 20.
Specifically, the second semiconductor layer 80 is formed on the channel layer 30a using an epitaxial growth process. In-situ doping is performed during the epitaxial growth to dope the P-type impurity or the N-type impurity in the second semiconductor layer 80. Further, ion implantation may be performed after the first semiconductor layer 20 is formed, so as to dope the first semiconductor layer 20 with conductive ions.
By forming the second semiconductor layer 80 on top of the channel pillar 30 in this step, the shape and doping concentration of the second semiconductor layer 80 can be well controlled. Because the distance between the second semiconductor layer and the channel column is very close, the short channel effect is easy to form, and the embodiment of the invention can avoid the charge concentration caused by the poor shape (such as a sharp corner and the like) of the second semiconductor layer by controlling the good outline of the second semiconductor layer, further avoid the formation of the short channel effect and avoid source-drain breakdown.
Referring to fig. 13, a third dielectric layer 90 is formed, wherein the third dielectric layer 90 covers the first dielectric layer 60, the second dielectric layer 70 and the second semiconductor layer 80.
Specifically, a chemical vapor deposition process may be used to form the third dielectric material layer, and the third dielectric material layer is planarized to form the third dielectric layer 90. The material of the third dielectric layer 90 may be silicon oxide, silicon nitride, silicon oxynitride, or the like. In this embodiment, the third dielectric layer 90, the second dielectric layer 80 and the first dielectric layer 60 are all made of silicon oxide. The stress between layers can be reduced by adopting the same material, and the reliability of the semiconductor device can be improved. In other embodiments, the materials of the third dielectric layer 90, the second dielectric layer 80, and the first dielectric layer 60 may be different.
Referring to fig. 13, a first connection structure 101, a second connection structure 102 and a third connection structure 103 are formed, the first connection structure 101 penetrates through the first dielectric layer 60, the third dielectric layer 90 and the isolation layer 40 and is electrically connected to the first semiconductor layer 20, the second connection structure 102 is located on the second semiconductor layer 80 and is electrically connected to the second semiconductor layer 80, the third connection structure 103 penetrates through the first dielectric layer 60 and the third dielectric layer 90, and the third connection structure 103 is electrically connected to the gate structure 50.
The material of the first connection structure 101, the second connection structure 102, and the third connection structure 103 is metal, and optionally, copper. In the embodiment of the present invention, a mosfet having a vertical gate structure is formed with the first semiconductor layer 20 as a source region and the second semiconductor layer 80 as a drain region, and in the embodiment, a plurality of mosfets share one drain region. In subsequent processes, an interconnect structure is formed on the formed structure and packaged to form the final semiconductor product.
In an embodiment of the invention, a method for forming a semiconductor device with a vertical gate structure is provided. According to the embodiment of the invention, the second semiconductor layer is formed in the groove by forming the groove surrounded by the second dielectric layer and the top of the channel column, and the outline of the second semiconductor layer is controlled by using the shape of the groove. Therefore, the second semiconductor layer inside the groove and the grid structure outside the groove are effectively isolated by the second dielectric layer, short circuit between the second semiconductor layer and the grid structure can be avoided, and reliability of the semiconductor device is improved.
The embodiment of the invention also provides a semiconductor device. In an alternative implementation, as shown in fig. 14, the semiconductor device includes: a semiconductor substrate 10';
a plurality of mutually discrete channel pillars 30' on the semiconductor substrate;
an isolation layer 40 ' on the semiconductor substrate at the side of the channel pillar, the isolation layer 40 ' covering the channel pillar portion sidewall 30 ';
a gate structure 50 ' on the isolation layer 40 ', the gate structure 50 ' surrounding the channel pillar 30 ' and covering a portion of the sidewall of the channel pillar 30 ';
a second dielectric layer 70 ' formed on the gate structure 50 ' surrounding a top region of the channel pillar 30 ';
a first dielectric layer 60 ' formed on the isolation layer and covering sidewalls of the gate structure 50 ' and the second dielectric layer 70 ';
a second semiconductor layer 80 'on top of the channel pillar 30'.
The material of the second dielectric layer 70 'is the same as or different from the material of the first dielectric layer 60'.
The semiconductor device further includes: a first semiconductor layer 20 ' between the semiconductor substrate 10 ' and the isolation layer 40 ' and between the semiconductor substrate 10 ' and the channel pillar 30 '.
In an alternative implementation the isolation layer 40 'covers the first semiconductor layer 20'. For electrically isolating the first semiconductor layer 20 'from the gate structure 50'.
The semiconductor device further includes: a third dielectric layer 90 'overlying the first dielectric layer 60', the second dielectric layer 70 ', and the second semiconductor layer 80';
a first connection structure 101 'penetrating through the first dielectric layer 60', the third dielectric layer 90 'and the isolation layer 40' and electrically connected to the first semiconductor layer 20 ', a second connection structure 102' on the second semiconductor layer 80 'and electrically connected to the second semiconductor layer 80', a third connection structure 103 'penetrating through the first dielectric layer 60' and the third dielectric layer 90 'and electrically connected to the gate structure 50'. The semiconductor device is a metal oxide field effect transistor, wherein a channel of the metal oxide field effect transistor is located in a channel column 30 ' between the first semiconductor layer 20 ' and the second semiconductor layer 80 '.
The gate structure 50 ' also covers a portion of the isolation layer 40 ' on one side of the channel pillar 30 '.
The top surface of the gate structure 50 'is lower than the top surface of the channel pillar 30'.
In one case, the first semiconductor layer 20 'around each channel pillar 30' is discrete. The gate structures 50' are discrete from one another.
In an embodiment of the invention, the profile of the second semiconductor layer is defined by the second dielectric layer, defining a good profile of the second semiconductor layer. The second semiconductor layer of the embodiment of the invention has a good profile, so that the charge concentration caused by poor shapes (such as sharp corners) of the second semiconductor layer can be avoided, the short channel effect can be further avoided, and the source-drain breakdown is avoided.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (19)

1. A method of forming a semiconductor device, the method comprising:
providing a semiconductor substrate;
forming a channel column on the semiconductor substrate;
forming an isolation layer covering partial side walls of the channel column on the semiconductor substrate at the side part of the channel column;
forming a grid stacking layer and a first dielectric layer on the isolation layer, wherein the grid stacking layer covers the side wall of the channel column, and the first dielectric layer covers the grid stacking layer;
etching the grid stacking layer on the side wall of the top area of the channel column to form a grid structure, and forming a groove positioned on the grid structure between the first dielectric layer and the channel column;
forming a second dielectric layer in the groove;
and after forming the second dielectric layer, forming a second semiconductor layer on the top of the channel column.
2. The method for forming a semiconductor device according to claim 1, wherein a mask layer is provided on top of the channel pillar before the second dielectric layer is formed, and a material of the mask layer is different from a material of each of the first dielectric layer and the second dielectric layer;
the method for forming the semiconductor device further comprises the following steps: and after the second dielectric layer is formed and before the second semiconductor layer is formed, removing the mask layer.
3. The method of claim 1, wherein the second semiconductor layer is formed by an epitaxial growth process, and wherein the second semiconductor layer is doped with conductive ions in situ during the formation of the second semiconductor layer.
4. The method for forming a semiconductor device according to claim 1, further comprising: before forming the channel column, forming a first semiconductor layer on the semiconductor substrate; after the channel column is formed, the channel column is positioned on the first semiconductor layer; the isolation layer is located on the first semiconductor layer at the side of the channel pillar.
5. The method of claim 1, wherein the gate structure height occupies 30% to 80% of the depth of the channel pillar.
6. The method for forming a semiconductor device according to claim 1, wherein the gate stack layer comprises a gate dielectric material layer, a work function material layer and a gate electrode material layer which are stacked from inside to outside; the gate stack layer for etching the sidewall at the top of the channel pillar comprises: and etching the work function material layer and the gate electrode material layer on the side wall of the top of the channel column.
7. The method for forming a semiconductor device according to claim 1, wherein a material of the second dielectric layer is the same as or different from a material of the first dielectric layer.
8. The method of claim 1, wherein the step of forming the second dielectric layer comprises: forming a second dielectric material layer in the groove, on the first dielectric layer and the grid structure; and flattening the second dielectric material layer until the top surface of the first dielectric layer is exposed.
9. The method of claim 8, wherein the process of forming the second dielectric material layer comprises: low temperature chemical vapor deposition, plasma chemical vapor deposition, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma enhanced chemical vapor deposition, and fluid chemical vapor deposition.
10. The method of claim 1, wherein a top surface of the gate structure is lower than a top surface of the channel pillar.
11. The method of claim 1, wherein the gate structure further covers a portion of the isolation layer on one side of the channel pillar.
12. The method of forming a semiconductor device according to claim 4, further comprising:
forming a third dielectric layer, wherein the third dielectric layer covers the first dielectric layer, the second dielectric layer and the second semiconductor layer;
forming a first connection structure, a second connection structure and a third connection structure, the first connection structure penetrating through the first dielectric layer, the third dielectric layer and the isolation layer and electrically connected to the first semiconductor layer, the second connection structure located on the second semiconductor layer and electrically connected to the second semiconductor layer, the third connection structure penetrating through the first dielectric layer and the third dielectric layer, and the third connection structure electrically connected to the gate structure.
13. A semiconductor device, characterized in that the semiconductor device comprises:
a semiconductor substrate;
a plurality of mutually discrete channel columns located on the semiconductor substrate;
the isolation layer is positioned on the semiconductor substrate at the side part of the channel column, and the isolation layer covers partial side wall of the channel column;
the grid structure is positioned on the isolation layer, surrounds the channel column and covers part of the side wall of the channel column;
the second dielectric layer is formed on the grid structure and surrounds the top area of the channel column;
the first dielectric layer is formed on the isolation layer and covers the side walls of the grid structure and the second dielectric layer;
and the second semiconductor layer is positioned on the top of the channel column.
14. The semiconductor device according to claim 13, further comprising: and the first semiconductor layer is positioned between the semiconductor substrate and the isolation layer and between the semiconductor substrate and the channel column.
15. The semiconductor device according to claim 13, wherein a material of the second dielectric layer is the same as or different from a material of the first dielectric layer.
16. The semiconductor device according to claim 14, further comprising:
a third dielectric layer covering the first dielectric layer, the second dielectric layer and the second semiconductor layer; a first connection structure penetrating through the first dielectric layer, the third dielectric layer and the isolation layer and electrically connected to the first semiconductor layer, a second connection structure located on the second semiconductor layer and electrically connected to the second semiconductor layer, and a third connection structure penetrating through the first dielectric layer and the third dielectric layer and electrically connected to the gate structure.
17. The semiconductor device of claim 13, wherein the gate structure further covers a portion of the isolation layer on one side of the channel pillar.
18. The semiconductor device of claim 13, wherein a top surface of the gate structure is lower than a top surface of the channel pillar.
19. The semiconductor device of claim 13, wherein the height of the second semiconductor layer occupies between 10% and 25% of the height of the gate structure.
CN201911368429.5A 2019-12-26 2019-12-26 Semiconductor device and forming method Pending CN113053815A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911368429.5A CN113053815A (en) 2019-12-26 2019-12-26 Semiconductor device and forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911368429.5A CN113053815A (en) 2019-12-26 2019-12-26 Semiconductor device and forming method

Publications (1)

Publication Number Publication Date
CN113053815A true CN113053815A (en) 2021-06-29

Family

ID=76505393

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911368429.5A Pending CN113053815A (en) 2019-12-26 2019-12-26 Semiconductor device and forming method

Country Status (1)

Country Link
CN (1) CN113053815A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116885005A (en) * 2023-07-13 2023-10-13 长鑫科技集团股份有限公司 Semiconductor structure, semiconductor device and preparation method of semiconductor structure

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160293756A1 (en) * 2015-03-31 2016-10-06 Stmicroelectronics, Inc. Vertical tunneling finfet
US9530866B1 (en) * 2016-04-13 2016-12-27 Globalfoundries Inc. Methods of forming vertical transistor devices with self-aligned top source/drain conductive contacts
US10103147B1 (en) * 2017-05-01 2018-10-16 International Business Machines Corporation Vertical transport transistors with equal gate stack thicknesses
US10332983B1 (en) * 2018-03-26 2019-06-25 International Business Machines Corporation Vertical field-effect transistors including uniform gate lengths
US20190319116A1 (en) * 2018-04-12 2019-10-17 International Business Machines Corporation Vertical transport fet devices having a sacrificial doped layer
US10461186B1 (en) * 2018-05-31 2019-10-29 Globalfoundries Inc. Methods of forming vertical field effect transistors with self-aligned contacts and the resulting structures

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160293756A1 (en) * 2015-03-31 2016-10-06 Stmicroelectronics, Inc. Vertical tunneling finfet
US9530866B1 (en) * 2016-04-13 2016-12-27 Globalfoundries Inc. Methods of forming vertical transistor devices with self-aligned top source/drain conductive contacts
US10103147B1 (en) * 2017-05-01 2018-10-16 International Business Machines Corporation Vertical transport transistors with equal gate stack thicknesses
US10332983B1 (en) * 2018-03-26 2019-06-25 International Business Machines Corporation Vertical field-effect transistors including uniform gate lengths
US20190319116A1 (en) * 2018-04-12 2019-10-17 International Business Machines Corporation Vertical transport fet devices having a sacrificial doped layer
US10461186B1 (en) * 2018-05-31 2019-10-29 Globalfoundries Inc. Methods of forming vertical field effect transistors with self-aligned contacts and the resulting structures

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116885005A (en) * 2023-07-13 2023-10-13 长鑫科技集团股份有限公司 Semiconductor structure, semiconductor device and preparation method of semiconductor structure
CN116885005B (en) * 2023-07-13 2024-05-17 长鑫科技集团股份有限公司 Semiconductor structure, semiconductor device and preparation method of semiconductor structure

Similar Documents

Publication Publication Date Title
US20220328356A1 (en) Mechanisms for Forming FinFET Device
US20200321468A1 (en) Structure of S/D Contact and Method of Making Same
US11791421B2 (en) Nanosheet field-effect transistor device and method of forming
US20210408022A1 (en) Ferroelectric random access memory devices and methods
US20200381426A1 (en) Single diffusion break isolation for gate-all-around field-effect transistor devices
TWI645459B (en) Semiconductor structures and methods for forming the same
US11916072B2 (en) Gate isolation structure
KR102234118B1 (en) Non-conformal oxide liner and manufacturing methods thereof
US11996472B2 (en) Multi-layer dielectric refill for profile control in semiconductor devices
KR102638127B1 (en) Etch profile control of via opening
US20230352534A1 (en) Hybrid Channel Semiconductor Device and Method
CN113053815A (en) Semiconductor device and forming method
US11876119B2 (en) Semiconductor device with gate isolation features and fabrication method of the same
US11522073B2 (en) Semiconductor devices and methods of manufacturing thereof
CN112825309B (en) Semiconductor device and forming method
KR20220127119A (en) Fin field-effect transistor device and method
US11855179B2 (en) Semiconductor devices and methods of manufacturing thereof
US11791403B2 (en) Semiconductor devices and methods of manufacturing thereof
US12034063B2 (en) Semiconductor devices and methods of manufacturing thereof
US20240014073A1 (en) Semiconductor devices and methods of manufacturing thereof
US20230402512A1 (en) Semiconductor device with dielectric liners on gate refill metal
US11482421B2 (en) Method of forming a semiconductor device by a replacement gate process
US20220359207A1 (en) Fin Field-Effect Transistor Device and Method of Forming the Same
US20230155005A1 (en) Semiconductor device and method
WO2023040424A1 (en) Semiconductor structure having bottom isolation and enhanced carrier mobility

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination