CN113051071A - Command submitting method and device, command reading method and device, and electronic equipment - Google Patents
Command submitting method and device, command reading method and device, and electronic equipment Download PDFInfo
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- CN113051071A CN113051071A CN202110229669.8A CN202110229669A CN113051071A CN 113051071 A CN113051071 A CN 113051071A CN 202110229669 A CN202110229669 A CN 202110229669A CN 113051071 A CN113051071 A CN 113051071A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30047—Prefetch instructions; cache control instructions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30069—Instruction skipping instructions, e.g. SKIP
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The embodiment of the application provides a command submitting method and device, a command reading method and device and electronic equipment.A CPU (central processing unit) firstly inserts a first linking instruction into a command queue, if the command queue has an image processing command to be executed by a GPU (graphics processing Unit), submits the image processing command to be executed by the GPU to a command buffer area, and inserts a second linking instruction at the tail of the command buffer area; configuring a link address of a first link instruction as an address corresponding to a command buffer; the link address of the second link instruction is configured as a wait instruction or the next first link instruction. According to the method and the device, the image processing commands are completely submitted to the command buffer area, the command queue is only used for storing the link command, the GPU can jump to the command buffer area through the link command to read and execute the image processing commands in the command buffer area, a part of memory is not required to be applied in advance for storing the image processing commands to be executed, and memory resources are saved.
Description
Technical Field
The present application relates to image processing technologies, and in particular, to a command submitting method and apparatus, a command reading method and apparatus, and an electronic device.
Background
In opengl (open Graphics library), a CPU (central Processing Unit) reserves a dedicated command buffer for each client, the command buffer stores a plurality of image Processing commands (e.g., rendering) to be executed by a GPU (Graphics Processing Unit), the image Processing commands are copied from the command buffer to a command queue by the CPU, and the GPU executes the image Processing commands in the command queue in sequence.
At present, a Ring Buffer mode is usually used to submit an image processing command, before the image processing command is submitted using this mode, a part of memory needs to be applied in advance as a circular command queue, a channel for submitting the command is established between a CPU and a GPU, and there are two types of read and write pointers in the circular command queue, the CPU writes the command into the circular command queue from the position of the write pointer, and the GPU reads the command from the circular command queue from the position of the read pointer, and updates the position of the read and write pointers after completing one-time write or read command.
Since the circular command queue needs to apply for a part of the memory in advance, there are problems in that the applied memory is too large or too small. If the applied memory is small, a large number of image processing commands needing GPU processing may be accumulated in the annular command queue after a period of time, and at the moment, the CPU must enter a waiting state until the annular command queue has a memory capable of accommodating the commands submitted by the CPU; if the applied memory is too large, the ring command queue may be in a non-full state in most cases, wasting memory resources.
Disclosure of Invention
The embodiment of the application provides a command submitting method and device, a command reading method and device and electronic equipment, and aims to solve the problem of memory resource waste in the prior art.
According to a first aspect of embodiments of the present application, there is provided a command submission method applied to a CPU of an electronic device, the electronic device including a command queue and a command buffer, the method including:
inserting a first linking instruction into the command queue;
judging whether an image processing command to be executed by the GPU exists or not;
if the image processing command to be executed by the GPU exists, submitting the image processing command to be executed by the GPU to the command buffer area, and inserting a second linking instruction at the tail end of the command buffer area;
configuring a link address of the first link instruction as an address corresponding to the command buffer;
and configuring the link address of the second link instruction as a waiting instruction or a next first link instruction, so that the GPU jumps to the waiting instruction or the next first link instruction after executing the second link instruction.
According to a second aspect of the embodiments of the present application, there is provided a command reading method applied to a GPU of an electronic device, the method including:
when an image processing command to be executed exists, reading a first link instruction in a command queue and then jumping to the command buffer area;
sequentially reading and executing the image processing commands in the command buffer;
after the image processing command in the command buffer is executed, the second link instruction is read and then jump to a waiting instruction or a next first link instruction is carried out.
According to a third aspect of the embodiments of the present application, there is provided a command submitting apparatus applied to a CPU of an electronic device, the electronic device including a command queue and a command buffer, the apparatus including:
the instruction inserting module is used for inserting a first link instruction into the command queue;
the judging module is used for judging whether an image processing command to be executed by the GPU exists or not;
the command submitting module is used for submitting the image processing command to be executed by the GPU to the command buffer area when the image processing command to be executed by the GPU exists;
the instruction insertion module is further used for inserting a second linking instruction at the end of the command buffer;
and the instruction configuration module is used for configuring the link address of the first link instruction as an address corresponding to the command buffer area and configuring the link address of the second link instruction as a waiting instruction or a next first link instruction, so that the GPU jumps to the waiting instruction or the next first link instruction after executing the second link instruction.
According to a fourth aspect of the embodiments of the present application, there is provided a command reading apparatus applied to a GPU of an electronic device, the apparatus including:
the command reading module is used for reading a first link instruction in a command queue and then jumping to a command buffer area when an image processing command to be executed exists; sequentially reading and executing the image processing commands in the command buffer area; after the image processing command in the command buffer is executed, the second link instruction is read and then jump to a waiting instruction or a next first link instruction is carried out.
According to a fifth aspect of embodiments of the present application, there is provided an electronic apparatus, including: the electronic device comprises a processor, a memory and a bus, wherein the processor comprises a CPU and a GPU, the memory stores machine readable instructions executable by the processor, when the electronic device runs, the processor and the memory are communicated through the bus, and the machine readable instructions are executed by the processor to execute a command submitting method or a command reading method provided by the embodiment.
According to a sixth aspect of the embodiments of the present application, there is provided a storage medium having stored thereon a computer program that, when executed by a processor, executes the command submitting method or the command reading method provided by the above embodiments.
In the embodiment, a first linking instruction is firstly inserted into a command queue, when an image processing command to be executed by a GPU exists, the image processing command to be executed by the GPU is submitted to a command buffer area, and a second linking instruction is inserted at the tail of the command buffer area; configuring a link address of a first link instruction as an address corresponding to a command buffer; and configuring the link address of the second link instruction as a waiting instruction or a next first link instruction, so that the GPU can jump to the waiting instruction or the next first link instruction after executing the second link instruction. In the embodiment of the application, all the image processing commands to be executed by the GPU are submitted to the command buffer area, only the link instruction is arranged in the command queue, the GPU can jump to the command buffer area through the link instruction to read and execute the image processing commands in the command buffer area, a part of memory does not need to be applied in advance for storing the image processing commands to be executed, and memory resources are saved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a schematic diagram of a prior art rendering of image processing commands;
fig. 2 is a schematic diagram of Ring Buffer mode provided in an embodiment of the present application;
FIG. 3 is a flowchart of a command submission method provided in an embodiment of the present application;
FIG. 4 is a diagram illustrating an example of an active command queue according to an embodiment of the present disclosure;
FIG. 5 is a second schematic diagram of an active command queue according to an embodiment of the present application;
FIG. 6 is a third schematic diagram of an active command queue according to an embodiment of the present application;
FIG. 7 is a second flowchart of a command submitting method according to an embodiment of the present application;
FIG. 8 is a diagram illustrating a command queue in an inactive state according to an embodiment of the present disclosure;
FIG. 9 is a second schematic diagram of a command queue in an inactive state according to an embodiment of the present application;
FIG. 10 is a functional block diagram of a command submitting apparatus according to an embodiment of the present application;
fig. 11 is a schematic view of an electronic device provided in an embodiment of the present application.
Icon: 10-an electronic device; 11-a processor; 12-a memory; 13-a bus; 110-command submission means; 1101-an instruction insertion module; 1102-a judgment module; 1103 — command submission module; 1104-command configuration module; 1105-loop module.
Detailed Description
In the process of implementing the present application, the inventors found that, in opengl (open Graphics library), each client has a rendering Context (Context) dedicated to itself, where the rendering Context includes a command buffer area private to the client, and a plurality of image Processing commands to be executed by a GPU (Graphics Processing unit) are stored in the command buffer area, and the image Processing commands in the command buffer area need to be copied to a command queue, and the GPU reads and executes the image Processing commands from the command queue in sequence. An excellent command queue must be able to receive commands submitted by the various command buffers to be executed by the GPU, and also be able to give the commands to the GPU in order to execute them on a first-in-first-out basis. As shown in fig. 1, fig. 1 is a schematic diagram of submitting an image processing command provided in the prior art.
In order to ensure that the GPU can issue the image processing commands in order and execute the commands in order, a Ring Buffer (Ring Buffer) mode is commonly used to issue the commands, as shown in fig. 2, and fig. 2 is a schematic diagram of the Ring Buffer mode provided in the embodiment of the present application. In this command submitting mode, a part of memory needs to be applied in advance to a memory of the CPU (or a display memory of the GPU) to be used as a circular command queue for establishing a submitting command channel between the CPU and the GPU, a read pointer and a write pointer exist in the command queue, the CPU writes an image processing command from a position where the write pointer is located when writing the image processing command (i.e., submitting the image processing command submitted by the client to the circular command queue), the GPU reads the image processing command from the position where the read pointer is located when reading the image processing command, and the positions of the read pointer and the write pointer are updated after each time the write command or the read command is completed.
Although this mechanism can provide the image processing commands to be executed to the command queue in order and allow the GPU to execute them in order, it is not possible to determine the memory size that the circular command queue needs to apply for in advance. If the applied memory is small, more image processing commands needing GPU processing are accumulated in the annular command queue after a period of time, no more memory can continuously accommodate the image processing commands submitted by the CPU, and the CPU must enter a waiting state until enough memory space appears in the annular command queue, and the CPU can not add the commands to the annular command queue again; if the applied memory is too large, a lot of image processing commands may be needed to completely fill the circular command queue, and in most cases, the circular command queue may be in a non-full state, wasting memory resources.
In view of the foregoing problems, embodiments of the present application provide a command submitting method and apparatus, a command reading method and apparatus, and an electronic device, where in this embodiment, a first linking instruction is first inserted into a command queue, when there is an image processing command to be executed by a GPU, the image processing command to be executed by the GPU is submitted to a command buffer, and a second linking instruction is inserted at the end of the command buffer; configuring a link address of a first link instruction as an address corresponding to a command buffer; and configuring the link address of the second link instruction as a waiting instruction or a next first link instruction, so that the GPU can jump to the waiting instruction or the next first link instruction after executing the second link instruction. In the embodiment of the application, all the image processing commands to be executed by the GPU are submitted to the command buffer, only the link instruction is in the command queue, the GPU can jump to the command buffer through the link instruction to read and execute the image processing commands in the command buffer, a part of memory for storing the image processing commands to be executed does not need to be applied in advance, the memory is not wasted, and the CPU does not need to wait.
In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following further detailed description of the exemplary embodiments of the present application with reference to the accompanying drawings makes it clear that the described embodiments are only a part of the embodiments of the present application, and are not exhaustive of all embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
Referring to fig. 3, fig. 3 is a flowchart of a command submitting method according to an embodiment of the present disclosure. In this embodiment, the command submission method is applied to a CPU of an electronic device, where the electronic device further includes a GPU, a command queue, and a command buffer, and the method includes:
in step S11, a first linking instruction is inserted into the command queue.
Step S12, determine whether there is an image processing command to be executed by the GPU.
In step S13, if there is an image processing command to be executed by the GPU, the image processing command to be executed by the GPU is submitted to the command buffer, and a second linking instruction is inserted at the end of the command buffer.
In step S14, the link address of the first link instruction is configured as the address corresponding to the command buffer.
In step S15, the link address of the second link instruction is configured as a wait instruction or a next first link instruction, so that the GPU jumps to the wait instruction or the next first link instruction after executing the second link instruction.
And repeating the steps until all the image processing commands to be executed by the GPU are submitted into the command buffer.
In the above steps, all the image processing commands to be executed by the GPU are submitted to the command buffer, only the link instruction is in the command queue, and the GPU can jump to the command buffer through the link instruction to read and execute the image processing commands in the command buffer, without applying a part of memory in advance for storing the image processing commands to be executed, without wasting the memory, and without requiring the CPU to wait, thereby saving the memory resources.
In this embodiment, after the client program submits the image processing commands to be executed by the GPU, the CPU needs to submit the image processing commands to the command buffer for the GPU to read and execute.
Optionally, during the process of submitting the image processing command, the CPU first needs to insert a first linking instruction into the command queue, and at this time, both the head pointer and the tail pointer of the command queue point to the first linking instruction. The queue head pointer is used for indicating the position of an instruction executed by the GPU, and the queue tail pointer is used for indicating the position of an instruction submitted by the CPU.
Therefore, the GPU starts to read the first linking instruction according to the position of the queue head pointer, then determines whether there is an image processing command to be executed by the GPU, that is, whether the client program submits a command requiring GPU processing, and if there is an image processing command to be executed by the GPU (this state may be defined as an active state), the image processing commands are submitted to the command buffer in sequence, and a second linking instruction is inserted at the end of the command buffer.
Then, the link address of the first link instruction is modified into an address corresponding to the command buffer area, namely, the GPU skips to the command buffer area after reading the first link instruction; and configuring the link address of the second link instruction as a waiting instruction or a next first link instruction, reading the second link instruction according to the sequence after the GPU finishes processing all image processing commands in the command buffer area, and then jumping to the waiting instruction or the next first link instruction. At this time, the position of the CPU insert instruction has reached the position of the next first link instruction, and therefore the queue tail pointer should be located at the position of the next first link instruction. As shown in fig. 4, fig. 4 is a schematic diagram of a command queue in an active state according to an embodiment of the present application.
Optionally, in this embodiment, after the GPU executes one image processing command, the queue head pointer may be updated to the position of the next image processing command, so that the GPU may process the image processing commands in sequence according to the position of the queue head pointer.
Fig. 5 is a second schematic diagram of the active command queue according to the embodiment of the present application, as shown in fig. 5. After the image processing command of one command buffer area is executed, jumping to the next first link instruction, then continuously judging whether the image processing command to be executed by the GPU still exists, if so, submitting the image processing command to the second command buffer area, and adding a second link instruction at the tail end of the second command buffer area, wherein the link address of the added second link instruction is configured as a waiting instruction or the next first link instruction; the link address of the first link instruction then needs to be configured to the address of the second command buffer.
That is, after the GPU executes the second link instruction at the end of the first command buffer, the GPU jumps to the next first link instruction, jumps to the second command buffer linked to the first link instruction, continues to read and execute the image processing command in the second command buffer, and thereafter, the GPU continues to read the second link instruction at the end of the second command buffer, and jumps to the waiting instruction or the next first link instruction linked to the second link instruction.
And repeating the steps until all the image processing commands to be executed are submitted into the command buffer.
Optionally, in this embodiment, the wait instruction includes a time that needs the GPU to wait, for example, the wait instruction indicates that the wait time of the GPU is 30 milliseconds, and the GPU waits for 30 milliseconds before executing the next instruction of the wait instruction.
Fig. 6 is a third schematic diagram of a command queue in an active state according to the embodiment of the present application, as shown in fig. 6. When the link address of the second link instruction is the wait instruction, the next instruction of the wait instruction is a link instruction (the third link instruction in fig. 6), and the link address of the third link instruction is the wait instruction. That is, when there is no image processing command to be executed by the GPU, that is, after the GPU has executed all commands of the last command buffer, the second chaining instruction at the end of the command buffer is executed and then jumps to the waiting instruction, after the waiting instruction is executed, the third chaining instruction is executed in sequence, after the third chaining instruction is executed, jumps to the waiting instruction to continue executing, and enters a loop flow to wait for the occurrence of the image processing command to be executed.
When the image processing command needing GPU processing is detected to exist, if the judgment result is that the subsequent image processing command waiting for GPU execution still exists, the waiting command needs to be changed into the first link command, so that the GPU can jump out of the waiting circulation flow and continue to execute the subsequent command.
Optionally, referring to fig. 7, fig. 7 is a second flowchart of a command submitting method according to an embodiment of the present application. In this embodiment, after step S12, the method further includes:
in step S16, if there is no image processing command to be executed by the GPU, the link address of the first link instruction is configured as the first link instruction, so that the GPU circularly executes the first link instruction.
In the above steps, as shown in fig. 8, fig. 8 is one of schematic diagrams of a command queue in an inactive state according to an embodiment of the present application. In this embodiment, if the client program does not submit the image processing command to the CPU, that is, there is no image processing command to be executed by the GPU (this state may be defined as an inactive state), the link address of the first link instruction needs to be configured as the address corresponding to the client program. The GPU, when executed, loops through the first linking instruction until there are image processing commands that require GPU processing.
When there is an image processing command requiring GPU processing, the method described in steps S13 to S15 is referred to, and the GPU jumps to the command buffer read command by configuring the link address of the first link instruction as the command buffer.
Optionally, in another embodiment, after step S12, the method further includes: and if the image processing command to be executed by the GPU does not exist, inserting a waiting instruction before the first linking instruction, and configuring the linking address of the first linking instruction as the waiting instruction.
In the above steps, as shown in fig. 9, fig. 9 is a second schematic diagram of the inactive command queue according to the embodiment of the present application. In this embodiment, when there is no image processing command to be executed by the GPU, a wait instruction may be inserted before the first link instruction, a next instruction of the wait instruction is the first link instruction, and a link address of the first link instruction is configured as the wait instruction.
When the GPU is executed, the wait instruction is executed first, after waiting for a period of time, the next instruction (i.e. the first link instruction) is executed, and when the first link instruction is executed, the GPU jumps to the wait instruction for execution, so that the GPU enters a loop wait flow, and the GPU jumps out of the loop wait flow until an image processing command which needs to be executed by the GPU occurs.
Optionally, in this embodiment, the command queue further includes a queue tail pointer, and when the CPU inserts each first link instruction, a position pointed by the queue tail pointer is updated to a position where the inserted first link instruction is located. That is, each time the CPU commits an instruction, the location pointed to by the queue tail pointer is updated to the location of the newly committed instruction.
Optionally, in this embodiment, the queue head pointer points to a first instruction (a waiting instruction or a first linking instruction) in the command queue when the queue head pointer is initialized, if the command queue is in an inactive state, the queue head pointer does not need to update the position of the pointer, and if the command queue is in an active state, the position of the pointer needs to be updated every time the GPU executes one instruction.
When the queue tail pointer is initialized, the queue tail pointer points to the first instruction (waiting instruction or first linking instruction) in the command queue, if the command queue is in an inactive state, the queue tail pointer does not need to update the position of the pointer, and if the command queue is in an active state, the queue tail pointer is updated to the position of the new first linking instruction every time the first linking instruction is newly inserted.
To sum up, in this embodiment, a first linking instruction is first inserted into a command queue, and when there is an image processing command that needs to be executed by a GPU, the image processing command that needs to be executed by the GPU is submitted to a command buffer, and a second linking instruction is inserted at the end of the command buffer; configuring a link address of a first link instruction as an address corresponding to a command buffer; configuring a link address of the second link instruction as a wait instruction or a next first link instruction, so that the GPU can jump to the wait instruction or the next first link instruction after executing the second link instruction; and repeating the steps until all the image processing commands needing to be executed by the GPU are submitted into the command buffer.
Through the command queue provided by the embodiment, all image processing commands required to be executed by the GPU are submitted to the command buffer area, only the link instruction is arranged in the command queue, the GPU can jump to the command buffer area through the link instruction, and the GPU can conveniently read the commands from the command buffer area to execute the commands. In addition, by using the method, a part of memory is not required to be applied in advance for storing the image processing command to be executed, the condition that the queue is occupied by the image processing command (namely, no memory) does not exist, the CPU does not wait for submitting the command, and the condition that the memory is wasted does not exist.
The embodiment of the application further provides a command reading method, which is applied to a GPU of electronic equipment, wherein the electronic equipment further comprises a CPU, a command queue and a command buffer area, and the method comprises the following steps:
when an image processing command to be executed exists, reading a first link instruction in a command queue and then jumping to a command buffer area; sequentially reading and executing the image processing commands in the command buffer; after the image processing command in the command buffer is executed, the second link instruction is read and then the jump is made to the waiting instruction or the next first link instruction.
In this embodiment, if there is an image processing command that needs to be executed by the GPU, the GPU first reads a first linking instruction in the command queue, then jumps to the command buffer to sequentially read the image processing command in the command buffer, then reads a second linking instruction at the end of the command buffer, and jumps to the next first linking instruction or waiting instruction.
And if the image processing command needing to be executed by the GPU does not exist, the GPU reads the first link instruction and then jumps to the first link instruction or jumps to a waiting instruction.
The command reading method of the GPU has been described in detail in the foregoing embodiments, and is not described herein again.
Referring to fig. 10, fig. 10 is a functional block diagram of a command submitting apparatus 110 according to an embodiment of the present application, applied to a CPU of an electronic device, where the electronic device further includes a GPU, a command queue, and a command buffer, and the apparatus includes:
an instruction insertion module 1101 is configured to insert a first chaining instruction into the command queue.
The determining module 1102 is configured to determine whether there is an image processing command that needs to be executed by the GPU.
A command submitting module 1103, configured to submit, to the command buffer, an image processing command to be executed by the GPU when there is an image processing command that needs to be executed by the GPU.
The instruction insertion module 1101 is further configured to insert a second linking instruction at the end of the command buffer.
An instruction configuration module 1104, configured to configure the link address of the first link instruction as an address corresponding to the command buffer, and configure the link address of the second link instruction as a wait instruction or a next first link instruction, so that the GPU jumps to the wait instruction or the next first link instruction after executing the second link instruction.
In an optional implementation manner, the apparatus further includes a pointer updating module, configured to update, every time a first link instruction is inserted, a location pointed by the queue tail pointer to a location where the inserted first link instruction is located.
In an alternative embodiment, the instruction configuration module 1104 is further configured to:
when the image processing command to be executed by the GPU does not exist, configuring the link address of the first link instruction as the first link instruction so as to enable the GPU to circularly execute the first link instruction.
In another alternative embodiment, the instruction configuration module 1104 is further configured to:
when no image processing command to be executed by the GPU exists, inserting a waiting instruction before the first linking instruction, and configuring the linking address of the first linking instruction as the waiting instruction.
Optionally, an embodiment of the present application further provides a command reading apparatus, where the command reading apparatus is applied to a GPU of an electronic device, the electronic device further includes a CPU, the CPU includes a command queue and a command buffer, and the apparatus includes:
the command reading module is used for reading a first link instruction in the command queue and then jumping to the command buffer area when an image processing command to be executed exists; sequentially reading and executing the image processing commands in the command buffer area; after the image processing command in the command buffer is executed, the second link instruction is read and then jump to a waiting instruction or a next first link instruction is carried out.
In an optional embodiment, the command reading module is further configured to read the first linking instruction and then jump to the first linking instruction or jump to a waiting instruction when there is no image processing command to be executed.
Referring to fig. 11, fig. 11 is a schematic diagram of an electronic device 10 according to an embodiment of the present disclosure, in the embodiment, the electronic device 10 includes a processor 11, a memory 12 and a bus 13, where the processor 11 includes a CPU and a GPU, the memory 12 stores machine-readable instructions executable by the processor 11, when the electronic device 10 runs, the processor 11 and the memory 12 communicate through the bus 13, and the machine-readable instructions are executed by the processor 11 to perform a command submitting method or a command reading method according to the embodiment of the present disclosure.
The embodiment of the present application further provides a storage medium, where a computer program is stored on the storage medium, and the computer program is executed by a processor to perform the command submitting method or the command reading method provided in the embodiment of the present application.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (14)
1. A command submission method applied to a central processing unit CPU of an electronic device including a command queue and a command buffer, the method comprising:
inserting a first linking instruction into the command queue;
judging whether an image processing command to be executed by the GPU exists or not;
if the image processing command to be executed by the GPU exists, submitting the image processing command to be executed by the GPU to the command buffer area, and inserting a second linking instruction at the tail end of the command buffer area;
configuring a link address of the first link instruction as an address corresponding to the command buffer;
and configuring the link address of the second link instruction as a waiting instruction or a next first link instruction, so that the GPU jumps to the waiting instruction or the next first link instruction after executing the second link instruction.
2. The method of claim 1, wherein after determining whether there is an image processing command to be executed by the GPU, the method further comprises:
and if the image processing command to be executed by the GPU does not exist, configuring the link address of the first link instruction as the first link instruction so as to enable the GPU to circularly execute the first link instruction.
3. The method of claim 1, wherein after determining whether there is an image processing command to be executed by the GPU, the method further comprises:
and if the image processing command to be executed by the GPU does not exist, inserting a waiting instruction before the first linking instruction, and configuring the linking address of the first linking instruction as the waiting instruction.
4. The method of any of claims 1-3, wherein the command queue further comprises a queue tail pointer, the method further comprising:
and updating the position pointed by the queue tail pointer to the position of the inserted first link instruction when each first link instruction is inserted.
5. A command reading method applied to a graphics processor GPU of an electronic device, the method comprising:
when an image processing command to be executed exists, reading a first link instruction in a command queue and then jumping to the command buffer area;
sequentially reading and executing the image processing commands in the command buffer;
after the image processing command in the command buffer is executed, the second link instruction is read and then jump to a waiting instruction or a next first link instruction is carried out.
6. The method of claim 5, further comprising:
and when the image processing command to be executed does not exist, reading the first link instruction and then jumping to the first link instruction or jumping to a waiting instruction.
7. A command submitting apparatus applied to a CPU of an electronic device including a command queue and a command buffer, the apparatus comprising:
the instruction inserting module is used for inserting a first link instruction into the command queue;
the judging module is used for judging whether an image processing command to be executed by the GPU exists or not;
the command submitting module is used for submitting the image processing command to be executed by the GPU to the command buffer area when the image processing command to be executed by the GPU exists;
the instruction insertion module is further used for inserting a second linking instruction at the end of the command buffer;
and the instruction configuration module is used for configuring the link address of the first link instruction as an address corresponding to the command buffer area and configuring the link address of the second link instruction as a waiting instruction or a next first link instruction, so that the GPU jumps to the waiting instruction or the next first link instruction after executing the second link instruction.
8. The apparatus of claim 7, wherein the instruction configuration module is further configured to:
configuring a link address of the first link instruction as the first link instruction when there is no image processing command to be executed by the GPU, so that the GPU loops through executing the first link instruction.
9. The apparatus of claim 7, wherein the instruction configuration module is further configured to:
when no image processing command to be executed by the GPU exists, inserting a waiting instruction before the first linking instruction, and configuring the linking address of the first linking instruction as the waiting instruction.
10. The apparatus of any of claims 7-9, wherein the command queue further comprises a queue tail pointer, the apparatus further comprising:
and the pointer updating module is used for updating the position pointed by the queue tail pointer to the position where the inserted first link instruction is located when each first link instruction is inserted.
11. A command reading apparatus applied to a GPU of an electronic device, the apparatus comprising:
the command reading module is used for reading a first link instruction in a command queue and then jumping to a command buffer area when an image processing command to be executed exists; sequentially reading and executing the image processing commands in the command buffer area; after the image processing command in the command buffer is executed, the second link instruction is read and then jump to a waiting instruction or a next first link instruction is carried out.
12. The command reading apparatus of claim 11, wherein the command reading module is further configured to: and when the image processing command to be executed does not exist, reading the first link instruction and then jumping to the first link instruction or jumping to a waiting instruction.
13. An electronic device, comprising: a processor, a memory and a bus, the processor comprising a CPU and a GPU, the memory storing machine-readable instructions executable by the processor, the processor and the memory communicating over the bus when the electronic device is running, the machine-readable instructions when executed by the processor performing the command submission method or the command reading method of any of claims 1-6.
14. A storage medium, having stored thereon a computer program which, when executed by a processor, performs a command submission method or a command reading method according to any one of claims 1 to 6.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110229669.8A CN113051071A (en) | 2021-03-02 | 2021-03-02 | Command submitting method and device, command reading method and device, and electronic equipment |
| PCT/CN2021/087385 WO2022183572A1 (en) | 2021-03-02 | 2021-04-15 | Command submitting method and apparatus, command reading method and apparatus, and electronic device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110229669.8A CN113051071A (en) | 2021-03-02 | 2021-03-02 | Command submitting method and device, command reading method and device, and electronic equipment |
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| CN113051071A true CN113051071A (en) | 2021-06-29 |
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| CN202110229669.8A Pending CN113051071A (en) | 2021-03-02 | 2021-03-02 | Command submitting method and device, command reading method and device, and electronic equipment |
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| CN (1) | CN113051071A (en) |
| WO (1) | WO2022183572A1 (en) |
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| CN116841739A (en) * | 2023-06-30 | 2023-10-03 | 沐曦集成电路(杭州)有限公司 | Data packet reuse system for heterogeneous computing platforms |
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| WO2022183572A1 (en) | 2022-09-09 |
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