CN113035882A - Universal preparation method of non-volatile semiconductor memory - Google Patents
Universal preparation method of non-volatile semiconductor memory Download PDFInfo
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- CN113035882A CN113035882A CN202110258467.6A CN202110258467A CN113035882A CN 113035882 A CN113035882 A CN 113035882A CN 202110258467 A CN202110258467 A CN 202110258467A CN 113035882 A CN113035882 A CN 113035882A
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
Abstract
A universal preparation method of a non-volatile semiconductor memory is based on the non-volatile semiconductor memory, metal doping is carried out in the process of preparing a silicon nitride charge trapping layer to form the metal doped silicon nitride charge trapping layer, and the defect energy level in the silicon nitride trapping layer is effectively regulated, so that shallow energy level defects in the silicon nitride charge trapping layer are simply and efficiently reduced, the transverse diffusion of charges is inhibited, and the density of charge storage is improved, so that the performance of the non-volatile semiconductor memory is improved, and the high reliability of the non-volatile semiconductor memory is realized.
Description
Technical Field
The invention relates to a general method for preparing a nonvolatile semiconductor memory, which improves the reliability of the nonvolatile semiconductor memory by inhibiting the lateral diffusion of charges and improving the density of charge storage, and belongs to the technical field of semiconductor memories.
Background
The development of the digital information era cannot avoid the storage of data, and the rapid growth of the data per se makes the storage of the data especially important in the big data era of the internet of things. The rapid improvement of the performance of the memory provides a good opportunity for data storage. In order to overcome the difficulties brought by the development of semiconductor process technology and the physical size limit of devices, the structure of the memory is changed from a traditional planar device (see fig. 1) to a three-dimensional device (see fig. 2), wherein the three-dimensional charge trapping memory becomes the mainstream of a non-volatile memory due to the advantages of high storage density, low cost and the like. FIG. 1 shows a structure diagram of a conventional planar memory, which includes a control gate (Poly-Si/metal), a barrier oxide layer (SiO)2) Charge trapping layer (Si)3N4) Tunneling oxide layer (SiO)2) And the like. FIG. 2 shows the structure of a three-dimensional charge trapping memory array and a single device, with a cross-sectional view on the right, comprising a polysilicon circular channel layer (Poly-Si) and silicon oxide (SiO) in addition to the planar memory described above2). Although the non-volatile memory is widely applied and has much attention, the reliability of the non-volatile memory is still affected by the charge loss, and specific charge loss mechanisms are shown in fig. 3, including charge loss caused by (i) the Poole-Frenkel effect, (ii) lateral diffusion and (iii) vertical diffusion. With the scaling of device size and the increase of storage density, charge loss is more serious, which may become a critical issue to be solved in the future for non-volatile memories. Therefore, it is an important issue in the field of integrated electronics to explore the physical mechanism of reliability of non-volatile memories, and especially how to improve the reliability of non-volatile memories.
The method for adjusting the performance of the device by atom doping is widely applied to various fields of electronic devices, changes material band gaps, defect energy levels and the like by atom doping, and can simply, quickly and efficiently improve the performance of the electronic devices. However, in the non-volatile memory, the research for improving the reliability of the memory by doping the silicon nitride charge trapping layer with metal atoms is still lacking. The application of metal atom doping may bring new opportunities for the development of nonvolatile memories. In charge trapping memory, a silicon nitride material acts as a charge trapping layer, in which defects effect the storage of data by trapping charge. However, the charges stored in the shallow level defects are easily laterally lost during data retention, thereby greatly reducing the reliability of the nonvolatile memory. Therefore, how to reduce the existence of the shallow level defects becomes a key point for improving reliability.
Disclosure of Invention
Aiming at the problem that the reliability of the nonvolatile semiconductor memory is reduced due to the fact that charges are laterally diffused due to the shallow level defects, the invention provides a universal preparation method of the nonvolatile semiconductor memory.
The general preparation method of the non-volatile semiconductor memory adopts the following technical scheme:
based on the nonvolatile semiconductor memory, metal doping is carried out in the process of preparing the silicon nitride charge trapping layer to form the metal doped silicon nitride charge trapping layer so as to effectively regulate and control the defect energy level of the material and reduce the generation of shallow energy level defects, thereby inhibiting the transverse diffusion of charges, improving the density of charge storage, improving the performance of the nonvolatile semiconductor memory and realizing the high reliability of the nonvolatile semiconductor memory.
The metal doping is to dope metal atoms into the silicon nitride charge trapping layer by evaporation or sputtering when the silicon nitride charge trapping layer is prepared.
The metal doped silicon nitride charge trapping layer requires doped defects to replace original defects, and the doping amount is based on that the defect energy level generated after doping is suitable for electron trapping and erasing.
The doping source of the metal doping is Ti or Hf. The doping concentration of the metal doping is that a defect is introduced into a supercell in 280 atoms, and the purpose of reducing shallow level defects cannot be achieved by excessive or too little doping.
The defect energy level of the regulating material is regulated by doping metal atoms to change the original defect type and form a new defect suitable for electron capture and erasure.
The lateral diffusion of the charges is inhibited, that is, the charges stored in the shallow level defects are easy to laterally diffuse, and the metal doping reduces the existence of the shallow level defects, so that the lateral diffusion of the charges is effectively inhibited.
The improvement of the performance of the non-volatile semiconductor memory refers to that the electron storage density of a doped silicon nitride charge trapping layer is improved, and the original shallow level defect is replaced by a defect suitable for electron trapping and releasing, so that the performance of the non-volatile semiconductor memory is improved.
The high reliability of the non-volatile semiconductor memory is realized, namely, after the silicon nitride is doped, the shallow level defects are reduced, so that the transverse diffusion of charges is inhibited, the loss of the charges is reduced, and the reliability of the non-volatile semiconductor memory is improved.
The invention utilizes metal atoms to dope the silicon nitride charge trapping layer, simply and efficiently reduces shallow energy level defects in the silicon nitride charge trapping layer, thereby inhibiting the lateral diffusion of charges, improving the electron storage density and effectively improving the reliability of the charge trapping type nonvolatile semiconductor memory.
Drawings
Fig. 1 is a schematic diagram of a conventional two-dimensional flash memory structure.
FIG. 2 is a schematic diagram of a conventional three-dimensional charge trapping flash memory structure.
FIG. 3 is a schematic diagram of three charge loss mechanisms of a conventional flash memory.
FIG. 4 is a schematic atomic structure of a silicon nitride charge trapping layer according to the present invention.
FIG. 5 is a diagram of the formation energy of various defects after metal doping in the present invention; wherein: (a) is a schematic diagram of a defect level generated when an atom doping position is an interstitial position, (b) is a schematic diagram of a shallow defect level introduced when N-substitutional doping is performed, and (c) is a schematic diagram of La replacing Si atoms (La)Si) Schematic diagram of shallow defect energy level introduced.
FIG. 6 is a statistical view of defect levels in metal-doped silicon nitride of the present invention.
Fig. 7 is a diagram of metal doping suppressing shallow level defects in the present invention.
FIG. 8 is a process core flow diagram of the present invention.
Fig. 9 is a graph of device transfer characteristics before and after metal doping in the present invention.
Fig. 10 is a graph showing the charge density distribution of the memory before and after the metal doping in the present invention.
FIG. 11 is a system layout of the present invention.
Detailed Description
The invention aims to improve the reliability of a nonvolatile semiconductor memory by utilizing a general preparation method of the nonvolatile semiconductor memory. On the basis of the nonvolatile semiconductor memory, the defect energy level is regulated and controlled by a metal doped (such as Ti or Hf doped) silicon nitride charge trapping layer, and the existence of shallow level defects is reduced, so that the transverse diffusion of charges is inhibited, the charge storage density is improved, the performance of the nonvolatile semiconductor memory is obviously optimized, and the reliability of the nonvolatile semiconductor memory is improved.
The invention carries out collaborative design on the non-volatile semiconductor memory based on the first principle calculation and the TCAD simulation. By doping different metal atoms in the silicon nitride charge trapping layer, the defect energy level is regulated and controlled, and the existence of shallow level defects is reduced, so that the transverse diffusion of charges is inhibited, and the reliability of the memory is improved.
The best doping source disclosed in the present invention is Ti or Hf, and excessive or insufficient doping cannot achieve the purpose of reducing shallow level defects. The small amount of doping can effectively reduce the existence of shallow level defects, for example, when the doping concentration is 1/280 (i.e. one defect is introduced into a supercell in 280 atoms) based on the first principle calculation in the invention, the shallow level defects are effectively reduced.
FIG. 4 is an atomic diagram of a silicon nitride charge trapping layer in a nonvolatile semiconductor memory. 280 atom based crystalline beta-Si3N4And the superlattice structure qualitatively researches the regulation and control effect of metal doping on the defect energy level in the silicon nitride through a first linear principle.
FIG. 5 shows the defect formation energies of various metal atoms doped with silicon nitride, including Ti, Zr, Hf, W, Ru, La, which are the defects associated with several common transition metal atoms as doping sources. In fig. 5(a), when the atomic doping site is an interstitial site, all the defects generated by metal doping are free of shallow level defects. However, when N is substituted, Zr and W replace N atom (Zr)NAnd WN) Shallow defect levels are introduced, as indicated by the arrows in fig. 5 (b). Similarly in FIG. 5(c), La replaces the Si atom (La)Si) Shallow defect energy levels are also introduced, and the doping atoms introducing the shallow defect energy levels are not suitable for being used as goldBelonging to a doping source of doping.
Figure 6 shows a statistical view of the defect levels when different metal atoms are doped with silicon nitride. With shallow defect levels indicated by underlining. It is shown in the graph that doping of metal atoms of Ti, Hf, Ru alone does not introduce shallow defect levels. However, it is noted that fig. 5 shows that Ru-related defects are formed with high energy and are not easily doped during the metal-doped silicon nitride process, so Ru metal atoms are not a suitable doping source. In contrast, not only does Ti or Hf atom doping result in lower energy of formation, but Ti replaces Si atoms (Ti)Si) Has a doping level of about 1.43eV and a gap doping (Hfi) level of about 1.32eV, are very suitable as electron defect levels, while they effectively increase the electron storage density. Therefore, the Ti and Hf metal atoms are suitable to be used as doping sources to realize the regulation and control of the defect energy level.
Fig. 7 is a graph comparing defect levels before and after metal-doped silicon nitride. In the original undoped silicon nitride, there are shallow level defects such as nitrogen vacancy defects (V)N) And nitrogen vacancy defects (V) passivated by oxygen atomsN-O), the defect energy level is about 0.53eV, and the charges stored at the energy level are easy to laterally diffuse, which brings about a problem of reliability of the nonvolatile memory. In the silicon nitride doped with Ti or Hf atoms, the defect levels are mainly 1.43eV and 1.32eV respectively, and no shallow level defect exists. Therefore, the Ti and Hf metal doped silicon nitride effectively reduces the existence of shallow level defects and inhibits the lateral diffusion of charges.
Fig. 8 is a process core flow diagram mainly describing a process flow of preparing a stack layer on the basis of a front-end preparation process, and for a planar 2D NAND preparation process, mainly depositing a tunneling oxide layer, a silicon nitride charge-trapping layer and a blocking oxide layer on a semiconductor substrate in sequence, wherein metal doping is performed when preparing the silicon nitride charge-trapping layer; based on 3D NAND, the preparation flow of the stacked layer mainly comprises the steps of sequentially depositing a barrier oxide layer, a silicon nitride charge trapping layer and a tunneling oxide layer, carrying out metal doping in the silicon nitride deposition process, and keeping the rest preparation process unchanged. The preparation process effectively solves the reliability problem caused by the shallow energy level defect in the silicon nitride.
FIG. 9 is a graph showing device transfer characteristics before and after metal-doped silicon nitride according to an example of the present invention applied to a three-dimensional charge trapping memory. Energy level result Ti calculated based on first sexual principleSi(1.43eV), TCAD simulation simulates the transfer characteristics of a three-dimensional charge-trapping memory. The left dotted line is the IV curve when no data is stored, and the right two lines are the IV curves for the device for the shallow defect level when undoped (0.53eV) and doped (1.43eV), respectively. The memory window of the doped deep level defects becomes significantly larger. Therefore, the metal doped silicon nitride reduces the existence of shallow level defects and effectively improves the performance of the memory.
Fig. 10 is a charge density distribution diagram of the charge stored before and after the metal-doped silicon nitride of the present invention after data retention. Based on the structure of the three-dimensional charge trapping memory, the data retention process thereof was simulated. From the charge density distribution, before the metal is doped with the silicon nitride, charges stored on shallow defect energy levels are obviously diffused, and the charges are diffused from the memory cell areas to the areas between the adjacent memory cells; after the metal is doped with the silicon nitride, the deep energy level defects are taken as the main, and the charges are not obviously diffused transversely, so that the reliability of the memory is ensured.
FIG. 11 is a brief introduction of the application of the present invention to metal-dope a silicon nitride charge trapping layer during the experimental preparation process to control the defect level and suppress the generation of shallow level defects. The non-volatile memory based on the deep defect energy level has a larger storage window on one hand, and the charge loss is restrained on the other hand, so that the performance and the reliability of the memory are improved.
According to the general preparation method of the nonvolatile semiconductor memory, the existence of shallow level defects such as Ti and Hf metal atom doping is effectively reduced through the metal doped silicon nitride charge trapping layer, and a proper trap level (the doping level of Ti replacing Si atoms is about 1.43eV, and the gap doping level of Hf is about 1.32eV) and higher electron storage density can be generated, so that the performance of the memory is improved, and meanwhile, the reliability of the memory is improved.
The invention has instructive significance for guiding the high-reliability optimization design of the nonvolatile semiconductor memory.
Claims (9)
1. A universal preparation method of a non-volatile semiconductor memory is characterized in that metal doping is carried out in the process of preparing a silicon nitride charge trapping layer based on the non-volatile semiconductor memory to form the metal doped silicon nitride charge trapping layer so as to effectively regulate and control the defect energy level of a material and reduce the generation of shallow energy level defects, thereby inhibiting the transverse diffusion of charges, improving the density of charge storage, improving the performance of the non-volatile semiconductor memory and realizing the high reliability of the non-volatile semiconductor memory.
2. The method as claimed in claim 1, wherein the metal doping is carried out by doping metal atoms into the silicon nitride charge trapping layer by evaporation or sputtering during the preparation of the silicon nitride charge trapping layer.
3. The method of claim 1, wherein the metal-doped silicon nitride charge trapping layer is doped to replace an original defect by a defect in an amount that results in a defect level suitable for electron trapping and erasure.
4. The method of claim 1, wherein the metal-doped source is Ti or Hf.
5. The method as claimed in claim 1, wherein the doping concentration of the metal dopant is such that the superlattice introduces a defect in 280 atoms.
6. The method of claim 1, wherein the defect level of the control material is controlled by doping metal atoms to change the type of defects and form new defects suitable for electron trapping and erasure.
7. The method of claim 1, wherein the lateral diffusion of charges is suppressed by reducing the presence of shallow level defects due to metal doping, thereby suppressing lateral diffusion of charges.
8. The method as claimed in claim 1, wherein the step of improving the performance of the non-volatile semiconductor memory is to improve the electron storage density of the doped silicon nitride charge trapping layer, and replace the original shallow level defects with defects suitable for electron trapping and releasing, so as to improve the performance of the non-volatile semiconductor memory.
9. The method according to claim 1, wherein the high reliability of the nonvolatile semiconductor memory is achieved by doping silicon nitride to reduce shallow level defects, thereby suppressing lateral diffusion of charges, reducing charge loss, and improving reliability of the nonvolatile semiconductor memory.
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Application publication date: 20210625 |