CN113035861A - Field effect transistor packaged with integrated circuit - Google Patents

Field effect transistor packaged with integrated circuit Download PDF

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Publication number
CN113035861A
CN113035861A CN202110139393.4A CN202110139393A CN113035861A CN 113035861 A CN113035861 A CN 113035861A CN 202110139393 A CN202110139393 A CN 202110139393A CN 113035861 A CN113035861 A CN 113035861A
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China
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type
doped region
region
type doped
field effect
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CN202110139393.4A
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Chinese (zh)
Inventor
柴力
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Zhongzhi Semiconductor Technology Dongguan Co ltd
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Zhongzhi Semiconductor Technology Dongguan Co ltd
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Priority to CN202110139393.4A priority Critical patent/CN113035861A/en
Publication of CN113035861A publication Critical patent/CN113035861A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The invention provides a field effect transistor packaged with integrated circuit, wherein, two sides of an N-type substrate are provided with an N-type main body and a drain electrode metal layer, and one side of the N-type main body is provided with a source electrode metal layer; the top of the N-type main body is provided with a first P-type doped region and a second P-type doped region which are spaced from each other, the top of the first P-type doped region is provided with a first N-type doped region, the top of the second P-type doped region is provided with a second N-type doped region, and the top of the N-type main body is also provided with a plurality of P-type injection regions; the bottom of the source electrode metal layer is provided with a first insulating layer and a second insulating layer, the first insulating layer is provided with a first gate layer, the second insulating layer is provided with a second gate layer, a first dielectric region is arranged outside the first gate layer, a second dielectric region is arranged outside the second gate layer, and Schottky contact is formed between the source electrode metal layer between the first dielectric region and the second dielectric region and the N-type main body. The Schottky diode is integrated into the field effect transistor, and the Schottky diode has low starting voltage, low impedance and low loss.

Description

Field effect transistor packaged with integrated circuit
Technical Field
The invention relates to a field effect transistor, and particularly discloses a field effect transistor packaged with an integrated circuit.
Background
The field effect transistor is a voltage-controlled semiconductor device, and has the advantages of low noise, low power consumption, large dynamic range, easy integration, no secondary breakdown, wide safe working area and the like.
The field effect transistor is a semiconductor device which controls the current of an output loop by controlling the electric field effect of an input loop, after the field effect transistor is connected with a Schottky diode in parallel, the performance of the field effect transistor such as the alternating frequency characteristic can be effectively improved, the field effect transistor and the Schottky diode are combined and used in the prior art, two independent wafers are usually used in parallel in a circuit through a lead, the occupied space is large, and the using operation is complicated.
Disclosure of Invention
Therefore, it is necessary to provide a field effect transistor packaged with an integrated circuit, which has the parallel performance of a field effect transistor parallel schottky diode, and has a stable and reliable overall structure and a small occupied space.
In order to solve the problems of the prior art, the invention discloses a field effect transistor packaged with an integrated circuit, which comprises an N-type substrate, wherein an N-type main body and a drain metal layer are respectively arranged on the upper side and the lower side of the N-type substrate, and a source metal layer is arranged on one side of the N-type main body, which is far away from the drain metal layer;
the top of the N-type main body is provided with a first P-type doped region and a second P-type doped region which are spaced from each other, the first P-type doped region and the second P-type doped region both extend towards the inside of the N-type main body, the top of the first P-type doped region is provided with a first N-type doped region, the first N-type doped region extends towards the inside of the first P-type doped region, the top of the second P-type doped region is provided with a second N-type doped region, the second N-type doped region extends towards the inside of the second P-type doped region, the top of the N-type main body is also provided with a plurality of P-type injection regions positioned between the first P-type doped region and the second P-type doped region, the P-type injection regions extend towards the inside of the N-type main body, and the top surfaces of the first P-type doped region, the second P-type doped region, the first N-type doped region, the second N-type doped region and the P-type injection regions all;
the bottom of the source metal layer is provided with a first insulating layer and a second insulating layer which are spaced, the first insulating layer is provided with a first gate layer, the second insulating layer is provided with a second gate layer, a first dielectric region is arranged outside the first insulating layer and the first gate layer, a second dielectric region is arranged outside the second insulating layer and the second gate layer, the first dielectric region and the second dielectric region both extend towards the inside of the source metal layer, a gap is formed between the first dielectric region and the second dielectric region, the first dielectric region and the second dielectric region are connected to two ends of the top of the P-type injection region, and Schottky contact is formed between the source metal layer in the gap and the N-type main body below the gap.
Furthermore, a first P-type enrichment region is arranged at the top of the first N-type doping region, a second P-type enrichment region is arranged at the top of the second N-type doping region, the first P-type enrichment region extends into the first P-type doping region towards the inside of the first N-type doping region, and the second P-type enrichment region extends into the second P-type doping region towards the inside of the second N-type doping region.
Furthermore, the N-type substrate is a silicon carbide substrate, and the N-type main body is a silicon carbide epitaxial layer.
Furthermore, the drain metal layer and the source metal layer are both aluminum layers.
Furthermore, the first P-type doped region, the second P-type doped region and the P-type injection region are all aluminum P-type doped layers.
Furthermore, the first N-type doped region and the second N-type doped region are both N-type doped layers of nitrogen or N-type doped layers of phosphorus.
Furthermore, the first insulating layer and the second insulating layer are both silicon dioxide layers.
Furthermore, the first gate layer and the second gate layer are both polysilicon layers.
Further, the first dielectric region and the second dielectric region are both silicon dioxide layers.
The invention has the beneficial effects that: the invention discloses a field effect transistor packaged with an integrated circuit, wherein a Schottky diode is integrated into the field effect transistor by adjusting the structure of a wafer, the performance of the field effect transistor can be effectively improved, the whole structure is stable and reliable, the occupied space is small, the use and the operation are convenient, and the field effect transistor connected with the Schottky diode in parallel has the advantages of low starting voltage, low impedance and low power loss.
Drawings
Fig. 1 is a schematic view of the internal structure of the present invention.
Fig. 2 is a schematic perspective view of the lower half of the present invention.
Fig. 3 is an internal schematic view of an embodiment of the present invention.
Reference numerals: an N-type substrate 10, an N-type body 11, a drain metal layer 12, a source metal layer 20, a first P-type doped region 30, a first N-type doped region 31, a first P-type enriched region 32, a second P-type doped region 40, a second N-type doped region 41, a second P-type enriched region 42, a P-type implanted region 50, a first insulating layer 60, a first gate layer 61, a first dielectric region 62, a second insulating layer 70, a second gate layer 71, a second dielectric region 72, a gap 80.
Detailed Description
For further understanding of the features and technical means of the present invention, as well as the specific objects and functions attained by the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description.
Refer to fig. 1 to 3.
The embodiment of the invention discloses a field effect transistor packaged with an integrated circuit, which comprises an N-type substrate 10, wherein an N-type main body 11 and a drain metal layer 12 are respectively arranged at the upper side and the lower side of the N-type substrate 10, a source metal layer 20 is arranged at one side of the N-type main body 11, which is far away from the drain metal layer 12, the drain metal layer 12 is coupled to a drain terminal of the field effect transistor after plastic packaging, and the source metal layer 20 is coupled to a source terminal of the field effect transistor after plastic packaging;
the top of the N-type body 11 is provided with a first P-type doped region 30 and a second P-type doped region 40 which are spaced apart from each other, the first P-type doped region 30 and the second P-type doped region 40 both extend towards the inside of the N-type body 11, the top of the first P-type doped region 30 is provided with a first N-type doped region 31, the first N-type doped region 31 extends towards the inside of the first P-type doped region 30, the top of the second P-type doped region 40 is provided with a second N-type doped region 41, the second N-type doped region 41 extends towards the inside of the second P-type doped region 40, the top of the N-type body 11 is further provided with a plurality of P-type injection regions 50 which are positioned between the first P-type doped region 30 and the second P-type doped region 40, the P-type injection regions 50 extend towards the inside of the N-type body 11, the top of the first P-type doped region 30, the top of the second P-type doped region 40, the top of the first N-type doped region 31, the top of the second N-type doped region 41 and the top of the P-type doped region 50 all, a field effect working region is formed between the first P-type doped region 30 and the second P-type doped region 40;
the bottom of the source metal layer 20 is provided with a first insulating layer 60 and a second insulating layer 70 which are spaced apart, preferably, a portion of the first insulating layer 60 is connected to the first P-type doped layer and the first N-type doped region 31, a portion of the second insulating layer 70 is connected to the second P-type doped layer and the second N-type doped region 41, a first gate layer 61 is provided on the first insulating layer 60, a second gate layer 71 is provided on the second insulating layer 70, the first gate layer 61 and the second gate layer 71 are both coupled to the gate terminal of the present invention, the same first dielectric region 62 is provided outside the first insulating layer 60 and the first gate layer 61, the same second dielectric region 72 is provided outside the second insulating layer 70 and the second gate layer 71, the first dielectric region 62 and the second dielectric region 72 both extend to the inside of the source metal layer 20, the first insulating layer 60 and the first gate layer 61 both extend to the inside of the first dielectric region 62, the second insulating layer 70 and the second gate layer 71 both extend to the inside of the second dielectric region 72, a gap 80 is formed between the first dielectric region 62 and the second dielectric region 72, the first dielectric region 62 and the second dielectric region 72 are connected to both ends of the top of the P-type injection region 50, that is, part of the structure of the first dielectric region 62 is located above the P-type injection region 50, part of the structure of the second dielectric region 72 is located above the P-type injection region 50, a schottky contact is formed between the source metal layer 20 in the gap 80 and the N-type body 11 below the gap 80, and an ohmic contact is formed between the source metal layer 20 in the gap 80 and the P-type injection region 50.
The invention integrates a Schottky diode in a field effect transistor, and the actual circuit structure is as follows: the source of the fet is coupled to the anode of the schottky diode as the source metal layer 20, the drain of the fet is coupled to the cathode of the schottky diode as the drain metal layer 12, and the two second gate layers 71 are coupled to form the gates. The invention has low starting voltage, wide application range, low impedance, low power loss and high efficiency working performance; the field effect transistor and the Schottky diode are packaged in the same wafer and are reflected by corresponding functions, so that the space can be effectively saved, the overall structure size is small, and the circuit layout is convenient.
In the present embodiment, as shown in fig. 3, a first P-type enrichment region 32 is disposed on the top of the first N-type doped region 31, a second P-type enrichment region 42 is disposed on the top of the second N-type doped region 41, the first P-type enrichment region 32 extends into the first P-type doped region 30 towards the inside of the first N-type doped region 31, and the second P-type enrichment region 42 extends into the second P-type doped region 40 towards the inside of the second N-type doped region 41, so as to further improve the performance of the field effect transistor, preferably, the first P-type enrichment region 32 and the second P-type enrichment region 42 are both aluminum P-type doped layers.
In the present embodiment, the N-type substrate 10 is a silicon carbide substrate, the N-type body 11 is a silicon carbide epitaxial layer, and silicon carbide is an N-type semiconductor material having good thermal conductivity.
In this embodiment, the drain metal layer 12 and the source metal layer 20 are both aluminum layers.
In the present embodiment, the first P-type doped region 30, the second P-type doped region 40 and the P-type implanted region 50 are all aluminum P-type doped layers.
In the present embodiment, the first N-type doped region 31 and the second N-type doped region 41 are both N-type doped layers of nitrogen or phosphorus.
In the present embodiment, the first insulating layer 60 and the second insulating layer 70 are both silicon dioxide layers.
In the present embodiment, the first gate layer 61 and the second gate layer 71 are both polysilicon layers.
In the present embodiment, the first dielectric region 62 and the second dielectric region 72 are both silicon dioxide layers.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (9)

1. The field effect transistor packaged with the integrated circuit is characterized by comprising an N-type substrate (10), wherein an N-type main body (11) and a drain metal layer (12) are respectively arranged on the upper side and the lower side of the N-type substrate (10), and a source metal layer (20) is arranged on one side, away from the drain metal layer (12), of the N-type main body (11);
the top of the N-type body (11) is provided with a first P-type doped region (30) and a second P-type doped region (40) which are spaced from each other, the first P-type doped region (30) and the second P-type doped region (40) both extend towards the inside of the N-type body (11), the top of the first P-type doped region (30) is provided with a first N-type doped region (31), the first N-type doped region (31) extends towards the inside of the first P-type doped region (30), the top of the second P-type doped region (40) is provided with a second N-type doped region (41), the second N-type doped region (41) extends towards the inside of the second P-type doped region (40), the top of the N-type body (11) is further provided with a plurality of P-type injection regions (50) which are positioned between the first P-type doped region (30) and the second P-type doped region (40), and the P-type injection regions (50) extend towards the inside of the N-type body (11), the top surfaces of the first P-type doped region (30), the second P-type doped region (40), the first N-type doped region (31), the second N-type doped region (41) and the P-type injection region (50) all penetrate through the top surface of the N-type main body (11);
a first insulating layer (60) and a second insulating layer (70) are arranged at intervals at the bottom of the source metal layer (20), a first gate layer (61) is arranged on the first insulating layer (60), a second gate layer (71) is arranged on the second insulating layer (70), a first dielectric region (62) is arranged outside the first insulating layer (60) and the first gate layer (61), a second dielectric region (72) is arranged outside the second insulating layer (70) and the second gate layer (71), the first dielectric region (62) and the second dielectric region (72) both extend towards the inside of the source metal layer (20), a gap (80) is formed between the first dielectric region (62) and the second dielectric region (72), the first dielectric region (62) and the second dielectric region (72) are connected to the two ends of the top of the P-type injection region (50), and the source metal layer (20) in the gap (80) and the N under the gap (80) are arranged at intervals Schottky contact is formed between the bodies (11).
2. The integrated circuit packaged field effect transistor of claim 1, wherein a top of the first N-type doped region (31) is provided with a first P-type rich region (32), a top of the second N-type doped region (41) is provided with a second P-type rich region (42), the first P-type rich region (32) extends into the first P-type doped region (30) towards an interior of the first N-type doped region (31), and the second P-type rich region (42) extends into the second P-type doped region (40) towards an interior of the second N-type doped region (41).
3. A field effect transistor packaged with an integrated circuit according to claim 1, characterized in that the N-type base plate (10) is a silicon carbide substrate and the N-type body (11) is a silicon carbide epitaxial layer.
4. A field effect transistor packaged with an integrated circuit according to claim 1, characterized in that the drain metal layer (12) and the source metal layer (20) are both aluminium layers.
5. The integrated circuit packaged field effect transistor of claim 1, wherein the first P-doped region (30), the second P-doped region (40), and the P-implant region (50) are all P-doped layers of aluminum.
6. The field effect transistor packaged with an integrated circuit according to claim 1, wherein the first N-doped region (31) and the second N-doped region (41) are both N-doped layers of nitrogen or P.
7. A field effect transistor packaged with an integrated circuit according to claim 1, characterized in that the first insulating layer (60) and the second insulating layer (70) are both silicon dioxide layers.
8. A field effect transistor packaged with an integrated circuit according to claim 1, wherein the first gate layer (61) and the second gate layer (71) are both polysilicon layers.
9. A field effect transistor packaged with an integrated circuit according to claim 1, characterized in that said first dielectric region (62) and said second dielectric region (72) are both silicon dioxide layers.
CN202110139393.4A 2021-02-01 2021-02-01 Field effect transistor packaged with integrated circuit Pending CN113035861A (en)

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Application Number Priority Date Filing Date Title
CN202110139393.4A CN113035861A (en) 2021-02-01 2021-02-01 Field effect transistor packaged with integrated circuit

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Application Number Priority Date Filing Date Title
CN202110139393.4A CN113035861A (en) 2021-02-01 2021-02-01 Field effect transistor packaged with integrated circuit

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105304708A (en) * 2014-07-31 2016-02-03 瀚薪科技股份有限公司 Silicon carbide semiconductor element
CN110459540A (en) * 2019-07-30 2019-11-15 创能动力科技有限公司 The semiconductor device and its manufacturing method of integrated MOSFET and diode

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105304708A (en) * 2014-07-31 2016-02-03 瀚薪科技股份有限公司 Silicon carbide semiconductor element
CN110459540A (en) * 2019-07-30 2019-11-15 创能动力科技有限公司 The semiconductor device and its manufacturing method of integrated MOSFET and diode

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