CN113035854A - Integrated chip, manufacturing method thereof, full-color integrated chip and display panel - Google Patents
Integrated chip, manufacturing method thereof, full-color integrated chip and display panel Download PDFInfo
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Abstract
The invention provides an integrated chip and a manufacturing method thereof, a full-color integrated chip and a display panel, wherein the manufacturing method of the integrated chip is used for forming and processing an electrode structure of the integrated chip, and comprises the steps of S1, manufacturing a light-emitting part, enabling the light-emitting part to comprise a plurality of light-emitting unit groups distributed in a matrix form, and S2, respectively and electrically leading out conductive ends from a plurality of first electrodes and a plurality of second electrodes of the light-emitting part to form a plurality of first pin electrodes and a plurality of second pin electrodes, wherein the first pin electrodes and the second pin electrodes are used for being electrically connected with a circuit substrate. The invention mainly aims to solve the problems that the manufacturing process of a Micro LED display panel in the prior art is complicated, the production and processing efficiency of the display panel is greatly reduced, the production period of a display screen is influenced, and the yield of finished products of the display panel is reduced due to the fact that the yield of laid chips is too low, so that the production efficiency of the display screen is low.
Description
Technical Field
The invention relates to the technical field of display, in particular to an integrated chip, a manufacturing method of the integrated chip, a full-color integrated chip and a display panel.
Background
Compared with an LCD and an OLED, the Micro LED display has obvious advantages in the aspects of high brightness, fast response time, high resolution, high color gamut, long service life and the like, so that the Micro LED display brings a technical revolution to the technical field of display.
In the manufacturing process of the Micro LED display panel, a large number of chips need to be sequentially laid on a circuit substrate in a chip transferring mode, the manufacturing process of the display panel is complicated due to frequent chip transferring operation, the production and processing efficiency of the display panel is greatly reduced, the production period of the display screen is influenced, the finished product qualification rate of the display panel is reduced due to too low yield of laid chips, and the production efficiency of the display screen is low.
In addition, when the size of the light emitting chip is small, the distance between the positive electrode and the negative electrode of the light emitting chip becomes small, and the requirements for the processing precision of the circuit substrate and the die bonding process are increased. Meanwhile, when the size of a single light-emitting chip is small, each light-emitting chip is provided with a positive electrode and a negative electrode, each light-emitting chip needs to be independently controlled, when the number of the light-emitting chips on the substrate is large, the design complexity of the circuit substrate is increased, and the design difficulty of the substrate is increased.
Disclosure of Invention
The invention mainly aims to provide an integrated chip and a manufacturing method thereof, a full-color integrated chip and a display panel, and aims to solve the problems that the manufacturing process of a Micro LED display panel in the prior art is complicated, the production and processing efficiency of the display panel is greatly reduced, the production period of a display screen is influenced, and the yield of finished products of the display panel is reduced due to the fact that the yield of laid chips is too low, so that the production efficiency of the display screen is low. In addition, the integrated chip adopts a common electrode structure, compared with the traditional mode that the light-emitting chip adopts independent electrodes, the number of the electrodes of the whole integrated chip is reduced, and the area of a single electrode is increased; the integrated chip has the characteristics of small wiring quantity, low transfer difficulty, low design difficulty of a circuit substrate of the display panel, low requirement on processing precision of the circuit substrate and the like, and has good practicability.
In order to achieve the above object, according to an aspect of the present invention, there is provided a method for manufacturing an integrated chip, for forming an electrode structure of the integrated chip, including: step S1, fabricating a light emitting portion, where the light emitting portion includes n × m light emitting unit groups distributed in a matrix, where n is a number of rows and m is a number of columns, and both n and m are positive integers greater than or equal to 1, each light emitting unit group includes x × y light emitting units distributed in a matrix, where x is a number of rows and y is a number of columns, and both x and y are positive integers greater than or equal to 1, and each light emitting unit includes an a-electrode and a b-electrode; respectively electrically connecting the a-pole electrodes of the light-emitting units in the same row of the light-emitting unit group together to form m × y first electrodes, and respectively electrically connecting the b-pole electrodes of the light-emitting units in the same row of the light-emitting unit group together to form n × x second electrodes; step S2, electrically leading out conductive terminals from the m × y first electrodes and the n × x second electrodes respectively to form m × y first pin electrodes and n × x second pin electrodes, where the first pin electrodes and the second pin electrodes are used to be electrically connected with the circuit substrate.
Further, the a-electrodes of the light emitting cells in the same column of the light emitting cell group are electrically connected to each other by evaporation or deposition to form m × y first electrodes,
and electrically connecting the b-pole electrodes of the light-emitting units in the same row of the light-emitting unit group respectively by using an evaporation or deposition mode to form n x second electrodes.
Further, step S2 includes: step S21, electrically leading out conductive ends from the m × y first electrodes to the peripheral edges of the integrated chip respectively to form m × y first pin electrodes; step S22, leading out conductive ends from the n x second electrodes to the peripheral edge of the integrated chip to form n x second pin electrodes; and m x y first lead electrodes and n x second lead electrodes are sequentially distributed at intervals around the edge of the integrated chip.
Further, in step S22, m and n are both set to 2, x is set to 3, y is set to 1, and the two first electrodes and the six second electrodes are led out to the peripheral edge of the integrated chip to form two first pin electrodes and six second pin electrodes.
Further, in step S2, N insulating protective layers are deposited or evaporated on the surfaces of the light emitting section where the first electrode and the second electrode are located; sequentially arranging metal circuit layers on the surfaces of the insulating protection layers far away from the first electrode and the second electrode by using an evaporation or deposition method to form N metal circuit layers; the first electrode, the second electrode and the N layers of metal circuit layers are electrically connected through metal through holes in the insulating protective layer, wherein N is a positive integer greater than or equal to 2.
Furthermore, an insulating layer is arranged on one side, far away from the insulating protective layer, of the Nth metal circuit layer, and the insulating layer covers the metal wiring and the metal via hole on the Nth metal circuit layer.
Further, the nth metal circuit layer includes m × y first lead electrodes and N × x second lead electrodes.
Furthermore, an identification mark for identifying the polarity of the first pin electrode or the polarity of the second pin electrode is arranged on the insulating protective layer which is in contact with the Nth layer of metal circuit layer.
Further, the insulating protective layer is a silicon dioxide layer or a silicon nitride layer.
Further, the insulating protective layer is formed by printing, deposition, or evaporation.
According to another aspect of the present invention, an integrated chip is provided, which is manufactured by the above-mentioned method for manufacturing an integrated chip.
According to another aspect of the present invention, there is provided a full-color integrated chip, including: the integrated chip described above; the light processing part is arranged above the integrated chip and comprises a red quantum dot base element, a green quantum dot base element and a light-transmitting complementary color element, and a retaining wall is arranged between any two adjacent elements in the red quantum dot base element, the green quantum dot base element and the light-transmitting complementary color element.
Furthermore, the integrated chip is a blue light integrated chip, and the light-transmitting complementary color element is a transparent scattering quantum dot layer.
Furthermore, the integrated chip is an ultraviolet light integrated chip, and the light-transmitting complementary color element is a blue quantum dot layer.
According to another aspect of the present invention, there is provided a display panel including: the integrated chip is the integrated chip, and the integrated chips are arranged on the circuit substrate in a matrix form; and the packaging adhesive layer covers the circuit substrate and packages the integrated chips.
According to another aspect of the present invention, there is provided a display panel including: the full-color integrated chip is arranged on the circuit substrate in a matrix form; and the packaging adhesive layer covers the circuit substrate and packages the full-color integrated chips.
By applying the technical scheme of the invention, the integrated chip with a novel structure is manufactured by providing the specific integrated chip manufacturing method, the electrode structure of the integrated chip can be quickly and conveniently manufactured, the light-emitting characteristic of the integrated chip can be ensured, the light-emitting performance of the display panel is ensured, and the integrated chip has a plurality of light-emitting points in an integrated form, so that the frequency of transferring the integrated chip is greatly reduced in the process of manufacturing the display panel, the production and processing efficiency of the display panel is improved, the production period of the display screen is shortened, the reduction of the finished product qualification rate of the display panel due to the over-low yield of the laid chip is avoided, and the production efficiency of the display screen is improved. In addition, the integrated chip adopts a common-electrode structure, and compared with the traditional mode that the light-emitting chip adopts independent electrodes, the number of the electrodes of the whole integrated chip is reduced; the integrated chip has the characteristics of small wiring quantity, low transfer difficulty, low design difficulty of a circuit substrate of the display panel, low requirement on processing precision of the circuit substrate and the like, and has good practicability.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a schematic view showing a distribution state of a plurality of first electrodes, a plurality of second electrodes, and a plurality of light emitting cell groups in a process of fabricating a light emitting part of an integrated chip according to an alternative embodiment of the present invention;
fig. 2 is a schematic view showing a distribution state of a plurality of first electrodes and a plurality of second electrodes of fig. 1 after covering a plurality of light emitting cell groups;
fig. 3 is a schematic diagram illustrating a distribution state of the plurality of first pin electrodes and the plurality of second pin electrodes after the plurality of first electrodes and the plurality of second electrodes in fig. 2 electrically lead out the conductive terminals to the peripheral edge of the integrated chip;
FIG. 4 is a schematic diagram illustrating the distribution of the first and second pin electrodes after the electrical lead-out structure is covered in FIG. 3;
fig. 5 is a schematic diagram illustrating distribution states of a plurality of first lead electrodes and a plurality of second lead electrodes in a process of fabricating a light emitting portion of an integrated chip according to another alternative embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides an integrated chip and a manufacturing method thereof, a full-color integrated chip and a display panel, aiming at solving the problems that the manufacturing process of a Micro LED display panel in the prior art is complicated, the production and processing efficiency of the display panel is greatly reduced, the production period of a display screen is influenced, and the yield of laid chips is too low, so that the finished product qualification rate of the display panel is reduced, and the production efficiency of the display screen is low; the display panel includes a circuit substrate and a plurality of integrated chips or a plurality of full-color integrated chips disposed thereon, where the integrated chips are the integrated chips described above and below, and the full-color integrated chips include the integrated chips described above and below.
As shown in fig. 1 and fig. 2, the method for manufacturing an integrated chip is used for forming and processing an electrode structure of the integrated chip, and includes: step S1, fabricating a light emitting portion, where the light emitting portion includes n × m light emitting unit groups distributed in a matrix, where n is a number of rows and m is a number of columns, and both n and m are positive integers greater than or equal to 1, each light emitting unit group includes x × y light emitting units distributed in a matrix, where x is a number of rows and y is a number of columns, and both x and y are positive integers greater than or equal to 1, and each light emitting unit includes an a-electrode and a b-electrode; respectively electrically connecting the a-pole electrodes of the light-emitting units in the same row of the light-emitting unit group together to form m × y first electrodes, and respectively electrically connecting the b-pole electrodes of the light-emitting units in the same row of the light-emitting unit group together to form n × x second electrodes; step S2, electrically leading out conductive terminals from the m × y first electrodes and the n × x second electrodes respectively to form m × y first pin electrodes and n × x second pin electrodes, where the first pin electrodes and the second pin electrodes are used to be electrically connected with the circuit substrate.
The application manufactures the integrated chip of a novel structure by providing a manufacturing method of a specific integrated chip, the electrode structure of the integrated chip can be quickly and conveniently manufactured, the light-emitting characteristic of the integrated chip can be ensured, the light-emitting performance of the display panel can be ensured, and the integrated chip is enabled to have a plurality of light-emitting points in an integrated form, so that in the process of manufacturing the display panel, the times of transferring the integrated chip are greatly reduced, the production and processing efficiency of the display panel is improved, the production period of the display screen is shortened, the problem that the yield of laying the chip is too low and the finished product qualification rate of the display panel is reduced is avoided, and the production efficiency of the display screen is improved. In addition, the integrated chip adopts a common-electrode structure, and compared with the traditional mode that the light-emitting chip adopts independent electrodes, the number of the electrodes of the whole integrated chip is reduced; the integrated chip has the characteristics of small wiring quantity, low transfer difficulty, low design difficulty of a circuit substrate of the display panel, low requirement on processing precision of the circuit substrate and the like, and has good practicability.
Alternatively, the a-pole electrodes of the light emitting cells in the same column of the light emitting cell group are electrically connected by evaporation or deposition to form m × y first electrodes, and the b-pole electrodes of the light emitting cells in the same row of the light emitting cell group are electrically connected by evaporation or deposition to form n × x second electrodes. Therefore, the processing and manufacturing cost of the integrated chip is controlled, and the polarity and stability of the first electrode and the second electrode can be ensured.
As shown in fig. 3, step S2 includes: step S21, electrically leading out conductive ends from the m × y first electrodes to the peripheral edges of the integrated chip respectively to form m × y first pin electrodes; step S22, leading out conductive ends from the n x second electrodes to the peripheral edge of the integrated chip to form n x second pin electrodes; and m x y first lead electrodes and n x second lead electrodes are sequentially distributed at intervals around the edge of the integrated chip. Therefore, the spacing distance between two adjacent pin electrodes can be conveniently controlled, the electrical interference between the pin electrodes is avoided, the circuit stability of the integrated chip is ensured, and the imaging reliability of the display panel is improved.
In the illustrated embodiment of the present application, in step S22, m and n are both set to 2, x is set to 3, y is set to 1, and two first electrodes and six second electrodes are led out of conductive terminals to the peripheral edge of the integrated chip to form two first pin electrodes and six second pin electrodes. The integrated chip with the structure is convenient to process and manufacture, and the first electrode and the second electrode are easily electrically guided to form the pin electrode, so that the electrical connection and installation of the integrated chip are ensured.
In step S2, N insulating protective layers are deposited or evaporated on the surfaces of the light-emitting section where the first electrode and the second electrode are located; sequentially arranging metal circuit layers on the surfaces of the insulating protection layers far away from the first electrode and the second electrode by using an evaporation or deposition method to form N metal circuit layers; the first electrode, the second electrode and the N layers of metal circuit layers are electrically connected through metal through holes in the insulating protective layer, wherein N is a positive integer greater than or equal to 2. In this way, it is advantageous to arrange the electrodes of the integrated chip according to design requirements.
It should be further noted that an insulating layer is disposed on one side of the nth metal circuit layer, which is far away from the insulating protection layer, and the insulating layer covers the metal traces and the metal vias on the nth metal circuit layer. Therefore, the electric stability of the integrated chip is facilitated, and the integrated chip is ensured to be stably lightened.
Optionally, the nth metal wiring layer includes m × y first lead electrodes and N × x second lead electrodes.
As shown in fig. 4 and 5, an identification mark for identifying the polarity of the first lead electrode or the polarity of the second lead electrode is provided on the insulating protective layer in contact with the nth metal wiring layer. Therefore, the polarity of the first pin electrode and the polarity of the second pin electrode can be accurately identified, and the positions of the first pin electrode and the second pin electrode can be accurately known.
In fig. 4, the plurality of first lead electrodes and the plurality of second lead electrodes are sequentially spaced around the edge of the integrated chip; in this figure, the two pin electrodes labeled 3 and 4 are first pin electrodes and the first pin electrode is a negative electrode, the six pin electrodes labeled 1, 2, and 5 through 8 are second pin electrodes and the second pin electrode is a positive electrode.
In fig. 5, the first lead electrode is located at the end of the first electrode in the length direction, and the second lead electrode is located at the middle or the end of the second electrode in the length direction; therefore, on the premise of ensuring that the two adjacent pin electrodes have a safe distance, the complexity of processing and generating the integrated chip is greatly reduced. In this figure, the two pin electrodes labeled 2 and 7 are first pin electrodes and the first pin electrodes are negative, the six pin electrodes labeled 1, 3 through 6, and 8 are second pin electrodes and the second pin electrodes are positive.
Optionally, the insulating protection layer is a silicon dioxide layer or a silicon nitride layer.
The insulating protective layer is formed by printing, deposition or evaporation in consideration of the economical manufacture of the integrated chip.
In the illustrated embodiment of the present application, the integrated chip is manufactured by the above-mentioned method for manufacturing an integrated chip; the full-color integrated chip comprises the integrated chip and the light processing part, wherein the light processing part is arranged above the integrated chip and comprises a red quantum dot base element, a green quantum dot base element and a light-transmitting complementary color element, and a retaining wall is arranged between any two adjacent elements in the red quantum dot base element, the green quantum dot base element and the light-transmitting complementary color element. Thus, the integrated chip is ensured to have a characteristic of stably emitting white light.
Optionally, the integrated chip is a blue light integrated chip, and the light-transmitting complementary color element is a transparent scattering quantum dot layer.
Of course, it is also optional that the integrated chip is an ultraviolet light integrated chip and the light-transmissive complementary color cell is a blue quantum dot layer.
In an optional embodiment of the display panel, the display panel includes a circuit substrate, a plurality of integrated chips and a packaging adhesive layer, where the integrated chips are the above-mentioned integrated chips, and the integrated chips are arranged on the circuit substrate in a matrix form; the packaging adhesive layer covers the circuit substrate and packages the integrated chips.
In another optional embodiment of the present application, the display panel includes a circuit substrate, a plurality of full-color integrated chips and a packaging adhesive layer, where the full-color integrated chips are the above-mentioned full-color integrated chips, and the plurality of full-color integrated chips are disposed on the circuit substrate in a matrix form; the packaging adhesive layer covers the circuit substrate and packages the full-color integrated chips.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
The relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Spatially relative terms, such as "above … …," "above … …," "above … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise variously oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular is intended to include the plural unless the context clearly dictates otherwise, and it should be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of features, steps, operations, devices, components, and/or combinations thereof.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (16)
1. A manufacturing method of an integrated chip is used for forming and processing an electrode structure of the integrated chip, and is characterized by comprising the following steps:
step S1, fabricating a light emitting portion, where the light emitting portion includes n × m light emitting unit groups distributed in a matrix, where n is a number of rows, m is a number of columns, and n and m are positive integers greater than or equal to 1, each of the light emitting unit groups includes x × y light emitting units distributed in a matrix, where x is a number of rows, y is a number of columns, and x and y are positive integers greater than or equal to 1, and each of the light emitting units includes an a-electrode and a b-electrode; respectively electrically connecting the a-pole electrodes of the light-emitting units in the same row of the light-emitting unit group together to form m × y first electrodes, and respectively electrically connecting the b-pole electrodes of the light-emitting units in the same row of the light-emitting unit group together to form n × x second electrodes;
step S2, electrically leading out conductive ends of the m × y first electrodes and the n × x second electrodes respectively to form m × y first pin electrodes and n × x second pin electrodes, where the first pin electrodes and the second pin electrodes are used to be electrically connected to the circuit substrate.
2. The method of claim 1, wherein the first and second substrates are different from each other,
electrically connecting the a-pole electrodes of the light emitting cells in the same row of the light emitting cell group by evaporation or deposition to form m x y first electrodes,
and electrically connecting the b-pole electrodes of the light-emitting units in the same row of the light-emitting unit group in the same row respectively by using an evaporation or deposition mode to form n x second electrodes.
3. The method for manufacturing an integrated chip according to claim 1, wherein the step S2 includes:
step S21, electrically leading out conductive terminals from the m × y first electrodes to the peripheral edges of the integrated chip, respectively, to form m × y first pin electrodes;
step S22, electrically leading out conductive terminals from the n × x second electrodes to the peripheral edges of the integrated chip, respectively, to form n × x second pin electrodes;
and sequentially distributing the m x y first pin electrodes and the n x second pin electrodes at intervals around the edge of the integrated chip.
4. The method for manufacturing an integrated chip according to claim 3, wherein in step S22, m and n are both set to 2, x is set to 3, y is set to 1, and two of the first electrodes and six of the second electrodes are led out to the peripheral edge of the integrated chip to form the two of the first pin electrodes and six of the second pin electrodes.
5. The method of claim 1, wherein in step S2, N insulating protective layers are deposited or evaporated on the surfaces of the light-emitting part where the first and second electrodes are located; sequentially arranging a metal circuit layer on the surface of the insulating protection layer far away from the first electrode and the second electrode by using an evaporation or deposition method to form N metal circuit layers; the first electrode, the second electrode and the N metal circuit layers are electrically connected through the metal through holes in the insulating protective layer, wherein N is a positive integer greater than or equal to 2.
6. The method according to claim 5, wherein an insulating layer is disposed on a side of the Nth metal line layer away from the insulating protection layer, and the insulating layer covers the metal traces and the metal vias on the Nth metal line layer.
7. The method of claim 5, wherein the Nth metal wiring layer comprises m x y first lead electrodes and N x second lead electrodes.
8. The method of claim 5, wherein an identification mark for identifying the polarity of the first lead electrode or the polarity of the second lead electrode is disposed on the insulating protection layer in contact with the Nth metal wiring layer.
9. The method of claim 5, wherein the insulating protective layer is a silicon dioxide layer or a silicon nitride layer.
10. The method of claim 5, wherein the insulating protective layer is formed by printing, deposition or evaporation.
11. An integrated chip manufactured by the method for manufacturing an integrated chip according to any one of claims 1 to 10.
12. A full-color integrated chip, comprising:
the integrated chip of claim 11;
the light processing part is arranged above the integrated chip and comprises a red quantum dot base element, a green quantum dot base element and a light-transmitting complementary color element, and a retaining wall is arranged between any two adjacent elements in the red quantum dot base element, the green quantum dot base element and the light-transmitting complementary color element.
13. The full-color integrated chip according to claim 12, wherein the integrated chip is a blue light integrated chip, and the light-transmissive complementary color element is a transparent scattering quantum dot layer.
14. The full-color integrated chip according to claim 12, wherein the integrated chip is an ultraviolet integrated chip, and the light-transmissive complementary color element is a blue quantum dot layer.
15. A display panel, comprising:
a circuit substrate and a plurality of integrated chips, said integrated chips being the integrated chips of claim 11, a plurality of said integrated chips being disposed in a matrix on said circuit substrate;
and the packaging adhesive layer covers the circuit substrate and packages the integrated chips.
16. A display panel, comprising:
a circuit substrate and a plurality of full-color integrated chips, the full-color integrated chips being as defined in any one of claims 12 to 14, the plurality of full-color integrated chips being provided in a matrix on the circuit substrate;
and the packaging adhesive layer covers the circuit substrate and packages the full-color integrated chip in a plurality of ways.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911358755.8A CN113035854A (en) | 2019-12-25 | 2019-12-25 | Integrated chip, manufacturing method thereof, full-color integrated chip and display panel |
| US17/788,151 US20230029972A1 (en) | 2019-12-25 | 2020-12-18 | Integrated chip and manufacturing method therefor, and full-color integrated chip and display panel |
| PCT/CN2020/137776 WO2021129542A1 (en) | 2019-12-25 | 2020-12-18 | Integrated chip and manufacturing method therefor, and full-color integrated chip and display panel |
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| CN201911358755.8A CN113035854A (en) | 2019-12-25 | 2019-12-25 | Integrated chip, manufacturing method thereof, full-color integrated chip and display panel |
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| CN113035854A true CN113035854A (en) | 2021-06-25 |
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