CN113035804A

CN113035804A - Semiconductor packaging device

Info

Publication number: CN113035804A
Application number: CN202110230646.9A
Authority: CN
Inventors: 萧敬霖; 王铭汉
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2021-03-02
Filing date: 2021-03-02
Publication date: 2021-06-25

Abstract

The present disclosure relates to semiconductor packaging devices. The semiconductor package device includes: the chip layer comprises a first chip and a second chip, and a first underfill material is arranged in a gap between the first chip and the second chip; the heat dissipation piece is located on the surface of the chip layer, a first through hole in the vertical direction is formed in the heat dissipation piece, and the first through hole is located at a position corresponding to the first bottom filling material. The semiconductor packaging device removes the part of the heat dissipation part, which is positioned on the upper surface of the first bottom filling material, so that the first bottom filling material is prevented from generating tensile stress due to large thermal expansion generated when the first bottom filling material is heated, the first bottom filling material can be prevented from being broken, and the product yield is improved on the premise of ensuring the heat dissipation effect of the structure.

Description

Semiconductor packaging device

Technical Field

The present disclosure relates to the field of semiconductor packaging devices, and more particularly, to a semiconductor packaging device.

Background

The FOCoS (Fan Out Chip on Substrate) packaging technology is implemented by using Fan-Out composite chips on a typical ball grid array Substrate. It can provide a lower cost solution with practically better electrical and thermal performance than silicon interposer structures.

In the FOCoS package structure, the Coefficients of Thermal Expansion (CTE) of the heat dissipation element and the substrate are both greater than those of the internal structure (e.g., the chip and the underfill), so that when heated, the internal structure is pulled outward due to the greater CTE of the heat dissipation element and the substrate, and is subjected to a greater tensile stress. In addition, since the thermal expansion coefficient of the heat dissipation element is generally larger than that of the substrate, the thermal expansion amount of the heat dissipation element is larger than that of the substrate when the same temperature change occurs, and the internal structure (e.g., underfill material) between the two is easily broken by tensile stress caused by the large thermal expansion amount of the heat dissipation element.

Therefore, it is necessary to provide a new FOCoS package solution.

Disclosure of Invention

The present disclosure provides a semiconductor package device.

The semiconductor package device provided by the present disclosure includes:

the chip layer comprises a first chip and a second chip, and a first underfill material is arranged in a gap between the first chip and the second chip;

the heat dissipation piece is located on the surface of the chip layer, a first through hole in the vertical direction is formed in the heat dissipation piece, and the first through hole is located at a position corresponding to the first bottom filling material.

In some optional embodiments, a ratio of a contact area of the heat spreader to the first chip to an upper surface area of the first chip is greater than 0.9.

In some alternative embodiments, an extension direction of a horizontal cross section of the first through hole coincides with an extension direction of a gap between the first chip and the second chip.

In some alternative embodiments, the extension of the horizontal cross section of the first through hole is greater than the extension of the gap between the first chip and the second chip.

In some alternative embodiments, the first via exposes an upper surface of the first underfill material.

In some alternative embodiments, the first via exposes an upper surface of the first underfill material and an upper surface of the second chip.

In some alternative embodiments, the first through hole includes an arc portion at an end of the first through hole.

In some alternative embodiments, the first through-hole includes a saw-tooth shaped portion.

In some alternative embodiments, the first through-hole includes a fence-type portion.

In some optional embodiments, a second through hole in a vertical direction is further disposed on the heat sink, a horizontal cross section of the second through hole extends in a direction perpendicular to a gap between the first chip and the second chip, and the second through hole is communicated with the first through hole.

In some alternative embodiments, the first through-hole and the second through-hole are integrally cross-shaped.

In some alternative embodiments, the number of the second chips is at least two, at least two of the second chips are juxtaposed on the same side of the first chip, and a gap between at least two of the second chips is provided with a second underfill material; and

the second via is located in a region corresponding to the second underfill material.

In some alternative embodiments, an adhesive layer is disposed between the heat spreader and the chip layer.

In some alternative embodiments, the adhesive layer is a thermally conductive material.

In some alternative embodiments, the heat sink has vertically oriented side walls.

In some optional embodiments, the chip layer further comprises an encapsulant around the first chip and the second chip.

In some optional embodiments, the semiconductor package device further comprises a fan-out wiring layer, and the chip layer is disposed on the fan-out wiring layer.

In some optional embodiments, the semiconductor package device further comprises a substrate, and the fan-out line layer is located on the substrate.

In some alternative embodiments, a third underfill material is disposed between the fan-out wiring layer and the substrate.

In some alternative embodiments, the first through hole is covered with an arc-shaped top.

In the semiconductor packaging device disclosed by the disclosure, the first through hole in the vertical direction is arranged at the position, corresponding to the first underfill material, on the heat dissipation member, the part, located on the upper surface of the first underfill material, of the heat dissipation member is removed, so that the first underfill material is prevented from generating tensile stress due to large thermal expansion generated when the first underfill material is heated, the first underfill material can be prevented from being broken, and the improvement of the product yield is facilitated on the premise of ensuring the heat dissipation effect of the structure.

Drawings

Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

FIG. 1 is a schematic diagram of a prior art heat dissipation structure;

fig. 2-13 are first to twelfth schematic views of semiconductor packaging devices according to embodiments of the present invention.

Description of the symbols:

11. a right chip; 12. a left side chip; 13. an underfill material; 14. a heat dissipating element; 15. a substrate; 100. a chip layer; 110. a first chip; 120. a second chip; 130. a first underfill material; 140. packaging materials; 150. a second underfill material; 200. a heat sink; 210. a first through hole; 220. a second through hole; 230. a side wall; 300. an adhesive layer; 500. a fan-out circuit layer; 600. a substrate; 610. an adhesive material; 620. a third underfill material.

Detailed Description

The following description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples, and the technical problems and effects solved by the present invention will be readily apparent to those skilled in the art from the description of the embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.

It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the scope of the present disclosure, which is defined by the claims and the appended claims, and therefore, they are not technically essential, and any structural modification, proportion change, or size adjustment should be within the scope of the present disclosure without affecting the function and achievement of the present disclosure. In addition, the terms "above", "first", "second" and "a" as used in the present specification are for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship thereof may be regarded as the scope of the present invention without substantial technical changes.

It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure may be a front view direction section, the transverse section may be a right view direction section, and the horizontal section may be a top view direction section.

In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 1 is a schematic diagram of a heat dissipation structure in the prior art. As shown in fig. 1, the right chip 11 and the left chip 12 are both located on the substrate 15. An underfill material 13 is disposed between the right side chip 11 and the left side chip 12. The heat dissipation member 14 is located above the right-side chip 11 and the left-side chip 12, and the lower surface of the heat dissipation member 14 is in contact with the upper surface of the right-side chip 11, the upper surface of the left-side chip 12, and the upper surface of the underfill material 13, respectively. Generally, the heat dissipation element 14 has a large thermal expansion coefficient, and generates a large amount of thermal expansion when heated, thereby generating a large tensile stress on the right-side chip 11, the left-side chip 12, and the underfill material 13. Since the underfill material 13 has low rigidity and is weak against tensile stress, it is liable to break under the tensile stress.

Fig. 2-13 are first to twelfth schematic views of semiconductor packaging devices according to embodiments of the present invention. In fig. 3 to 8, the left side is a state before the heat sink 200 is placed, the position of the heat sink 200 is indicated by a dotted line, and the right side is a state after the heat sink 200 is placed.

Fig. 2 shows a longitudinal section of the semiconductor package device in the present embodiment. As shown in fig. 2, the semiconductor package device in the present embodiment includes a chip layer 100 and a heat sink 200. The chip layer 100 includes a first chip 110 and a second chip 120, and a gap between the first chip 110 and the second chip 120 may be provided with a first underfill material 130. The heat sink 200 is located on the surface of the chip layer 100, the heat sink 200 is provided with a first through hole 210 in a vertical direction, and the first through hole 210 is located at a position corresponding to the first underfill material 130.

Fig. 3 shows a top view of the semiconductor package device in the present embodiment. As shown in fig. 3, the first through hole 210 may expose an upper surface of the first underfill material 130 to the outside, preventing it from being in direct contact with a lower surface of the heat sink 200. In one example, the width of the first through-hole 210 (corresponding to the size of the first through-hole 210 in the up-down direction in fig. 3) may be 2 mm greater than the width of the gap between the first chip 110 and the second chip 120. The length of the first through-hole 210 (corresponding to the size of the first through-hole 210 in the left-right direction in fig. 3) may be 4 mm greater than the length of the gap between the first chip 110 and the second chip 120.

In the embodiment, the first chip 110 may be an ASIC (Application Specific Integrated Circuit) chip, and the second chip 120 may be an HBM (High Bandwidth Memory) chip. The heat sink 200 may be a metal material, such as copper, aluminum, or the like. The heat sink 200 may also be a highly thermally conductive non-metallic material such as graphite, silicone grease, etc.

In the semiconductor package device in this embodiment, the first through hole 210 in the vertical direction is disposed at the position on the heat dissipation member 200 corresponding to the first underfill material 130, so that the portion of the heat dissipation member 200 on the upper surface of the first underfill material 130 is removed, and the first underfill material 130 is prevented from generating tensile stress due to large thermal expansion when being heated, thereby preventing the first underfill material 130 from breaking, and facilitating improvement of product yield on the premise of ensuring the heat dissipation effect of the structure.

It can be confirmed by simulation calculation that the stress at the first underfill material 130 can be reduced by 34% in the semiconductor package device in the present embodiment, compared to the existing structure.

In the present embodiment, a ratio of a contact area of the heat sink 200 and the first chip 110 with respect to an upper surface area of the first chip 110 may be greater than 0.9. By setting the ratio of the contact area of the heat dissipation member 200 and the first chip 110 to the upper surface area of the first chip 110 to be greater than 0.9, it can be ensured that the heat dissipation member 200 and the first chip 110 have a large enough contact area to bring a good heat dissipation effect, and the influence on the heat dissipation effect of the first chip 110 due to the opening of the first through hole 210 is avoided. In addition, it is also advantageous to prevent the semiconductor package device from warping.

In the present embodiment, an extending direction of a horizontal cross section of the first through hole 210 may coincide with an extending direction of a gap between the first chip 110 and the second chip 120. As shown in fig. 3, the gap between the first chip 110 and the second chip 120 extends from left to right, and the horizontal cross section of the first through hole 210 also extends from left to right, which are consistent, so as to reduce the area of the horizontal cross section of the first through hole 210, thereby reducing the influence of the first through hole 210 on the heat dissipation capability of the heat dissipation member 200.

In the present embodiment, an extension length of a horizontal section of the first through-hole 210 may be greater than an extension length of a gap between the first chip 110 and the second chip 120. As shown in fig. 3, the extension length of the horizontal section of the first through hole 210 is greater than the extension length of the gap between the first chip 110 and the second chip 120, which is beneficial to ensure that the upper surface of the first underfill material 130 is completely exposed.

In this embodiment, the first via 210 may expose an upper surface of the first underfill material 130. As shown in fig. 3, the horizontal cross-sectional area of the first via hole 210 is greater than the upper surface area of the first underfill material 130 so that the first via hole 210 may expose the upper surface of the first underfill material 130. In addition, a portion of the upper surface of the first chip 110 and a portion of the upper surface of the second chip 120 are also exposed.

In the present embodiment, the first via hole 210 may expose the upper surface of the first underfill material 130 and the upper surface of the second chip 120. As shown in fig. 13, the horizontal cross-sectional area of the first via hole 210 is greater than the sum of the area of the upper surface of the first underfill material 130 and the area of the upper surface of the second chip 120, so that both the upper surface of the first underfill material 130 and the upper surface of the second chip 120 are exposed.

In the present embodiment, the first through hole 210 may include an arc portion. As shown in fig. 9, the first through hole 210 is entirely of a race track type, and both ends of the first through hole 210 are arc-shaped portions. Therefore, the first through hole 210 is smooth as a whole, and the stress concentration phenomenon at the first through hole 210 is prevented.

In one example, as shown in fig. 10, the first through-hole 210 may include a zigzag type portion. In another example, as shown in fig. 11, the first through-hole 210 may include a fence type portion. The first through hole 210 may have various shapes to meet various design requirements.

In one example, as shown in fig. 7, the heat sink 200 may further include a second through hole 220 in a vertical direction, a horizontal cross section of the second through hole 220 extends in a direction perpendicular to a gap between the first chip 110 and the second chip 120, and the second through hole 220 is in communication with the first through hole 210.

In one example, as shown in fig. 12, the first and second through

holes

210 and 220 may be cross-shaped as a whole.

In one example, as shown in fig. 7, the number of the second chips 120 may be at least two, at least two second chips 120 may be juxtaposed on the same side of the first chip 110, the second underfill material 150 may be disposed in a gap between at least two second chips 120, and the second through hole 220 may be located at a region corresponding to the second underfill material 150.

In one example, as shown in fig. 4, two second chips 120 may be juxtaposed on the same side of the first chip 110, and a first via 210 is also distributed on the side, and the first via 210 may expose the first underfill material 130 between the first chip 110 and the second chip 120. In another example, as shown in fig. 5, four second chips 120 may be distributed on both sides of the first chip 110, and two first through holes 210 are also distributed on both sides of the first chip 110, wherein there may be two juxtaposed second chips 120 on each side of the first chip 110, and the first through holes 210 may expose the first underfill material 130 between the first chip 110 and the second chips 120. In another example, as shown in fig. 6, eight second chips 120 may be distributed around the first chip 110, and four first through holes 210 may also be distributed around the first chip 110, wherein two second chips 120 may be present on each side of the first chip 110, and the first through holes 210 may expose the first underfill material 130 between the first chip 110 and the second chips 120.

In the present embodiment, an adhesive layer 300 may be disposed between the heat sink 200 and the chip layer 100. Both surfaces of the adhesive layer 300 may be adhered to the heat sink 200 and the chip layer 100, respectively, to thereby integrally connect the heat sink 200 and the chip layer 100.

In one example, the adhesive layer 300 may be a thermally conductive material, such as solder paste. Thus, the heat dissipation performance of the semiconductor packaging device can be further improved.

In the present embodiment, the heat sink 200 may have a sidewall 230 in a vertical direction. Thus, the heat dissipation area of the heat sink 200 is increased, and the heat dissipation performance of the semiconductor package device is further improved. In addition, heat sink 200 with side walls 230 may also provide protection for internal structures.

In this embodiment, the chip layer 100 may further include a packaging material 140 (Molding). The encapsulation material 140 may be positioned around the first chip 110 and the second chip 120, thereby providing protection for the first chip 110 and the second chip 120.

In this embodiment, the semiconductor package device may further include a fan-out wiring layer 500, and the chip layer 100 may be disposed on the fan-out wiring layer 500. In this manner, better external connection of the chip layer 100 is facilitated.

In this embodiment, the semiconductor package device may further include a substrate 600, and the fan-out wiring layer 500 may be located on the substrate 600. A third underfill 620 may be disposed between the fan-out line layer 500 and the substrate 600. The sidewall 230 of the heat sink 200 and the substrate 600 may be joined by an adhesive material 610.

In one example, the first through-hole 210 may be covered with an arc-shaped ceiling (not shown in the drawings) above. The arc-shaped top may protect the first through hole 210 from being directly exposed to the outside.

While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction in the present disclosure and the actual device due to variables in the manufacturing process and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.

Claims

1. A semiconductor package device, comprising:

2. The semiconductor package device according to claim 1, wherein a ratio of a contact area of the heat sink with the first chip to an upper surface area of the first chip is greater than 0.9.

3. The semiconductor package device according to claim 1, wherein an extending direction of a horizontal cross section of the first through hole coincides with an extending direction of a gap between the first chip and the second chip.

4. The semiconductor package device of claim 3, wherein an extension length of a horizontal cross section of the first via is greater than an extension length of a gap between the first chip and the second chip.

5. The semiconductor package device of claim 1, wherein the first via exposes an upper surface of the first underfill material.

6. The semiconductor package device of claim 1, wherein the first via exposes an upper surface of the first underfill material and an upper surface of the second chip.

7. The semiconductor package device of any of claims 1-6, wherein the first via includes an arcuate portion at an end of the first via.

8. The semiconductor package device of any of claims 1-6, wherein the first via includes a saw tooth portion.

9. The semiconductor package device of any of claims 1-6, wherein the first via comprises a fence-type portion.

10. The semiconductor package device according to claim 1, wherein a second through hole in a vertical direction is further provided in the heat sink, a horizontal cross section of the second through hole extending in a direction perpendicular to a gap between the first chip and the second chip, the second through hole communicating with the first through hole.

11. The semiconductor package device of claim 10, wherein the first and second vias are generally cross-shaped.

12. The semiconductor package device of claim 10, wherein the number of the second chips is at least two, at least two of the second chips are juxtaposed on the same side of the first chip, and a gap between at least two of the second chips is provided with a second underfill material; and

13. The semiconductor package device of any one of claims 1-6, wherein an adhesive layer is disposed between the heat spreader and the chip layer.

14. The semiconductor package device of claim 13, wherein the adhesive layer is a thermally conductive material.

15. The semiconductor package device of any one of claims 1-6, wherein the heat spreader has vertically oriented sidewalls.

16. The semiconductor package device of any of claims 1-6, wherein the chip layer further comprises a packaging material, the packaging material being located around the first chip and the second chip.

17. The semiconductor package device of any of claims 1-6, wherein the semiconductor package device further comprises a fan-out wiring layer, the chip layer disposed on the fan-out wiring layer.

18. The semiconductor package device of any one of claims 1-6, wherein the semiconductor package device further comprises a substrate, the fan-out wiring layer being located on the substrate.

19. The semiconductor package device of claim 18, wherein a third underfill material is disposed between the fan-out wiring layer and the substrate.

20. The semiconductor package device of any of claims 1-6, wherein the first via is capped with an arc-shaped top.