CN113031352A - Display substrate, display panel and display device - Google Patents
Display substrate, display panel and display device Download PDFInfo
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- CN113031352A CN113031352A CN202110383194.8A CN202110383194A CN113031352A CN 113031352 A CN113031352 A CN 113031352A CN 202110383194 A CN202110383194 A CN 202110383194A CN 113031352 A CN113031352 A CN 113031352A
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- 239000000758 substrate Substances 0.000 title claims abstract description 79
- 239000000126 substance Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 17
- 238000000034 method Methods 0.000 description 13
- 230000008569 process Effects 0.000 description 13
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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Abstract
The invention provides a display substrate, a display panel and a display device, wherein the display substrate comprises: the display device comprises a substrate base plate, a display area and a non-display area, wherein the substrate base plate comprises the display area and the non-display area surrounding the display area, and the non-display area comprises a binding area positioned on one side of the display area; the display area comprises a signal line, the signal line comprises a data line and a grid line which are arranged in a crossed mode, the binding area comprises a plurality of binding electrodes and a plurality of routing lines coupled with the binding electrodes, and at least part of the routing lines extend to the display area along the direction which is approximately the same as the extending direction of the data line or the grid line and are coupled with the signal line. For implementing a narrow bezel design.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display substrate, a display panel and a display device.
Background
At present, in display products, especially mobile phones, the requirements of users on frames are higher and higher, and narrow frames or even zero frames are expected to be achieved. The main reason that the frame is large at present is that a sector area needs to be set, that is, routing lines connected from the inside of an Integrated Circuit (IC) are set in areas on both sides of the IC, and oblique routing lines are often more, so that the distance from the IC to a display area is larger, and narrow frame design cannot be guaranteed.
Disclosure of Invention
The invention provides a display substrate, a display panel and a display device, which are used for realizing narrow frame design.
In a first aspect, an embodiment of the present invention provides a display substrate, including:
the display device comprises a substrate base plate, a display area and a non-display area, wherein the substrate base plate comprises the display area and the non-display area surrounding the display area, and the non-display area comprises a binding area positioned on one side of the display area; wherein the content of the first and second substances,
the display area comprises a signal line, the signal line comprises a data line and a grid line which are arranged in a crossed mode, the binding area comprises a plurality of binding electrodes and a plurality of routing lines coupled with the binding electrodes, and at least part of the routing lines extend to the display area along the direction which is approximately the same as the extending direction of the data line or the grid line and are coupled with the signal line.
In a possible implementation manner, if at least a portion of the plurality of traces extend to the display area along a direction substantially the same as an extending direction of the data lines, at least a portion of the plurality of traces includes a first trace coupled to the gate line, and the first trace extends to the display area along a direction substantially the same as the extending direction of the data lines.
In a possible implementation manner, at least a portion of the plurality of traces includes a second trace coupled to the data line, the second trace includes a first line segment that is consistent with an extending direction of the data line and a second line segment that is substantially the same as the extending direction of the gate line, and the second trace extends to the display area along the first line segment and is coupled to the data line along the second line segment.
In a possible implementation manner, if at least a portion of the plurality of traces extend to the display area along a direction substantially the same as the extending direction of the gate line, at least a portion of the plurality of traces includes a third trace coupled to the data line, and the third trace extends to the display area along a direction substantially the same as the extending direction of the gate line.
In one possible implementation manner, at least a portion of the plurality of traces includes a fourth trace coupled to the gate line, the fourth trace includes a third line segment having a substantially same extending direction as the gate line and a fourth line segment having a substantially same extending direction as the data line, and the fourth trace extends to the display area along the third line segment and is coupled to the gate line along the fourth line segment. In a possible implementation manner, the first trace is coupled to the gate line through a first via, the second trace adjacent to the first trace is coupled to the data line through a second via, and the first via is closer to the bonding area than the second via, where an orthographic projection of the first trace on the substrate base plate and an orthographic projection of the second trace on the substrate base plate are not overlapped with each other.
In a possible implementation manner, the extending length of at least a part of the plurality of same traces is inversely related to the distance from the corresponding via to the bonding area.
In a possible implementation manner, a plurality of same routing lines are arranged between two adjacent data lines, and first line segments of the first routing lines and the second routing lines, which are substantially the same along the extending direction of the data lines, are sequentially arranged at intervals along the extending direction of the gate lines.
In a possible implementation manner, a plurality of the same routing lines are arranged between two adjacent data lines, first line segments of the two adjacent second routing lines, which have substantially the same extension direction along the data lines, extend to one side of the display area, which is far away from the binding area, at least three data lines are arranged between the two adjacent first line segments at intervals, and the first routing line is arranged between two adjacent data lines of the at least three data lines.
In a possible implementation manner, orthographic projections of any two of at least some of the plurality of routing lines on the substrate do not overlap with each other.
In a possible implementation manner, the signal line further includes a potential trace and an initialization trace, the display area includes a plurality of sub-display areas, at least a portion of the plurality of traces is coupled to a corresponding initialization trace of at least a portion of the sub-display areas, and a first initialization voltage loaded by the initialization trace deviating from the bonding area in the plurality of sub-display areas is greater than a second initialization voltage loaded by the initialization trace close to the bonding area.
In a second aspect, an embodiment of the present invention provides a display panel, including:
a display substrate as claimed in any preceding claim.
In a third aspect, an embodiment of the present invention provides a display device, including:
such as the display panel described above. The invention has the following beneficial effects:
the embodiment of the invention provides a display substrate, a display panel and a display device, wherein the display substrate comprises a substrate base plate, the substrate base plate comprises a display area and a non-display area surrounding the display area, the non-display area comprises a binding area positioned on one side of the display area, the display area comprises signal lines, the signal lines comprise data lines and grid lines which are arranged in a crossed mode, the binding area comprises a plurality of binding electrodes and a plurality of routing lines coupled with the binding electrodes, and at least part of the routing lines extend to the display area along the direction which is approximately the same as the extending direction of the data lines or the grid lines and are coupled with the signal lines. That is to say, at least part of the plurality of wires coupled to the plurality of bonding electrodes in the bonding area directly extend to the display area along a direction in which the data line or the gate line extends, and are coupled to the signal line, so that a space occupied by a part of the plurality of wires coupled to the plurality of bonding electrodes in the bonding area, which obliquely enters the display area, in the bonding area is reduced, and thus a frame space occupied by the bonding area can be reduced to a great extent, thereby realizing a narrow frame design.
Drawings
FIG. 1 is a schematic diagram of a display device according to the related art;
fig. 2 is a schematic structural diagram of a display substrate according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating a distribution of a display area, a non-display area, and a bonding area in a display substrate according to an embodiment of the present invention;
fig. 4 is a schematic view illustrating a distribution of traces in a display substrate according to an embodiment of the invention;
fig. 5 is a schematic view illustrating a distribution of traces in a display substrate according to an embodiment of the invention;
fig. 6 is a schematic view illustrating a distribution of traces in a display substrate according to an embodiment of the invention;
fig. 7 is a schematic view illustrating a distribution of traces in a display substrate according to an embodiment of the invention;
fig. 8 is a schematic structural diagram of a display substrate according to an embodiment of the present invention, in which a trace and a signal line are coupled;
fig. 9 is a schematic view illustrating a distribution of traces in a display substrate according to an embodiment of the invention;
fig. 10 is a schematic view illustrating a distribution of traces in a display substrate according to an embodiment of the invention;
fig. 11 is a schematic view illustrating a distribution of traces in a display substrate according to an embodiment of the invention;
fig. 12 is a schematic view illustrating a distribution of traces in a display substrate according to an embodiment of the invention;
fig. 13 is a schematic view illustrating a distribution of traces in a display substrate according to an embodiment of the invention;
fig. 14 is a schematic diagram illustrating a region division of a display region in a display substrate according to an embodiment of the present invention;
fig. 15 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Description of reference numerals:
01-control IC; 1-a substrate base plate; 2-binding the electrodes; a-a display area; b-a non-display area; c-a binding region; d-a data line; g-grid line; s-a signal line; 3-routing; 31-a first trace; 32-a second trace; 33-a third trace; 34-a fourth trace; 321-a first line segment; 322-second line segment; 323-third line segment; 324-a fourth line segment; 310 — a first via; 320-a second via; 4-initializing wiring; 100-a display substrate; 200-a display panel; 300-a control chip; 301-binding terminals.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of the word "comprise" or "comprises", and the like, in the context of this application, is intended to mean that the elements or items listed before that word, in addition to those listed after that word, do not exclude other elements or items.
It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
In the prior art, as shown in fig. 1, wires connected inside an IC01 are often routed to areas on two sides wider than the IC01, and more oblique wires often result in a larger distance from the IC01 to a display area, and a bezel often becomes wider.
In view of this, embodiments of the present invention provide a display substrate, a display panel and a display device, which are used to implement a narrow frame design.
Fig. 2 is a schematic structural diagram of a display substrate according to an embodiment of the present invention, specifically, the display substrate includes:
the display panel comprises a substrate base plate 1, wherein the substrate base plate 1 comprises a display area A and a non-display area B surrounding the display area A, and the non-display area B comprises a binding area C positioned on one side of the display area A; wherein the content of the first and second substances,
the display area A comprises a signal line S, the signal line S comprises a data line D and a grid line G which are arranged in a crossed mode, the binding area comprises a plurality of binding electrodes 2 and a plurality of wires 3 coupled with the binding electrodes 2, and at least part of the wires 3 extend to the display area A along the direction which is approximately the same as the extending direction of the data line D and are coupled with the signal line S.
In a specific implementation process, the substrate 1 may be a glass substrate, a silicon substrate, a flexible substrate, or the like, which is not limited herein. The display substrate includes a display area a and a non-display area B surrounding the display area a, the non-display area B includes a bonded area C located on one side of the display area a, the plurality of bonded electrodes 2 are located in the bonded area C, one of distribution diagrams of the display area a, the non-display area B, and the bonded area C may be as shown in fig. 2, and furthermore, one of distribution diagrams of the display area a, the non-display area B, and the bonded area C may also be as shown in fig. 3, and of course, the display area a, the non-display area B, and the bonded area C may also be set according to actual application needs, which is not limited herein. In addition, fig. 2 and fig. 3 illustrate a limited number of the binding electrodes 2, and each binding electrode 2 is located in the same behavior example, in practical applications, the binding electrodes 2 in the binding region C are used for binding and connecting with an IC, the number and arrangement of the binding electrodes 2 in the binding region C may be set according to the number and distribution of binding terminals of the IC that need to be bound, and the number and arrangement of the binding electrodes 2 are not limited here.
In a specific implementation, the display region a includes a signal line S, the signal line S includes a data line D and a gate line G, the data line D may extend along a first direction indicated by an arrow x in fig. 2, the gate line G may extend along a second direction indicated by an arrow y in fig. 2, and the first direction and the second direction cross each other. The bonding area C further includes a plurality of traces coupled to the plurality of bonding electrodes 2, and at least a portion of the plurality of traces 3 extends to the display area a along a direction substantially the same as an extending direction of the data line D and is coupled to the signal line S. As shown in fig. 3, at least a portion of the plurality of routing lines 3 may extend to the display area a along a direction substantially the same as the extending direction of the gate line G. The signal lines S may further include a potential trace and an initialization trace, where the potential trace may be a low potential trace or a high potential trace, and is not limited herein, fig. 2 only illustrates a case where at least a portion of the plurality of traces 3 is coupled to the gate line G, and fig. 3 only illustrates a case where at least a portion of the plurality of traces 3 is coupled to the data line D.
It should be noted that "substantially the same" in the embodiment of the present invention may be the same within a process tolerance, may be an included angle between an extending direction of at least a portion of any one of the plurality of traces 3 and an extending direction of the data line D is [ -30 °, +30 ° ], and may be an included angle between an extending direction of at least a portion of any one of the plurality of traces 3 and an extending direction of the gate line G is [ -30 °, +30 ° ]. For example, when an included angle between an extending direction of any one of at least some of the plurality of traces 3 and the extending direction of the data line D is 10 °, it indicates that the extending direction of the any one of the traces is substantially the same as the extending direction of the data line D.
In a specific implementation process, at least a portion of the plurality of traces coupled to the plurality of bonding electrodes 2 of the bonding area C directly extend to the display area a along a direction substantially the same as an extending direction of the data line D or the gate line G, and are coupled to the signal line S, so that a space occupied by a portion of the plurality of traces that obliquely enters the display area a in the bonding area C is reduced, and thus a frame space occupied by the bonding area C can be reduced to a great extent, thereby implementing a narrow frame design.
In the embodiment of the present invention, since the distribution of the display area a, the non-display area B, and the binding area C may be different, and accordingly, the distribution of at least a portion of the plurality of wires 3 may also be different, specifically, at least a portion of the plurality of wires may be set according to the following four setting manners, but is not limited to the following four setting manners.
In the embodiment of the present invention, when the display area a, the non-display area B, and the bonding area C are distributed as shown in fig. 2, at least a portion of the plurality of traces 3 are disposed according to a first arrangement manner, as shown in fig. 4, fig. 4 is a schematic diagram of a distribution of the plurality of traces 3 in the display substrate according to the first arrangement manner, specifically, if at least a portion of the plurality of traces 3 extends to the display area a along a direction substantially the same as an extending direction of the data line D, at least a portion of the plurality of traces 3 includes a first trace 31 coupled to the gate line G, and the first trace 31 extends to the display area a along a direction substantially the same as an extending direction of the data line D.
In a specific implementation process, as shown in fig. 4, at least a portion of the first traces 31 of the plurality of traces 3 directly extend from the bonding area C to the display area a and are coupled to the gate line G, so that a space occupied by a portion of the first traces 31 coupled to the gate line G, which obliquely enter the display area a, in the bonding area C is reduced, and thus a frame space occupied by the bonding area C is reduced to a certain extent, thereby implementing a narrow frame design.
In this embodiment of the present invention, when the display area a, the non-display area B, and the bonding area C are distributed as shown in fig. 2, at least a portion of the plurality of traces 3 may be disposed according to a second arrangement manner, as shown in fig. 5, fig. 5 is a schematic diagram of one of the plurality of traces in the display substrate, specifically, at least a portion of the plurality of traces includes a second trace 32 coupled to the data line D, the second trace 32 includes a first line segment 321 extending in a substantially same direction as the data line D and a second line segment 322 extending in a substantially same direction as the gate line G, and the second trace 32 extends to the display area along the first line segment 321 and is coupled to the data line D along the second line segment 322.
In a specific implementation process, as shown in fig. 5, at least a portion of the second traces 32 in the plurality of traces directly extend from the bonding area C to the display area a along a first line segment 321 having a substantially same extending direction as the data line D, and the second traces 32 are coupled to the data line D along a second line segment 322 having a substantially same extending direction as the gate line G, so that a space occupied by a portion of the second traces 32 coupled to the data line D, which obliquely enter the display area a, in the bonding area C is reduced, and thus a frame space occupied by the bonding area C is reduced to a certain extent, thereby implementing a narrow frame design.
In this embodiment of the present invention, when the display area a, the non-display area B, and the bonding area C are distributed as shown in fig. 3, at least a portion of the plurality of traces 3 are disposed according to a third arrangement manner, as shown in fig. 6, fig. 6 is a schematic diagram of the distribution of the plurality of traces 3 in the display substrate according to the third arrangement manner, specifically, if at least a portion of the plurality of traces 3 extends to the display area a along a direction substantially the same as an extending direction of the gate line G, at least a portion of the plurality of traces 3 includes a third trace 33 coupled to the data line D, and the third trace 33 extends to the display area a along a direction substantially the same as the extending direction of the gate line G.
In a specific implementation process, as shown in fig. 6, at least a portion of the third traces 33 of the plurality of traces 3 directly extend from the bonding area C to the display area a and are coupled to the data lines D, so that a space occupied by a portion of the third traces 33 coupled to the data lines D, which obliquely enter the display area a, in the bonding area C is reduced, and thus a frame space occupied by the bonding area C is reduced to a certain extent, thereby implementing a narrow frame design.
In the embodiment of the present invention, when the display area a, the non-display area B, and the bonding area C are distributed as shown in fig. 2, at least part of the plurality of traces 3 may be further disposed in a fourth arrangement manner, as shown in fig. 7, fig. 7 is a schematic diagram illustrating one of the plurality of traces in the display substrate, specifically, at least part of the plurality of traces 3 includes a fourth trace 34 coupled to the gate line G, the fourth trace 34 includes a third line segment 323 substantially identical to the extending direction of the gate line G and a fourth line segment 324 substantially identical to the extending direction of the data line D, and the fourth trace 34 extends to the display area a along the third line segment 323 and is coupled to the gate line G along the fourth line segment 324.
In a specific implementation process, as shown in fig. 7, at least a portion of the fourth traces 34 in the plurality of traces 3 directly extend from the bonding area C to the display area a along a third line segment 323 having a substantially same extending direction as the gate line G, and the fourth trace 34 is coupled to the gate line G along a fourth line segment 324 having a substantially same extending direction as the data line D, so that a space occupied by a portion of the fourth trace 34 coupled to the gate line G, which obliquely enters the display area a, in the bonding area C is reduced, and thus a frame space occupied by the bonding area C is reduced to a certain extent, thereby implementing a narrow frame design.
In an embodiment of the present invention, at least a portion of any trace of the plurality of traces 3 is coupled to the signal line through a via, as shown in fig. 8, fig. 8 is a schematic structural diagram of at least a portion of the plurality of traces 3 being coupled to the signal line S, specifically, the first trace 31 is coupled to the gate line G through a first via 310, the second trace 32 adjacent to the first trace 31 is coupled to the data line D through a second via 320, the first via 310 is closer to the bonding area C than the second via 320, and an orthographic projection of the first trace 31 on the substrate 1 and an orthographic projection of the second trace 32 on the substrate 1 do not overlap each other.
In a specific implementation process, after the second trace 32 is coupled to the data line D through the second via 320, the opening position of the first via 310 may be adjusted according to the specific position where the second via 320 is opened, in the via opening process, as long as it is ensured that the first via 310 is closer to the bonding region C than the second via 320, and the orthographic projections of the first trace 31 and the second trace 32 on the substrate 1 are not overlapped, wherein the orthographic projections of the first trace 31 and the second trace 32 on the substrate 1 are not overlapped, so as to effectively avoid interference between the signal transmitted on the first trace 31 and the signal transmitted on the second trace 32, that is, the position where the second via 320 is opened may be adjusted according to the position where the first via 310 is opened, the first routing lines 31 and the second routing lines 32 are not overlapped, interference between signals is avoided, meanwhile, flexible arrangement of via holes is achieved, and therefore manufacturing cost of the display substrate is reduced.
In the embodiment of the present invention, as shown in fig. 9, a schematic diagram of a distribution of the plurality of traces 3 in the display substrate is shown, specifically, an extending length of at least a part of the same trace in the plurality of traces 3 is inversely related to a distance from a corresponding via to the bonding area C. Taking the plurality of first traces 31 coupled to the gate line G as an example, as shown in fig. 9, the longer the extended length of the plurality of first traces 31 is, the smaller the distance from the first via 310 coupled to the gate line G to the bonding region C is, otherwise, the shorter the extended length of the plurality of first traces 31 is, the greater the distance from the first via 310 coupled to the gate line G to the bonding region C is, so that the resistance value between the first traces 31 is ensured to be approximately equal, thereby avoiding the problem of uneven display caused by the difference of the resistance-capacitance Loading (RC Loading), ensuring the uniformity of display, and improving the display quality.
In the embodiment of the present invention, when the display area a, the non-display area B and the binding area C are distributed according to fig. 2, and at least part of the plurality of traces includes the first trace 31 and the second trace 32, the related traces can be arranged in the manner shown in fig. 10, a plurality of the same traces are arranged between two adjacent data lines D, the first line segments 321 of the first trace 31 and the second trace 32, which are substantially the same in the extending direction of the data line D, are sequentially spaced along the extending direction of the gate line G, in this way, the resistance values of the first traces 31 are approximately equal, the resistance values of the second traces 32 are approximately equal, therefore, the problem of uneven display caused by RC Loading difference is avoided while the design of a narrow frame is ensured, the display uniformity is ensured, and the display quality is improved.
In the embodiment of the present invention, when the display area a, the non-display area B, and the bonding area C are distributed according to fig. 2, and at least a portion of the plurality of traces includes the first trace 31 and the second trace 32, the related traces may be further arranged in a manner as shown in fig. 11, specifically, the same trace is arranged between two adjacent data lines D, first line segments 321 of the two adjacent second traces 32, which have substantially the same extension direction along the data line D, both extend to a side of the display area a away from the bonding area C, at least three data lines D are arranged between the two adjacent first line segments 321 at intervals, and the first trace 31 is arranged between two adjacent data lines D of the at least three data lines D.
Still referring to fig. 11, at least a portion of the plurality of traces 3 are substantially uniformly distributed along the extending direction of the data line D, the first line segments 321 of the second traces 32 that are substantially the same along the extending direction of the data line D may extend to the uppermost of the display area a, the first line segments 321 and the gate line G are not overlapped, and the same trace is disposed between two adjacent data lines D, in addition, fig. 10 and 11 respectively illustrate a case where three first traces 31 are disposed between two adjacent data lines D or three second traces 32 are disposed. In addition, since the distance between the first via hole 310 and the bonding area C is smaller than the distance between the second via hole 320 and the bonding area C, as shown in fig. 11, when the first line segment 321 of the second trace 32, which is substantially the same in the extending direction of the data line D, extends to the uppermost of the display area a, the position adjustment range of the first via hole 310 may be wider, thereby ensuring the flexibility of the manufacturing process of the display substrate. In addition, when at least a portion of the traces 3 are disposed in the manner shown in fig. 11, corresponding traces may be disposed in each area in the display area a, so that the traces may be uniformly distributed, thereby reducing the optical reflection difference in each area.
In the embodiment of the present invention, orthographic projections of any two of at least some of the plurality of traces 3 on the substrate 1 are not overlapped with each other, so that signals transmitted on the traces are not interfered with each other, and a short circuit caused by release of the two traces is avoided, thereby ensuring the display quality of the display substrate.
In a specific implementation process, when the display area a, the non-display area B, and the binding area C are distributed according to fig. 3, and at least a portion of the plurality of traces includes the third trace 33 and the second trace 34, the relevant traces may be set in a manner as shown in fig. 12 and 13, and of course, the relevant traces may be set in other manners according to actual application needs, which is not described in detail herein.
In this embodiment of the present invention, when the display area a, the non-display area B, and the bonding area C are distributed as shown in fig. 2, as shown in fig. 14, a schematic diagram of one of the areas of the display area a is shown, specifically, the display area a includes a plurality of sub-display areas, at least some of the plurality of traces 3 are coupled to corresponding initialization traces 4 of at least some of the sub-display areas, and a first initialization voltage loaded by an initialization trace that deviates from the bonding area C in the plurality of sub-display areas is greater than a second initialization voltage loaded by an initialization trace 4 that is close to the bonding area C.
It should be noted that, here, the first initialization voltage is greater than the second initialization voltage, specifically, an absolute value of the first initialization voltage is greater than an absolute value of the second initialization voltage.
In a specific implementation process, at least one routing line can be coupled with an initialization routing line in a certain sub-display area, on one hand, the routing line can directly extend from the binding area to the display area a along the extension direction of the data line D, so that a narrow frame design is realized; on the other hand, different initialization traces are arranged in different sub-display areas, the initialization traces in different sub-display areas load corresponding initialization voltages, and compared with the situation that only one initialization trace is arranged in the whole display area A, the corresponding initialization traces are arranged for different sub-display areas, so that the parasitic capacitance in each sub-display area is reduced, and the display quality is guaranteed. In addition, different initialization voltages are loaded to different sub-display areas, for example, a first initialization voltage loaded to an initialization trace away from the bonding area C in the plurality of sub-display areas is greater than a second initialization voltage loaded to an initialization trace close to the bonding area C, and specifically, a corresponding initialization voltage is loaded to the initialization trace of each sub-display area according to an inverse relationship between a distance between each sub-display area and the bonding area C and a magnitude of the initialization voltage loaded to the initialization trace of the corresponding sub-display area. The initialization voltage applied to the initialization trace of the sub-display area farther from the binding area C may be larger, and correspondingly, the initialization voltage applied to the initialization trace of the sub-display area closer to the binding area C may be smaller, so that the influence of RC Loading on each sub-display area is avoided, and the display uniformity is ensured.
Fig. 14 only illustrates a situation that the display area a includes four sub-display areas including a sub-display area a, a sub-display area b, a sub-display area c, and a sub-display area d, where the initialization trace in the sub-display area a may be loaded with a voltage of-3.3V, the initialization trace in the sub-display area b may be loaded with a voltage of-3.2V, the initialization trace in the sub-display area c may be loaded with a voltage of-3.1V, and the initialization trace in the sub-display area d may be loaded with a voltage of-3V. For the case that the display area a includes other number of sub-display areas, the setting situation is the same as the setting situation of four sub-display areas, and details thereof are not described herein.
It should be noted that each of the traces may also be coupled to the high-potential trace of each corresponding sub-display region, and for the situation of the voltage loaded by the high-potential trace in each sub-display region, the situation of the voltage loaded by the initialization trace may be referred to, and details are not described.
Based on the same inventive concept, as shown in fig. 15, an embodiment of the present invention further provides a display panel, where the display panel 200 includes the display substrate 100 as described above. The Display Panel may be a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED), a Plasma Display Panel (PDP), or an electrophoretic Display (EPD), which is not limited herein.
The principle of the display panel 200 to solve the problem is similar to the display substrate 100, so the implementation of the display panel 200 can be referred to the implementation of the display substrate 100, and repeated descriptions are omitted.
Based on the same inventive concept, as shown in fig. 16, an embodiment of the present invention further provides a display device, which has a similar problem solving principle to the display substrate 100, so that the implementation of the display device can refer to the implementation of the display substrate 100, and repeated details are omitted.
In a specific implementation process, the display device further includes a control chip 300, the control chip 300 includes a plurality of binding terminals 301, and the binding terminals 301 are directly bound and connected with the binding electrodes 2 in the display substrate 100.
In a specific implementation process, the display device provided by the embodiment of the invention may be a mobile phone, and may also be any product or component with a display function, such as a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein nor should they be construed as limiting the present invention.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (12)
1. A display substrate, comprising:
the display device comprises a substrate base plate, a display area and a non-display area, wherein the substrate base plate comprises the display area and the non-display area surrounding the display area, and the non-display area comprises a binding area positioned on one side of the display area; wherein the content of the first and second substances,
the display area comprises a signal line, the signal line comprises a data line and a grid line which are arranged in a crossed mode, the binding area comprises a plurality of binding electrodes and a plurality of routing lines coupled with the binding electrodes, and at least part of the routing lines extend to the display area along the direction which is approximately the same as the extending direction of the data line or the grid line and are coupled with the signal line.
2. The display substrate according to claim 1, wherein if at least a portion of the plurality of traces extend to the display area along a direction substantially the same as an extending direction of the data lines, at least a portion of the plurality of traces includes a first trace coupled to the gate line, and the first trace extends to the display area along a direction substantially the same as the extending direction of the data lines.
3. The display substrate according to claim 2, wherein at least a portion of the plurality of traces includes a second trace coupled to the data line, the second trace includes a first line segment having a substantially same extending direction as the data line and a second line segment having a substantially same extending direction as the gate line, and the second trace extends along the first line segment to the display area and is coupled to the data line along the second line segment.
4. The display substrate according to claim 1, wherein if at least a portion of the plurality of traces extend to the display area along a direction substantially the same as the extending direction of the gate line, at least a portion of the plurality of traces includes a third trace coupled to the data line, and the third trace extends to the display area along a direction substantially the same as the extending direction of the gate line.
5. The display substrate according to claim 4, wherein at least a portion of the plurality of traces includes a fourth trace coupled to the gate line, the fourth trace includes a third line segment extending in a substantially same direction as the gate line and a fourth line segment extending in a substantially same direction as the data line, and the fourth trace extends along the third line segment to the display area and is coupled to the gate line along the fourth line segment.
6. The display substrate of claim 3, wherein the first trace is coupled to the gate line through a first via, and the second trace adjacent to the first trace is coupled to the data line through the second via, the first via being closer to the bonding area than the second via, wherein an orthographic projection of the first trace on the substrate and an orthographic projection of the second trace on the substrate do not overlap each other.
7. The display substrate of claim 6, wherein an extension length of at least a portion of the same one of the plurality of traces is inversely related to a distance from the corresponding via to the bonding area.
8. The display substrate according to claim 7, wherein a plurality of same type of traces are disposed between two adjacent data lines, and first line segments of the first traces and the second traces, which are substantially the same along the extending direction of the data lines, are sequentially disposed at intervals along the extending direction of the gate lines.
9. The display substrate of claim 1, wherein orthographic projections of any two of at least some of the plurality of traces on the substrate do not overlap.
10. The display substrate according to claim 1, wherein the signal lines further include potential traces and initialization traces, the display area includes a plurality of sub-display areas, at least some of the traces are coupled to corresponding initialization traces of at least some of the sub-display areas, and a first initialization voltage loaded by an initialization trace of the plurality of sub-display areas that deviates from the bonding area is greater than a second initialization voltage loaded by an initialization trace of the plurality of sub-display areas that is close to the bonding area.
11. A display panel, comprising:
a display substrate according to any one of claims 1 to 10.
12. A display device, comprising:
the display panel of claim 11.
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| CN202110383194.8A CN113031352B (en) | 2021-04-09 | 2021-04-09 | Display substrate, display panel and display device |
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| WO2023159510A1 (en) * | 2022-02-25 | 2023-08-31 | 京东方科技集团股份有限公司 | Display substrate and display apparatus |
| WO2024000793A1 (en) * | 2022-06-30 | 2024-01-04 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
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| CN113031352B (en) | 2024-04-02 |
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