CN113014094B - Boost converter - Google Patents
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- CN113014094B CN113014094B CN201911323182.5A CN201911323182A CN113014094B CN 113014094 B CN113014094 B CN 113014094B CN 201911323182 A CN201911323182 A CN 201911323182A CN 113014094 B CN113014094 B CN 113014094B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/14—Arrangements for reducing ripples from dc input or output
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
A boost converter is provided, through setting up the series combination of second power switch pipe Mp1 and first power switch pipe Mp0, can both keep normally stepping up, and when input voltage VIN is close to, is equal to or greater than output voltage VOUT, VOUT ripple still keeps less state in order to guarantee steady voltage output and improve conversion efficiency.
Description
Technical Field
The invention relates to a DCDC conversion technology, in particular to a boost converter, which can keep normal boost and can still keep a small VOUT ripple wave to ensure voltage stabilization output and improve conversion efficiency when an input voltage VIN is close to, equal to or greater than an output voltage VOUT by arranging a series combination of a second power switch tube Mp1 and a first power switch tube Mp 0.
Background
A Boost converter, also referred to as a Boost converter, is a common type of DCDC converter. DCDC (direct current-direct current) refers to the conversion of direct current to direct current that changes the direct current parameters. Boost converters generally boost a lower input voltage VIN to a higher output voltage VOUT. However, during the boost conversion, VIN may also be near, equal to, or greater than VOUT. When such a situation is met, the conventional Boost converter has the problems of large ripple and incapability of maintaining the output voltage. Therefore, the Boost converter in the prior art adopts an inductor current peak control mode to cope with such a situation. By using the inductor current peak control mode, when VIN is close to VOUT, the gate of the synchronous PMOS transistor (the first power switch transistor Mp0) is connected to VIN, so that VOUT of the Boost converter can be maintained constant. This presents a problem in that the conversion efficiency of VIN to VOUT is low. The inventor believes that if the series combination of the second power switch Mp1 and the first power switch Mp0 is provided and the inductor current valley control mode is adopted in the loop control, the normal boost can be maintained, and the VOUT ripple can still be kept small when the input voltage VIN is close to, equal to or greater than the output voltage VOUT, so as to ensure the regulated output and improve the conversion efficiency. In view of the above, the present inventors have completed the present invention.
Disclosure of Invention
Aiming at the defects or shortcomings in the prior art, the invention provides the boost converter, and by arranging the series combination of the second power switch tube Mp1 and the first power switch tube Mp0, normal boost can be kept, and when the input voltage VIN is close to, equal to or greater than the output voltage VOUT, the VOUT ripple is still kept in a small state to ensure voltage stabilization output and improve the conversion efficiency.
The technical scheme of the invention is as follows:
a boost converter comprises a first PMOS power switch tube driven by a first control signal through a first driving circuit and a first NMOS power switch tube driven by a third control signal through a third driving circuit, and is characterized in that a second PMOS power switch tube is introduced, the second PMOS power switch tube and the first PMOS power switch tube form a series combination, and the second PMOS power switch tube is driven by a second control signal through a second driving circuit.
The source electrode of the first PMOS power switch tube is connected with an output voltage end, the drain electrode of the first PMOS power switch tube is connected with the source electrode of the second PMOS power switch tube, the drain electrodes of the second PMOS power switch tube and the first NMOS tube are interconnected to form a switch node, the switch node is connected with the input voltage end through a first inductor, and the source electrode of the first NMOS tube is connected with a grounding end.
The first PMOS power switch tube and the second PMOS power switch tube are connected with an interconnection node, the end of the third PMOS tube is connected with the end of the fourth PMOS tube, the end of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube, the source electrode of the third PMOS tube is connected with the output voltage end, the source electrode of the fourth PMOS tube is connected with the input voltage end, the grid electrode of the third PMOS tube is connected with the output end of the first phase inverter, the input end of the first phase inverter is connected with the output end of the highest voltage selection comparator, the grid electrode of the fourth PMOS tube is connected with the output end of the highest voltage selection comparator, the positive input end of the highest voltage selection comparator is connected with the output voltage end, and the negative input end of the highest voltage selection comparator is connected with the input voltage end.
The second control signal is an output end signal of the highest voltage selection comparator.
The second driving circuit comprises a fifth PMOS tube and a sixth PMOS tube, wherein the source electrodes of the fifth PMOS tube and the sixth PMOS tube are interconnected, the drain electrode of the fifth PMOS tube is connected with the output voltage end, the drain electrode of the sixth PMOS tube is connected with the input voltage end, the grid electrode of the fifth PMOS tube is connected with the output end of the second phase inverter, the input end of the second phase inverter is connected with the output end of the highest voltage selection comparator, and the grid electrode of the sixth PMOS tube is connected with the output end of the highest voltage selection comparator.
The source electrode of the fifth PMOS tube is connected with the source electrode of a seventh PMOS tube, the gate and drain of the seventh PMOS tube are connected with the grounding end through a first current source after being interconnected, the source electrode of the sixth PMOS tube is respectively connected with the output end of the second driving circuit, the source electrode of the eighth PMOS tube and the drain electrode of the second NMOS tube through a second current source, the eighth PMOS tube is interconnected with the gate electrode of the seventh PMOS tube, the drain electrode of the eighth PMOS tube and the source electrode of the second NMOS tube are both connected with the grounding end, and the gate electrode of the second NMOS tube is connected with the output end of the highest voltage selection comparator.
The invention has the following technical effects: according to the boost converter, the synchronous PMOS tube is connected in series by two high-power tubes (namely the first PMOS power switch tube is connected in series with the second PMOS power switch tube), and the loop control adopts an inductive current valley control mode, so that output voltage ripples are still small when the input voltage VIN is close to or equal to the output voltage VOUT. When the input voltage is higher than the output voltage, the gate drive output voltage VA (the output end of the second drive circuit) of the synchronous PMOS tube (namely, the second PMOS power switch tube) connected with the switch node SW is slightly lower than the input voltage VIN, the synchronous PMOS tube (namely, the first PMOS power switch tube) connected with VOUT is normally opened and closed, the loop control still maintains the inductive current valley value control mode, the output voltage ripple is ensured not to be increased, meanwhile, the high level of the negative half cycle SW is only slightly higher than the input voltage VIN, and the conversion efficiency is very high.
The invention has the characteristics that: when the input voltage VIN is close to or more than the output voltage VOUT, the ripple of the output voltage VOUT is small, and the conversion efficiency is high.
Drawings
Fig. 1 is a schematic circuit diagram of a boost converter embodying the present invention. In fig. 1, the second PMOS transistor Mp1 (or referred to as a second PMOS power switch transistor) is a newly added synchronous PMOS transistor connected in series with the Mp0 based on an existing synchronous PMOS transistor (the first PMOS transistor Mp0, also referred to as a first PMOS power switch transistor, or an upper transistor), a drain of the Mp1 and a drain of the first NMOS transistor Mn0 are interconnected to form a switch node SW, the SW is connected to the input voltage terminal VIN through a first inductor L1, and a gate of the Mp1 is connected to the second Driver 2. When VIN is less than VOUT, SEL is equal to 1 (the output end SEL of a highest voltage selection comparator COMP 1), Mp2 is conducted, Mp3 is cut off, the potential of the interconnection body end of Mp0 and Mp1 is equal to VOUT, VA is zero potential, and Mp1 is conducted at low resistance. When VIN is smaller than and close to VOUT and equal to VOUT, the on-time of Mn0 is shortened, the on-time of Mp0 is prolonged and even close to the whole period, and VOUT basically has no voltage ripple. When VIN is greater than VOUT, SEL is equal to 0, Mp2 is turned off, Mp3 is turned on, the potential of the interconnection body terminal of Mp0 and Mp1 is equal to VIN, Mp0 and Mn0 are normally turned on and off, Mp1 can turn on the freewheeling current to achieve VOUT stabilization, and the voltage ripple of VOUT is maintained in a small state.
Fig. 2 is a schematic circuit structure diagram of the gate Driver2 of the second PMOS transistor Mp1 in fig. 1. When SEL is equal to 0, Mp4 is turned off, Mp5 is turned on, and VMAX is equal to VIN. The VA voltage is determined by the Mp6 gate-source voltage difference and the Mp7 gate-source voltage difference.
The reference numbers are listed below: VIN-input voltage terminal or input voltage; VOUT-output voltage terminal or output voltage; GND-ground; driver 1-first drive circuit; driver 2-second drive circuit; driver 3-a third drive circuit; PON-first control signal; SEL-second control signal or highest voltage selects comparator output end; NON-third control signal; VA-second node or second node voltage or second drive circuit output end; SW-first node or switch node voltage; VMAX — third node or third node voltage; l1 — first inductance; i1 — a first current source; i2 — a second current source; COMP 1-first comparator or highest voltage selection comparator; NG 1-first inverter; NG 2-second inverter; mp 0-Mp 7-first to eighth PMOS tubes; mn 0-Mn 1-first to second NMOS transistors.
Detailed Description
The invention is described below with reference to the accompanying drawings (fig. 1-2).
Fig. 1 is a schematic circuit diagram of a boost converter embodying the present invention. Fig. 2 is a schematic circuit structure diagram of the gate Driver2 of the second PMOS transistor Mp1 in fig. 1. Referring to fig. 1 to 2, a boost converter includes a first PMOS power switch Mp0 driven by a first control signal PON through a first Driver1, and a first NMOS transistor Mn0 driven by a third control signal NON through a third Driver3, introducing a second PMOS power switch Mp1, the second PMOS power switch Mp1 forming a series combination with the first PMOS power switch Mp0, the second PMOS power switch Mp1 driven by a second control signal SEL through a second Driver 2. The source electrode of the first PMOS power switch tube Mp0 is connected with an output voltage end VOUT, the drain electrode of the first PMOS power switch tube Mp0 is connected with the source electrode of the second PMOS power switch tube Mp1, the drain electrodes of the second PMOS power switch tube Mp1 and the first NMOS tube Mn0 are interconnected to form a switch node SW, the switch node SW is connected with an input voltage end VIN through a first inductor L1, and the source electrode of the first NMOS tube Mn0 is connected with a ground terminal GND. The first PMOS power switch tube Mp0 is connected to an interconnection node where the body end (substrate) of the second PMOS power switch tube Mp1 is interconnected and then connected to the body end and the drain end of the third PMOS tube Mp2 and the fourth PMOS tube Mp3, the source of the third PMOS tube Mp2 is connected to an output voltage terminal VOUT, the source of the fourth PMOS tube Mp3 is connected to an input voltage terminal VIN, the gate of the third PMOS tube Mp2 is connected to the output terminal of the first inverter NG1, the input terminal of the first inverter NG1 is connected to the output terminal SEL of the highest voltage selection comparator COMP1, the gate of the fourth PMOS tube Mp3 is connected to the output terminal SEL of the highest voltage selection comparator COMP1, the positive input terminal (+) of the highest voltage selection comparator is connected to the output voltage terminal VOUT, and the negative input terminal (-) of the highest voltage selection comparator is connected to the input voltage terminal VIN. The second control signal SEL is the output end signal of the highest voltage selection comparator COMP 1.
The second driving circuit Driver2 includes a fifth PMOS transistor Mp4 and a sixth PMOS transistor Mp5, the drain of the fifth PMOS transistor Mp4 is connected to the output voltage terminal VOUT, the drain of the sixth PMOS transistor Mp5 is connected to the input voltage terminal VIN, the gate of the fifth PMOS transistor Mp4 is connected to the output terminal of the second inverter NG2, the input terminal of the second inverter NG2 is connected to the output terminal SEL of the highest voltage selection comparator COMP1, and the gate of the sixth PMOS transistor Mp5 is connected to the output terminal SEL of the highest voltage selection comparator COMP 1. The source electrode of the fifth PMOS transistor Mp4 is connected to the source electrode of a seventh PMOS transistor Mp6, the gate-drain of the seventh PMOS transistor Mp6 is connected to the ground terminal GND through a first current source I1 after being interconnected, the source electrode of the sixth PMOS transistor Mp5 is connected to the output terminal VA of the second driving circuit, the source electrode of the eighth PMOS transistor Mp7 and the drain electrode of the second NMOS transistor Mn1 through a second current source I2, the eighth PMOS transistor Mp7 is connected to the gate electrode of the seventh PMOS transistor Mp6, the drain electrode of the eighth PMOS transistor Mp7 and the source electrode of the second NMOS transistor Mn1 are both connected to the ground terminal GND, and the gate electrode of the second NMOS transistor Mn1 is connected to the output terminal SEL of the highest voltage selection comparator COMP 1.
As shown in fig. 1, the normal Boost operation principle is to control the on and off of Mp0 and Mn0 through PON and NON signals: when NON is H, Mn0 is turned on, and Mp0 is turned off; when PON is H, Mp0 turns on and Mn0 turns off. The invention introduces a power switch tube Mp1 connected with the Mp0 in series.
When VIN is smaller than VOUT, the output SEL of the highest voltage selection comparator COMP1 becomes 1, Mp2 is turned on, and Mp3 is turned off. The body terminals of Mp0 and Mp1 are connected to VOUT potential. Fig. 2 shows a gate Driver2 of Mp 1. Since SEL is equal to 1, Mp4 turns on, Mp5 turns off, and the third node voltage VMAX is equal to VOUT potential. Mn1 is turned on to connect the second node voltage VA to zero potential, and Mp1 is turned on with low resistance. The loop control mode adopts an inductive current valley value control mode, namely, the current of the Mp0 tube is sampled to be used as current loop feedback. When VIN is close to or equal to VOUT, the loop control will make the turn-on time of Mn0 very short for each switching cycle, and Mp0 turn-on time is close to the whole cycle. Since the current sampling is the upper pipe Mp0 of the sampling, the minimum on-time is not limited, and the situation that the voltage ripple of VOUT becomes large does not occur.
When VIN is greater than VOUT, the output SEL of the highest voltage selection comparator COMP1 becomes 0, Mp2 is turned off, and Mp3 is turned on. The terminals of Mp0 and Mp1 are connected to the VIN potential. Since SEL is equal to 0, Mp4 of the Mp1 gate Driver2 is turned off, Mp5 is turned on, and the third node voltage VMAX is equal to VIN potential. Mn1 is turned off and the voltage at second node VA is biased to a slightly lower potential than VIN, such as VIN-0.7V. The voltage of the second node VA is determined by the difference between the gate-source voltage of Mp6 and the gate-source voltage of Mp 7. Mp0 and Mn0 are still switched on and off in the normal control manner, the loop control still maintains the inductor current valley control mode, and the current sampling still samples Mp 0. Since VA is 0.7V lower than VIN, assuming that the Mp0 turn-on voltage is-0.9V, the high level of the first node SW in the negative half period is approximately equal to VIN +0.2V, so that Mp1 can conduct and freewheel to realize VOUT voltage stabilization, and the ripple of VOUT is substantially the same as the ripple in normal boost operation and is relatively small. Meanwhile, the high level of the SW in the negative half period is only about 0.2V higher than the VIN, the consumption is relatively small, and therefore, the conversion efficiency is relatively high.
It is pointed out here that the above description is helpful for the person skilled in the art to understand the invention, but does not limit the scope of protection of the invention. Any such equivalents, modifications and/or omissions as may be made without departing from the spirit and scope of the invention may be resorted to.
Claims (1)
1. A boost converter comprises a first PMOS power switch tube driven by a first control signal through a first driving circuit and a first NMOS power switch tube driven by a third control signal through a third driving circuit, and is characterized in that a second PMOS power switch tube is introduced, the second PMOS power switch tube and the first PMOS power switch tube form a series combination, and the second PMOS power switch tube is driven by a second control signal through a second driving circuit;
the second driving circuit comprises a fifth PMOS tube and a sixth PMOS tube, wherein the source electrodes of the fifth PMOS tube and the sixth PMOS tube are interconnected, the drain electrode of the fifth PMOS tube is connected with an output voltage end, the drain electrode of the sixth PMOS tube is connected with an input voltage end, the grid electrode of the fifth PMOS tube is connected with the output end of a second phase inverter, the input end of the second phase inverter is connected with the output end of a highest voltage selection comparator, and the grid electrode of the sixth PMOS tube is connected with the output end of the highest voltage selection comparator;
the source electrode of the fifth PMOS tube is connected with the source electrode of a seventh PMOS tube, the gate and drain of the seventh PMOS tube are connected with a ground terminal through a first current source after being interconnected, the source electrode of the sixth PMOS tube is respectively connected with the output end of the second driving circuit, the source electrode of the eighth PMOS tube and the drain electrode of the second NMOS tube through a second current source, the eighth PMOS tube is interconnected with the gate electrode of the seventh PMOS tube, the drain electrode of the eighth PMOS tube and the source electrode of the second NMOS tube are both connected with the ground terminal, and the gate electrode of the second NMOS tube is connected with the output end of the highest voltage selection comparator;
the source electrode of the fifth PMOS tube is connected with the output end of the second driving circuit;
the source electrode of the first PMOS power switch tube is connected with an output voltage end, the drain electrode of the first PMOS power switch tube is connected with the source electrode of the second PMOS power switch tube, the drain electrodes of the second PMOS power switch tube and the first NMOS tube are interconnected to form a switch node, the switch node is connected with the input voltage end through a first inductor, and the source electrode of the first NMOS tube is connected with a grounding end;
the first PMOS power switch tube and the second PMOS power switch tube are connected with an interconnection node, the end of which is interconnected with the end of a third PMOS tube and a fourth PMOS tube, and the drain electrode of which are interconnected, the source electrode of the third PMOS tube is connected with an output voltage end, the source electrode of the fourth PMOS tube is connected with an input voltage end, the grid electrode of the third PMOS tube is connected with the output end of a first phase inverter, the input end of the first phase inverter is connected with the output end of a highest voltage selection comparator, the grid electrode of the fourth PMOS tube is connected with the output end of the highest voltage selection comparator, the positive input end of the highest voltage selection comparator is connected with the output voltage end, and the negative input end of the highest voltage selection comparator is connected with the input voltage end;
the second control signal is an output end signal of the highest voltage selection comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911323182.5A CN113014094B (en) | 2019-12-20 | 2019-12-20 | Boost converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911323182.5A CN113014094B (en) | 2019-12-20 | 2019-12-20 | Boost converter |
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| Publication Number | Publication Date |
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| CN113014094A CN113014094A (en) | 2021-06-22 |
| CN113014094B true CN113014094B (en) | 2022-07-12 |
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| CN201911323182.5A Active CN113014094B (en) | 2019-12-20 | 2019-12-20 | Boost converter |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101171678A (en) * | 2005-06-17 | 2008-04-30 | 罗姆股份有限公司 | Semiconductor device, power supply device, and information processing device |
| CN101330253A (en) * | 2007-06-20 | 2008-12-24 | 株式会社理光 | Switching regulator and motiono control method thereof |
| CN103294098A (en) * | 2012-02-29 | 2013-09-11 | 精工电子有限公司 | Voltage regulator |
| CN105337500A (en) * | 2014-06-27 | 2016-02-17 | 意法半导体研发(深圳)有限公司 | Power converter and method for adjusting linear transient response of power converter |
| CN105915056A (en) * | 2016-05-30 | 2016-08-31 | 武汉新芯集成电路制造有限公司 | Boost circuit preventing reverse current |
-
2019
- 2019-12-20 CN CN201911323182.5A patent/CN113014094B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101171678A (en) * | 2005-06-17 | 2008-04-30 | 罗姆股份有限公司 | Semiconductor device, power supply device, and information processing device |
| CN101330253A (en) * | 2007-06-20 | 2008-12-24 | 株式会社理光 | Switching regulator and motiono control method thereof |
| CN103294098A (en) * | 2012-02-29 | 2013-09-11 | 精工电子有限公司 | Voltage regulator |
| CN105337500A (en) * | 2014-06-27 | 2016-02-17 | 意法半导体研发(深圳)有限公司 | Power converter and method for adjusting linear transient response of power converter |
| CN105915056A (en) * | 2016-05-30 | 2016-08-31 | 武汉新芯集成电路制造有限公司 | Boost circuit preventing reverse current |
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| CN113014094A (en) | 2021-06-22 |
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