CN113013006A - Upper electrode and reaction chamber - Google Patents
Upper electrode and reaction chamber Download PDFInfo
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- CN113013006A CN113013006A CN202110234174.4A CN202110234174A CN113013006A CN 113013006 A CN113013006 A CN 113013006A CN 202110234174 A CN202110234174 A CN 202110234174A CN 113013006 A CN113013006 A CN 113013006A
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- upper electrode
- horizontal direction
- plasma
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32532—Electrodes
- H01J37/32568—Relative arrangement or disposition of electrodes; moving means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/02—Details
- H01J37/04—Arrangements of electrodes and associated parts for generating or controlling the discharge, e.g. electron-optical arrangement, ion-optical arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/30—Electron-beam or ion-beam tubes for localised treatment of objects
- H01J37/305—Electron-beam or ion-beam tubes for localised treatment of objects for casting, melting, evaporating or etching
- H01J37/3053—Electron-beam or ion-beam tubes for localised treatment of objects for casting, melting, evaporating or etching for evaporating or etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32532—Electrodes
- H01J37/32541—Shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67069—Apparatus for fluid treatment for etching for drying etching
Abstract
The invention provides an upper electrode and a reaction chamber, comprising: the module comprises a plurality of modules which are arranged in the horizontal direction, the number of the modules is more than or equal to 2, the lower surface of each module comprises a curved surface and/or a plane, and the plane comprises a plane parallel to the horizontal direction and a plane inclined to the horizontal direction. Therefore, when the plasma flows out of the modules of the upper electrode, the moving direction of the plasma is adjusted through the modules, and the moving direction of the plasma can be adjusted through each module, so that the moving direction of the plasma flowing out of the upper electrode can be accurately adjusted, the plasma acts on the surface of the wafer as vertically as possible, the etching rate on the wafer is uniform, and the electrical property and the yield of a semiconductor finished product are improved.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to an upper electrode and a reaction chamber.
Background
In the manufacturing process of a semiconductor device, plasma treatment is a key process for processing a wafer into a design pattern, and plasma flows out through a through hole of an upper electrode, moves towards the surface of the wafer under the action of an electric field between the upper electrode and a lower electrode, and performs physical bombardment or chemical action with the surface of the wafer so as to treat the wafer.
In general, the direction of the plasma flowing out of the through holes of the upper electrode is not the same, the plasma in the central region acts substantially perpendicularly on the wafer, and the plasma in the peripheral region has a certain angle with the wafer. Because the different directions of plasma motion lead to the slope of certain angle of some deep grooves that the sculpture obtained, the deep groove of slope influences semiconductor processing technology and even influences the electrical property and the yield of semiconductor finished product.
Therefore, an upper electrode is needed to improve the moving direction of the plasma and to improve the electrical performance and yield of the semiconductor product.
Disclosure of Invention
Accordingly, the present invention is directed to an upper electrode and a reaction chamber for improving the moving direction of plasma and increasing the electrical property and yield of semiconductor products.
In order to achieve the purpose, the invention has the following technical scheme:
an upper electrode, comprising:
a plurality of modules arranged in a horizontal direction, the number of the modules being greater than or equal to 2;
the lower surface of each module comprises a curved surface and/or a plane, and the plane comprises a plane parallel to the horizontal direction and a plane inclined to the horizontal direction.
Optionally, the plurality of modules are arranged in a horizontal direction.
Optionally, the modules are annularly nested in the horizontal direction.
Optionally, the modules are sequentially arranged, the upper surfaces of the modules are flush, and the lower surface of each module is continuous with the lower surface of an adjacent module.
Optionally, an outermost module of the plurality of modules has a downwardly protruding structure with respect to a module adjacent to the outermost module.
Optionally, the method further includes: a substrate;
the upper portions of the plurality of modules are connected to the substrate.
Optionally, the upper portions of the plurality of modules are connected to the substrate by screws.
Optionally, a filler is disposed between adjacent modules of the plurality of modules.
Optionally, at least one through hole is formed in the modules, and the through hole is used for introducing plasma.
A reaction chamber, comprising:
the upper electrode and the lower electrode are arranged in parallel opposite to the upper electrode.
An upper electrode provided in an embodiment of the present invention includes: the module comprises a plurality of modules which are arranged in the horizontal direction, the number of the modules is more than or equal to 2, the lower surface of each module comprises a curved surface and/or a plane, and the plane comprises a plane parallel to the horizontal direction and a plane inclined to the horizontal direction. Therefore, when the plasma flows out of the modules of the upper electrode, the moving direction of the plasma is adjusted through the modules, and the moving direction of the plasma can be adjusted through each module, so that the moving direction of the plasma flowing out of the upper electrode can be accurately adjusted, the plasma acts on the surface of the wafer as vertically as possible, the etching rate on the wafer is uniform, and the electrical property and the yield of a semiconductor finished product are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 shows a schematic view of a structure of an upper electrode;
FIG. 2 shows a schematic diagram of an etched structure;
FIG. 3 is a schematic diagram illustrating a top view of an upper electrode and a cross-sectional structure of a module according to an embodiment of the invention;
FIG. 4 is a schematic diagram illustrating a top view of an upper electrode according to an embodiment of the present invention;
5-8 are schematic cross-sectional views of an upper electrode according to an embodiment of the present invention;
FIG. 9 is a schematic cross-sectional view of a reaction chamber according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
As described in the background section, the direction of the plasma flowing out of the through holes 102 of the upper electrode 100 is not the same, and as shown in fig. 1, the plasma in the central region acts substantially vertically on the wafer 110, and the plasma in the peripheral region is at an angle to the wafer 110. Since the etched part of the deep trench 120 is inclined at a certain angle due to the different moving directions of the plasma, referring to fig. 2, the inclined deep trench 120 affects the semiconductor processing process and even affects the electrical property and yield of the semiconductor product. Therefore, an upper electrode is needed to improve the moving direction of the plasma and to improve the electrical performance and yield of the semiconductor product.
To this end, an embodiment of the present application provides an upper electrode, including: the module comprises a plurality of modules which are arranged in the horizontal direction, the number of the modules is more than or equal to 2, the lower surface of each module comprises a curved surface and/or a plane, and the plane comprises a plane parallel to the horizontal direction and a plane inclined to the horizontal direction. Therefore, when the plasma flows out of the modules of the upper electrode, the moving direction of the plasma is adjusted through the modules, and the moving direction of the plasma can be adjusted through each module, so that the moving direction of the plasma flowing out of the upper electrode can be accurately adjusted, the plasma acts on the surface of the wafer as vertically as possible, the etching rate on the wafer is uniform, and the electrical property and the yield of a semiconductor finished product are improved.
In order to facilitate understanding of the technical solutions and effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
An upper electrode 130 provided in an embodiment of the present application is shown in fig. 3 to 7, and includes:
a plurality of modules 132 arranged in a horizontal direction, the number of the modules 132 being greater than or equal to 2;
the lower surface of each module 132 includes curved surfaces and/or flat surfaces including a surface parallel to the horizontal direction and a surface inclined to the horizontal direction.
In the embodiment of the present application, the upper electrode 130 includes a plurality of modules 132, the number of the modules 132 is greater than or equal to 2, and the number of the modules 132 may be determined according to specific situations, for example, may be 5, because the size of the upper electrode 130 is generally determined according to the size of the reaction chamber, that is, the size of the upper electrode 130 is generally fixed, and under the condition that the size of the upper electrode 130 is fixed, if the requirement for the flatness of the surface of the wafer to be etched is high, the number of the modules 132 may be increased; if the requirement for the flatness of the surface of the wafer to be etched is low, the number of modules 132 can be reduced. It can be understood that the greater the number of modules 132, the more precisely the moving direction of the plasma flowing out of the upper electrode 130 can be adjusted.
The plurality of modules 132 are arranged in a horizontal direction, and referring to fig. 3, fig. 3 is a schematic top view structure of the upper electrode 130 and a schematic cross-sectional structure of the modules 132, for convenience of description, the horizontal direction may be referred to as an X direction and a Y direction, the X direction is perpendicular to the Y direction, and the plurality of modules 132 may be arranged in the X direction, the Y direction, or both the X direction and the Y direction.
The lower surface of each module 132 includes curved surfaces and/or flat surfaces including a surface parallel to the horizontal direction and a surface inclined to the horizontal direction. Specifically, the lower surface of each module may include a curved surface, may include a plane, and the plane includes a plane parallel to the horizontal direction and a plane inclined to the horizontal direction, and may also include a curved surface and a plane, where the plane inclined to the horizontal direction may be a plane having a certain included angle with the horizontal direction, and the degree of the included angle may be greater than 0 degree and less than 180 degrees. The lower surfaces of the plurality of modules 132 may be the same or different, and may be the same curved surface, the same flat surface, or a combination of the same curved surface and the same flat surface, for example. The bottom surfaces of some of the modules 132 in the plurality of modules 132 may be the same, such as the same curved surface, the same flat surface, or a combination of the same curved surface and the same flat surface. The lower surface of each module 132 may include one or more curved surfaces, may include one or more flat surfaces, may include one curved surface and a plurality of flat surfaces, may include one flat surface and a plurality of curved surfaces, and may include a plurality of flat surfaces and a plurality of curved surfaces, and obviously, the curved surface in this application is a surface whose curvature is not 0.
In this embodiment, the lower surfaces of the modules 132 may include curved surfaces, as shown in fig. 5, fig. 5 is a schematic cross-sectional structure diagram of the upper electrode, and after the modules 132 are sequentially arranged in the horizontal direction, the upper surfaces of the modules 132 are flush, and the lower surface of each module may be continuous with the lower surface of an adjacent module, that is, the lower surfaces of the modules 132 may be continuous. When the lower surfaces of the plurality of modules 132 are continuous, the lower surfaces of the plurality of modules 132 may form a continuous curved surface; of course, the lower surfaces of the adjacent modules 132 may also be discontinuous, and the lower surface formed by combining the modules 132 includes a plurality of discontinuous curved surfaces, and the number of the discontinuous curved surfaces is the same as that of the modules 132; or the lower surfaces of some of the adjacent modules 132 in the plurality of modules 132 may be continuous, and the lower surface formed by combining the plurality of modules 132 is still a plurality of discontinuous curved surfaces, and the number of the discontinuous curved surfaces is smaller than the number of the modules 132. The lower surface of each module 132 may include one or more curved surfaces, and when the lower surface of the module 132 includes a plurality of curved surfaces, the curvature of some of the plurality of curved surfaces is different.
Referring to fig. 6, fig. 6 is a schematic cross-sectional view of an upper electrode, and after the modules 132 are arranged in the horizontal direction, the lower surfaces of each module 132 and the adjacent module 132 may be continuous or discontinuous. When the lower surfaces of each module 132 and the adjacent module 132 are continuous, the lower surfaces of the modules 132 are continuous, and the lower surfaces of the modules 132 form a broken line surface; when the lower surfaces of the partial modules 132 and the adjacent modules 132 are discontinuous, the lower surfaces of the modules 132 are discontinuous, and the lower surface formed by combining the modules 132 is a plurality of discontinuous planes, and the number of the discontinuous planes is the same as that of the modules 132; or the lower surfaces of some of the modules 132 may be continuous, and the lower surfaces of the modules 132 are discontinuous planes, and the number of the discontinuous planes is less than the number of the modules 132. The lower surface of each module 132 may include one or more flat surfaces.
Referring to fig. 7, fig. 7 is a schematic cross-sectional view of an upper electrode, and after the modules 132 are arranged in the horizontal direction, the lower surfaces of each module 132 and the adjacent module 132 may be continuous or discontinuous. The lower surfaces of each module 132 and the adjacent module 132 are continuous, so that the lower surfaces of the modules 132 are continuous, and the lower surfaces formed by combining the modules 132 are alternately arranged in a curved surface and a plane; the lower surface of each module 132 is discontinuous with the lower surface of the adjacent module 132, and the lower surface formed by combining the plurality of modules 132 is discontinuous. If the lower surfaces of some of the modules 132 in the plurality of modules 132 are continuous, they may form a continuous surface with alternating curved surfaces and planes, and if the lower surfaces of the plurality of modules 132 are discontinuous, the lower surface formed by the arrangement of the plurality of modules 132 is discontinuous and includes a plurality of surfaces. The lower surface of each module 132 may include a curved surface and a plurality of flat surfaces, or a flat surface and a plurality of curved surfaces, or a plurality of flat surfaces and a plurality of curved surfaces.
In some embodiments, the plurality of modules 132 may be arranged in a horizontal array, as shown in fig. 3, that is, the plurality of modules 132 arranged in sequence are included in the X direction, the plurality of modules 132 arranged in sequence are included in the Y direction, lower surfaces of the plurality of modules 132 arranged in sequence in the X direction may have the same or different surfaces, lower surfaces of the plurality of modules arranged in sequence in the Y direction may have the same or different surfaces, for example, a lower surface of the module 1321 may be a plane parallel to the horizontal direction, a lower surface of the module 1322 may be a curved surface, and a lower surface of the module 1323 may be an inclined surface. In other embodiments, the modules 132 may also be arranged in a ring-shaped manner in a nested manner in a horizontal direction, specifically, each module 132 has a ring structure, as shown in fig. 4, and each module has a different size, and the module 132 with a large size is nested in the periphery of the module 132 with a small size.
The lower surfaces of the plurality of modules 132 form a continuous surface, and the sides of adjacent modules 132 that are adjacent or in contact have the same size and shape. As exemplified by the arrangement of the plurality of modules 132 in a horizontal direction, the X direction includes five modules, and as shown in fig. 5, for convenience of description, the five modules are sequentially ordered, and referred to as a first module 1324, a second module 1325, a third module 1326, a fourth module 1327, and a fifth module 1328, the sides of the first module 1324 in contact with the second module 1325 have the same size and shape, the sides of the second module 1325 in contact with the third module 1326 have the same size and shape, the sides of the third module 1326 in contact with the fourth module 1327 have the same size and shape, and the sides of the fourth module 1327 in contact with the fifth module 1328 have the same size and shape. For example, referring to fig. 4, the 2 nd module 1326 'is sleeved on the periphery of the 1 st module 1327', the 3 rd module 1325 'is sleeved on the periphery of the 2 nd module 1326', the 4 th module 1324 'is sleeved on the outer side of the 3 rd module 1325', the bottom of the side of the 1 st module 1327 'contacting the 2 nd module 1326' has the same size and shape, the bottom of the side of the 2 nd module 1326 'contacting the 3 rd module 1325' has the same size and shape, and the bottom of the side of the 3 rd module 1325 'contacting the 4 th module 1324' has the same size and shape.
In the present embodiment, the outermost module 132 among the plurality of modules 132 has a downwardly protruding structure with respect to the module 132 adjacent to the outermost module 132, as shown in fig. 5 to 7, to define the moving direction of the plasma onto the wafer. Specifically, a direction perpendicular to the horizontal direction is referred to as a Z direction, and when a plurality of modules 132 are arrayed in the horizontal direction, the outermost module 132 in the X direction has a structure protruding downward with respect to the outermost module 132, that is, in the Z direction, the size of the outermost module 132 is larger than the size of the module 132 adjacent to the outermost module 132; the outermost module 132 in the Y direction has a structure protruding downward with respect to the outermost module 132, i.e., the size of the outermost module 132 is larger than the size of the module adjacent to the outermost module 132 in the Z direction. Specifically, a side surface of the outermost module 132, which is in contact with the adjacent module 132, may be referred to as a first side surface, and a side surface opposite to the first side surface may be referred to as a second side surface, and a dimension of the second side surface in the Z direction may be larger than a dimension of the first side surface in the Z direction. In a specific application, the lower surface of the protruding structure may be curved, or flat, or a combination of curved and flat surfaces.
In this embodiment, the method further includes: the substrate 134, the upper portions of the plurality of modules 132 and the substrate 134 are connected, as shown in fig. 8, that is, the upper surfaces of the plurality of modules 132 are connected to one side of the substrate 134, the upper portions of the plurality of modules 132 and the substrate 134 may be connected by screws 136, and the plurality of modules 132 may be sequentially arranged in the horizontal direction of the substrate 134. A filler may be formed between adjacent modules 132 of the plurality of modules 132 to fill gaps between the adjacent modules 132.
In a specific application, at least one through hole 160 is disposed on a plurality of modules 132, and as shown in fig. 5-7, for example, one or more through holes 160 are disposed on each module 132, or one or more through holes 160 are disposed on some modules 132, and the through holes 160 are used for introducing plasma. Specifically, when the upper electrode 130 is connected to a radio frequency source, the process gas forms a plasma under the action of radio frequency excitation, and the plasma moves to the surface of the wafer under the action of an electric field between the upper electrode and the lower electrode through the through hole 160 of the module 132 in the upper electrode 130.
The upper electrode provided by the embodiment of the application is described in detail above, when the plasma flows out of the modules of the upper electrode, the motion direction of the plasma is adjusted through the modules, and since each module can adjust the motion direction of the plasma, the motion direction of the plasma flowing out of the upper electrode can be accurately adjusted, so that the plasma acts on the surface of the wafer as vertically as possible, the etching rate on the wafer is distributed uniformly, and the electrical property and the yield of a semiconductor finished product are improved.
The embodiment of the present application further provides a reaction chamber 200, as shown in fig. 9, including:
the upper electrode 130 and the lower electrode 140 disposed opposite to and parallel to the upper electrode 130.
In a specific application, when the wafer 150 needs to be subjected to the plasma etching process, the wafer 150 is placed on the lower electrode 140 in the reaction chamber 200, or on a wafer carrying device (not shown) on the lower electrode 140, and then when the upper electrode 130 is connected to the rf source, the process gas forms a plasma under the rf excitation, and the plasma moves toward the surface of the wafer 150 under the electric field between the upper electrode 140 and the lower electrode 140, so as to perform the etching process on the wafer 150.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the reaction chamber embodiment, since it is substantially similar to the upper electrode embodiment, it is described more simply, and in relation thereto, reference is made to the partial description of the electrode embodiment above.
The foregoing is only a preferred embodiment of the present invention, and although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (10)
1. An upper electrode, comprising:
a plurality of modules arranged in a horizontal direction, the number of the modules being greater than or equal to 2;
the lower surface of each module comprises a curved surface and/or a plane, and the plane comprises a plane parallel to the horizontal direction and a plane inclined to the horizontal direction.
2. The upper electrode according to claim 1, wherein the plurality of modules are arranged in an array in a horizontal direction.
3. The upper electrode as claimed in claim 1, wherein the plurality of modules are annularly nested in a horizontal direction.
4. The upper electrode according to claim 1, wherein the plurality of modules are arranged in sequence with the upper surfaces flush, and the lower surface of each module is continuous with the lower surface of an adjacent module.
5. The upper electrode according to claim 1, wherein an outermost module of the plurality of modules has a downwardly protruding structure with respect to a module adjacent to the outermost module.
6. The upper electrode according to any one of claims 1 to 5, further comprising: a substrate;
the upper portions of the plurality of modules are connected to the substrate.
7. The upper electrode as claimed in claim 6, wherein upper portions of the plurality of modules are connected to the substrate by screws.
8. The upper electrode according to any one of claims 1 to 5, wherein a filler is provided between adjacent modules of the plurality of modules.
9. The upper electrode according to any one of claims 1 to 5, wherein at least one through hole is provided on the plurality of modules, and the through hole is used for introducing plasma.
10. A reaction chamber, comprising:
the upper electrode of any of claims 1-9 and a lower electrode disposed parallel and opposite to the upper electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110234174.4A CN113013006B (en) | 2021-03-03 | 2021-03-03 | Upper electrode and reaction chamber |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110234174.4A CN113013006B (en) | 2021-03-03 | 2021-03-03 | Upper electrode and reaction chamber |
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| Publication Number | Publication Date |
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| CN113013006A true CN113013006A (en) | 2021-06-22 |
| CN113013006B CN113013006B (en) | 2022-01-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202110234174.4A Active CN113013006B (en) | 2021-03-03 | 2021-03-03 | Upper electrode and reaction chamber |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5609690A (en) * | 1994-02-15 | 1997-03-11 | Matsushita Electric Industrial Co., Ltd. | Vacuum plasma processing apparatus and method |
| JP2000208483A (en) * | 1999-01-08 | 2000-07-28 | Mitsubishi Electric Corp | Method and system for processing wafer |
| US20020170676A1 (en) * | 2000-01-10 | 2002-11-21 | Mitrovic Andrej S. | Segmented electrode apparatus and method for plasma processing |
| US20030121886A1 (en) * | 2000-05-12 | 2003-07-03 | Strang Eric J. | Method of adjusting the thickness of an electrode in a plasma processing system |
| US20130340941A1 (en) * | 2012-06-20 | 2013-12-26 | Tel Solar Ag | Lens offset |
| US20140299273A1 (en) * | 2013-04-08 | 2014-10-09 | Lam Research Corporation | Multi-segment electrode assembly and methods therefor |
-
2021
- 2021-03-03 CN CN202110234174.4A patent/CN113013006B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5609690A (en) * | 1994-02-15 | 1997-03-11 | Matsushita Electric Industrial Co., Ltd. | Vacuum plasma processing apparatus and method |
| JP2000208483A (en) * | 1999-01-08 | 2000-07-28 | Mitsubishi Electric Corp | Method and system for processing wafer |
| US20020170676A1 (en) * | 2000-01-10 | 2002-11-21 | Mitrovic Andrej S. | Segmented electrode apparatus and method for plasma processing |
| US20030121886A1 (en) * | 2000-05-12 | 2003-07-03 | Strang Eric J. | Method of adjusting the thickness of an electrode in a plasma processing system |
| US20130340941A1 (en) * | 2012-06-20 | 2013-12-26 | Tel Solar Ag | Lens offset |
| US20140299273A1 (en) * | 2013-04-08 | 2014-10-09 | Lam Research Corporation | Multi-segment electrode assembly and methods therefor |
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| Publication number | Publication date |
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| CN113013006B (en) | 2022-01-21 |
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