CN113011121B - Variable-step-size fine discrete mapping modeling method for ultrahigh frequency switching converter - Google Patents
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Abstract
The invention discloses a variable-step-size fine discrete mapping modeling method of an ultrahigh frequency switching converter, which consists of a traditional mapping link, a mode switching time calculation link and a modified mapping link, wherein the traditional mapping link simulates a system by using a discrete mapping model, a switching time positioning link calculates accurate system state switching time according to a simulation result, and the modified mapping link corrects an existing calculation result according to the mode switching time to reduce model errors, so that the accurate modeling of the ultrahigh frequency switching converter is realized.
Description
Technical Field
The invention relates to the technical field of ultrahigh frequency switching converters, in particular to a variable step size fine discrete mapping modeling method of an ultrahigh frequency switching converter.
Background
The discrete mapping model is a classical modeling method in the field of power electronics, and is used for solving numerical solutions of complex differential equations in a short time interval. The modeling method is basically characterized in that a continuous system is discretized according to a fixed step length, an approximate solution of the system in the step length is solved through an approximation method, and then the working state of the system is described.
The traditional discrete mapping model has the characteristics that: the system of differential equations is discretized such that the complex system of differential equations can be solved by numerical solution. However, when the method is applied to the ultrahigh frequency switching converter, the fixed model step length causes the problems of large model error and long operation time.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, provides a variable-step-size fine discrete mapping modeling method of an ultrahigh frequency switching converter, and can realize the accurate modeling of the ultrahigh frequency switching converter.
In order to achieve the purpose, the technical scheme provided by the invention is as follows: a variable step size fine discrete mapping modeling method for an ultrahigh frequency switching converter is characterized in that the running process of the ultrahigh frequency switching converter is decomposed according to set time step sizes, and discrete mapping modeling is carried out on each time step size, and the method comprises the following steps:
s1, selecting a system state variable of the switching converter as an initial state, and starting the calculation of the current time step;
s2, judging the mode of the switching converter with the current step length according to the initial state of the system of the switching converter determined in the step S1, and selecting the duration time of the current step length according to the time constant of the mode;
s3, calculating the system state of the step length ending time by using a discrete mapping method according to the mode and the step length duration determined in the step S2, namely mapping the initial state of the switching converter system of the step length starting time to the step length ending time;
s4, judging whether the system of the switching converter generates mode switching in the time step according to the system state of the switching converter at the step length end time calculated in the step S3; if the modality switching occurs, executing step S5-1, if the modality switching does not occur, executing step S5-2;
s5-1, according to the result obtained by the judgment in the step S4, if the system of the switching converter is switched in mode, the dichotomy is used for solving the accurate moment of mode switching, the system state of the switching converter at the step end moment is subjected to reverse discrete mapping to the switching moment to serve as the final system state obtained by calculating the time step, and when the next time step starts, the obtained final system state serves as the initial state of the next time step, and the calculation of a new time step is restarted;
and S5-2, if the system of the switching converter has not mode switching according to the judgment result of the step S4, taking the system state of the switching converter at the step ending moment obtained by the calculation of the step S3 as the final system state obtained by the calculation of the time step, and when the next time step starts, taking the final system state as the initial state of the next time step and restarting the calculation of a new time step.
In step S2, the minimum time constant of the system mode of the current switching converter is compared with the sampling duration of the converter, and the minimum value is selected as the duration of the current time step.
In step S5-1, the time step is used as an initial solution interval to solve the system state of the midpoint of the interval, and the midpoint state is compared with the two end point states of the time step to determine the left half interval or the right half interval of the midpoint as a new solution interval, the system state of the midpoint of the solution interval is repeatedly calculated, and the length of the solution interval is continuously reduced until the length of the solution interval meets the precision requirement, and then the time corresponding to the midpoint of the solution interval is used as the precise time when the switching converter mode changes.
In step S5-1, an inverse discrete mapping modeling method is established, and the system state of the switching converter at a given time is calculated according to the system state of the switching converter at the time, wherein the inverse discrete mapping modeling method is as follows:
x(ts)＝Φi(Δt)x(t+t0)+Ψi(Δt)u(t+t0),i＝1,2,3...m
Δt＝ts-(t+t0)
in the formula: t denotes the starting time, t0Representing a single time step, tsIndicating the precise moment when the system mode of the switching converter is switched; Δ t represents the time from the precise moment when the system mode of the switching converter is switched to the end moment of the time step, and the value of Δ t is negative; x (t)s) Indicating the switching converter at tsSystem state at time, x (t + t)0) Indicating the switching converter is at t + t0System state at time u (t + t)0) Indicating the switching converter at time t + t0I represents the system modality, m represents the number of system modalities, j represents the sum variable in the sum formula, j! Denotes the factorial of the coefficient j, e denotes the natural logarithm, Ai、BiRepresenting the state matrix, phi, of the switching converter system in mode ii(Δt)、Ψi(Δ t) are respectively the matrix Ai、BiDiscrete form over time at, phii(Δ t- τ) is the discrete form of the matrix over time Δ t- τ; for Ai、BiAt any starting time t, there is
x (t) is the system state of the switching converter at time t,
is the derivative of the state variable of the system of the switching converter at time t.
Compared with the prior art, the invention has the following advantages and beneficial effects:
1. the modeling method establishes a discrete mapping model with modified mapping, can effectively inhibit error accumulation generated by modal change of the switching converter, and improves the modeling accuracy of the switching converter.
2. The modeling method adopts a dichotomy to solve the modal switching accurate time, and divides the modeling of each mode of the switching converter by taking the modal switching time as a demarcation point. The model significance is clearer, and the modeling for each switch mode is more targeted.
3. The modeling method adopts different time step lengths aiming at different modes of the switching converter, improves the operation speed, reduces the data storage amount and improves the model performance on the premise of ensuring the operation precision.
4. The modeling method selects a fixed amount of data to be stored, and continuously covers old data with new operation results, so that the problems of traditional simulation data accumulation and memory overflow are solved.
Drawings
FIG. 1 is a control logic diagram of the method of the present invention.
FIG. 2 is a circuit diagram of the verification method of the present invention.
Fig. 3 is a comparison graph of the inductance current waveform calculated by the method of the present invention.
FIG. 4 is a comparison graph of voltage waveforms of the capacitor calculated by the method of the present invention.
FIG. 5 is a graph comparing the output voltage waveforms calculated by the method of the present invention.
Detailed Description
The present invention will be described in further detail with reference to examples and drawings, but the present invention is not limited thereto.
As shown in fig. 1, the step-size-variable fine discrete mapping modeling method for the ultra-high frequency switching converter provided in this embodiment includes the following specific steps:
s1, selecting a system state variable of the switching converter as an initial state, and starting the calculation of the current time step;
s2, judging the mode of the switching converter with the current step length according to the initial state of the system of the switching converter determined in the step S1, and selecting the duration time of the current step length according to the time constant of the mode;
s3, calculating the system state of the step length ending time by using a discrete mapping method according to the mode and the step length duration determined in the step S2, namely mapping the initial state of the switching converter system of the step length starting time to the step length ending time;
s4, judging whether the system of the switching converter generates mode switching in the time step according to the system state of the switching converter at the step length end time calculated in the step S3; if the modality switching occurs, executing step S5-1, if the modality switching does not occur, executing step S5-2;
s5-1, according to the result obtained by the judgment in the step S4, if the system of the switching converter is switched in mode, the dichotomy is used for solving the accurate moment of mode switching, the system state of the switching converter at the step end moment is subjected to reverse discrete mapping to the switching moment to serve as the final system state obtained by calculating the time step, and when the next time step starts, the obtained final system state serves as the initial state of the next time step, and the calculation of a new time step is restarted;
and S5-2, if the system of the switching converter has not mode switching according to the judgment result of the step S4, taking the system state of the switching converter at the step ending moment obtained by the calculation of the step S3 as the final system state obtained by the calculation of the time step, and when the next time step starts, taking the final system state as the initial state of the next time step and restarting the calculation of a new time step. .
As shown in fig. 2, a specific implementation circuit diagram is provided. The implementation circuit of the method of the invention consists of a main circuit and a control circuit, wherein the main circuit consists of a soft switch SEPIC converter and comprises an input direct current power supply and an input end energy storage inductor L1DC blocking capacitor C1N-channel MOS tube and switched capacitor C2And an output end energy storage inductor L2Power diode D1Reverse parallel diode D of switch tube2An output capacitor CoAnd the control circuit comprises a sampling module, a hysteresis comparison module and a driving circuit module. The main circuit is specifically constructed as follows: the positive pole of the input voltage source is connected with the energy storage inductor L of the input end1A section of (1), energy storage inductance L1Another end of (1) and a blocking capacitor C1One end of the N-channel MOS tube is connected with the D pole of the N-channel MOS tube, and the D pole of the N-channel MOS tube is connected with the switch capacitor C2One end of the switching tube is connected with a diode D in reverse parallel2Is connected with the cathode of the N-channel MOS tube, the S pole of the N-channel MOS tube is connected with the switch capacitor C2The other end of the switch tube is connected with a diode D in reverse parallel2Is connected with the anode of the capacitor C1Another terminal of (2) and a power diode D1Energy storage inductor L at anode and output end2Connected, power diode D1The cathode of the output capacitor C is connected with one end of an output load, the other end of the output load is connected with the other end of the output capacitor C, the S pole of the N-channel MOS tube and an output end energy storage inductor L2The other end of the input power supply is connected with the cathode of the input power supply. The control loop comprises a voltage sampling module, a hysteresis controller module and a drive circuit module, and outputs a voltage UoThe voltage is transmitted to a hysteresis comparison module through a voltage sampling module and is compared with the upper limit voltage V of the hysteresis comparison moduleupperAnd a lower limit voltage VlowerAfter comparison, the output driving circuit works andand if not, when the driving circuit works, the driving circuit sends a pulse signal to the G pole of the N-channel MOS tube at a fixed duty ratio to realize the work of the converter.
Establishing a variable-step fine discrete mapping model for the UHF SEPIC converter shown in FIG. 2, firstly defining a converter state variable x (t) as
x(t)＝[iL1(t) iL2(t) uC1(t) uo(t) uC2(t)]T
Where t denotes the system time, iL1(t) represents the input end energy storage inductor L1Current of (i)L2(t) represents the output end energy storage inductor L2Current of (u)C1(t) represents a blocking capacitance C1Voltage across uo(t) denotes the output inductance CoVoltage across uC2(t) represents a switched capacitor C2The two terminal voltages, T, represent the transpose of the vector.
The working process of the ultrahigh frequency SEPIC converter can be divided into 5 modes according to the switching state, and each mode can be described as a linear differential equation
Wherein,
the derivative of the state variable x (t) of the switching converter system at time t, u (t), represents the input variable of the switching converter at time t. A. the1、A2…A5And B1、B2…B5Are constant matrixes of state equations under each mode, wherein a mode 1 state matrix is the same as a mode 5, a mode 2 state matrix is the same as a mode 4, and each matrix is defined as follows
Wherein L is2Representing the energy storage inductance L of the output terminal2Inductance value of, C1Represents a blocking capacitance C1Capacitance value of RoRepresenting the resistance of the load at the output, CoRepresenting the output capacitance CoCapacitance value of L1Representing input end energy storage inductance L1Inductance value of, C2Representing switched capacitance C2Capacitance value of RDRepresenting a power diode D1Equivalent on-resistance of UDRepresenting a power diode D1Conducting voltage drop of, UinRepresenting the voltage value of the converter input voltage.
The above formula is pressed by a fixed step length t0Discretizing to obtain discrete mapping model
x(t+t0)＝Φi(t0)x(t)+Ψi(t0)u(t),i＝1,2,3...m
Wherein, x (t + t)0) Indicating the switching converter is at t + t0The system state at the moment, i represents the current mode of the system, m represents the number of modes of the system, j represents the summation variable in the summation formula, j! Denotes the factorization of the coefficient j and e denotes the natural logarithm. A. thei、BiRepresenting the state matrix, phi, of the switching converter system in mode ii(t0)、Ψi(t0) Are respectively a matrix Ai、BiAt time step t0Internal discrete form, phii(Δ t- τ) is the discrete form of the matrix over time Δ t- τ.
When a time step begins, firstly, the mode of the converter system is determined according to the initial state of the converter system, and the duration time t of the step is selected according to the minimum time constant of the RC component in the corresponding state matrix and the minimum value of the model sampling time interval0. Duration t of the selected step0Then, since the initial state x (t) of the system is determined, the system state x (t + t) at the end of the step length can be calculated according to the discrete mapping model0). Comparing the system state with x (t) to judge whether the system generates mode switching in the step length.
When the mode switching of the system is judged to occur within the step length, the model solves the accurate time of the mode switching through a dichotomy. The specific implementation mode is as follows: and taking the time step as an initial solving interval, solving the system state of the midpoint in the interval, and comparing the midpoint state with the states of the two end points of the time step to determine the left half interval or the right half interval of the midpoint as a new solving interval. And repeatedly calculating the system state of the midpoint of the solving interval, and continuously reducing the length of the solving interval until the length of the solving interval meets the precision requirement, and taking the moment corresponding to the midpoint of the solving interval as an approximate solution of the precise moment when the mode of the switching converter changes.
Solving to obtain the accurate time t of system modal switchingsThen, the discrete mapping method is also used to end the system state x (t + t) of the step size0) Reverse mapping to time t of modality switchingsInverse mapping of a publicThe formula is as follows:
x(ts)＝Φi(Δt)x(t+t0)+Ψi(Δt)u(t+t0),i＝1,2,3...m
Δt＝ts-(t+t0)
in the formula, tsThe time interval Δ t represents the time from the time when the system mode of the switching converter is switched to the time step end time, and the value is negative. x (t)s) Indicating the switching converter at tsSystem state at time u (t + t)0) Indicating the switching converter at time t + t0Input variable of phii(Δt)、Ψi(Δ t) are respectively the matrix Ai、BiDiscrete form over time at, phii(Δ t- τ) is the discrete form of the matrix over time Δ t- τ.
The time t of the system mode switching is obtained by reverse mappingsSystem state x (t)s) Then, t is addedsAs the end time of the step length, x (t) is sets) And the final system state obtained by calculation of the step length is used as the final system state, the simulation of the step length is finished, the final system state is used as the initial state of the system of the next step length, and the simulation of the next step length is started.
When judging that the system does not have modal switching in the step length, t + t is used0As the end time of the step, x (t + t)0) And the final system state obtained by calculation of the step length is used as the final system state, the simulation of the step length is finished, the final system state is used as the initial state of the system of the next step length, and the simulation of the next step length is started.
As shown in fig. 3, a comparison graph of the calculation result of the variable-step fine discrete mapping modeling method of the ultra-high frequency switching converter of the present invention and the PSIM simulation result is shown. The dotted line waveform represents the blocking capacitor voltage calculated by the proposed modeling method, and the solid line waveform represents the blocking capacitor voltage obtained by the same circuit device in the PSIM simulation. The two waveforms are almost completely overlapped, demonstrating the accuracy of the proposed model.
As shown in fig. 4, a comparison graph of the calculation result of the variable-step fine discrete mapping modeling method of the ultra-high frequency switching converter of the present invention and the PSIM simulation result is shown. The waveform of the dotted line represents the waveform of the input end energy storage inductor calculated by the proposed modeling method, and the waveform of the solid line represents the waveform of the input end energy storage inductor obtained by the same circuit device in the PSIM simulation. The two waveforms are almost completely overlapped, demonstrating the accuracy of the proposed model.
As shown in fig. 5, a comparison graph of the calculation result of the variable-step fine discrete mapping modeling method of the ultra-high frequency switching converter of the present invention and the PSIM simulation result is shown. The dashed waveform represents the output voltage waveform calculated by the proposed modeling method, and the solid waveform represents the output voltage waveform obtained by the same circuit device in the PSIM simulation. The waveforms of the two have only small deviation, which shows that the proposed model can accurately describe the change of the output voltage.
The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.
Claims (4)
1. A variable step size fine discrete mapping modeling method of an ultrahigh frequency switching converter is characterized by comprising the following steps: the method decomposes the operation process of the ultrahigh frequency switching converter according to the set time step length, and carries out discrete mapping modeling on each time step length, and comprises the following steps:
s1, selecting a system state variable of the switching converter as an initial state, and starting the calculation of the current time step;
s2, judging the mode of the switching converter with the current step length according to the initial state of the system of the switching converter determined in the step S1, and selecting the duration time of the current step length according to the time constant of the mode;
s3, calculating the system state of the step length ending time by using a discrete mapping method according to the mode and the step length duration determined in the step S2, namely mapping the initial state of the switching converter system of the step length starting time to the step length ending time;
s4, judging whether the system of the switching converter generates mode switching in the time step according to the system state of the switching converter at the step length end time calculated in the step S3; if the modality switching occurs, executing step S5-1, if the modality switching does not occur, executing step S5-2;
s5-1, according to the result obtained by the judgment in the step S4, if the system of the switching converter is switched in mode, the dichotomy is used for solving the accurate moment of mode switching, the system state of the switching converter at the step end moment is subjected to reverse discrete mapping to the switching moment to serve as the final system state obtained by calculating the time step, and when the next time step starts, the obtained final system state serves as the initial state of the next time step, and the calculation of a new time step is restarted;
and S5-2, if the system of the switching converter has not mode switching according to the judgment result of the step S4, taking the system state of the switching converter at the step ending moment obtained by the calculation of the step S3 as the final system state obtained by the calculation of the time step, and when the next time step starts, taking the final system state as the initial state of the next time step and restarting the calculation of a new time step.
2. The method of claim 1, wherein the step-size-variable fine discrete mapping modeling for the UHF switching converter is as follows: in step S2, the minimum time constant of the system mode of the current switching converter is compared with the sampling duration of the converter, and the minimum value is selected as the duration of the current time step.
3. The method of claim 1, wherein the step-size-variable fine discrete mapping modeling for the UHF switching converter is as follows: in step S5-1, the time step is used as an initial solution interval to solve the system state of the midpoint of the interval, and the midpoint state is compared with the two end point states of the time step to determine the left half interval or the right half interval of the midpoint as a new solution interval, the system state of the midpoint of the solution interval is repeatedly calculated, and the length of the solution interval is continuously reduced until the length of the solution interval meets the precision requirement, and then the time corresponding to the midpoint of the solution interval is used as the precise time when the switching converter mode changes.
4. The method of claim 1, wherein the step-size-variable fine discrete mapping modeling for the UHF switching converter is as follows: in step S5-1, an inverse discrete mapping modeling method is established, and the system state of the switching converter at a given time is calculated according to the system state of the switching converter at the time, wherein the inverse discrete mapping modeling method is as follows:
x(ts)＝Φi(Δt)x(t+t0)+Ψi(Δt)u(t+t0),i＝1,2,3...m
Δt＝ts-(t+t0)
in the formula: t denotes the starting time, t0Representing a single time step, tsIndicating the precise moment when the system mode of the switching converter is switched; delta t represents the system mode switching of the switching converterThe time from the precise time to the time step end time is negative in value; x (t)s) Indicating the switching converter at tsSystem state at time, x (t + t)0) Indicating the switching converter is at t + t0System state at time u (t + t)0) Indicating the switching converter at time t + t0I represents the system modality, m represents the number of system modalities, j represents the sum variable in the sum formula, j! Denotes the factorial of the coefficient j, e denotes the natural logarithm, Ai、BiRepresenting the state matrix, phi, of the switching converter system in mode ii(Δt)、Ψi(Δ t) are respectively the matrix Ai、BiDiscrete form over time at, phii(Δ t- τ) is the discrete form of the matrix over time Δ t- τ; for Ai、BiAt any starting time t, there is
x (t) is the system state of the switching converter at time t,
is the derivative of the state variable of the system of the switching converter at time t.
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| WO2017042388A1 (en) * | 2015-09-11 | 2017-03-16 | Abb Schweiz Ag | Optimized pulse patterns for mmc control |
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