CN113010469A - Image feature extraction method, device and computer-readable storage medium - Google Patents
Image feature extraction method, device and computer-readable storage medium Download PDFInfo
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Abstract
The invention relates to the technical field of image processing, in particular provides an image feature extraction method, an image feature extraction device and a computer readable storage medium, and aims to solve the technical problem of how to effectively improve the image feature extraction efficiency. For this purpose, according to the method of the embodiment of the present invention, a configuration file of an FPGA can be generated according to an operator of each neural network layer in an image feature extraction model, the FPGA is configured according to the configuration file, so as to form a plurality of operator processing modules capable of respectively simulating operation of each operator on the FPGA, and to enable line data of an input image to be sequentially transmitted to the corresponding operator processing modules in a data stream manner according to a sequence of operation of each operator, each operator processing module performs parallel feature extraction on a plurality of line data respectively input thereto, and the configured FPGA can be used to synchronously complete extraction of image features in a process of acquiring the input image, thereby significantly improving extraction efficiency of image features.
Description
Technical Field
The invention relates to the technical field of image processing, in particular to an image feature extraction method and device and a computer readable storage medium.
Background
Image recognition (image identification) mainly recognizes different image objects according to image features by extracting the image features. At present, the conventional image recognition method mainly uses an image recognition model constructed based on a neural network for image recognition, and in order to improve the accuracy of image recognition, the neural network with a more complex network structure is often adopted for constructing the image recognition model. However, because the network structure is complex, the neural network needs a large amount of calculation when extracting image features, which significantly affects the recognition speed of image objects. Therefore, the image recognition method cannot be applied to application scenes with high requirements on image recognition accuracy and real-time performance, such as automatic driving of vehicles and the like.
Disclosure of Invention
In order to overcome the above-mentioned drawbacks, the present invention is proposed to provide an image feature extraction method, an apparatus, and a computer-readable storage medium that solve or at least partially solve the technical problem of how to effectively improve the image feature extraction efficiency.
In a first aspect, an image feature extraction method is provided, and the method includes:
acquiring an image feature extraction model based on a neural network, and generating a configuration file of an FPGA according to an operator of each neural network layer in the image feature extraction model;
configuring the FPGA according to the configuration file so as to form a plurality of operator processing modules capable of respectively simulating the operation of each operator on the FPGA and sequentially transmit line data of an input image to the operator processing module corresponding to each operator in a data stream mode according to the sequence of the operation of each operator in the image feature extraction model;
performing feature extraction on an image to be identified by using the configured FPGA;
wherein each operator processing module is configured to perform parallel feature extraction on the plurality of input line data respectively.
In one technical solution of the above image feature extraction method, before the step of "generating a configuration file of an FPGA according to an operator of each neural network layer in the image feature extraction model", the method further includes:
respectively carrying out low-bit quantization processing on the operator parameter of each operator and/or carrying out operator fusion on the operators of the plurality of neural network layers;
and/or the method further comprises storing the operator parameters of each neural network layer separately by:
judging whether the bit number of the operator parameter of the current neural network layer is less than or equal to a preset bit number threshold value or not; if yes, storing the operator parameters of the current neural network layer to an on-chip memory of the FPGA; and if not, storing the operator parameters of the current neural network layer to a preset external memory.
In one technical solution of the image feature extraction method, the step of "configuring the FPGA according to the configuration file" specifically includes:
acquiring operator parameters of operators in each neural network layer in the configuration file;
classifying the neural network layers according to the comparison result of the bit number of the operator parameter and a preset bit number threshold value to form a first type of neural network layer and a second type of neural network layer, wherein the bit number of the operator parameter in the first type of neural network layer is less than or equal to the preset bit number threshold value, and the bit number of the operator parameter in the second type of neural network layer is greater than the preset bit number threshold value;
configuring an LUT lookup table in the FPGA according to the operator parameters to form a plurality of first operator processing modules based on the LUT lookup table, each first operator processing module being configured to simulate operator operation of each first type of neural network layer;
configuring a DSP processor in the FPGA according to the operator parameters to form a plurality of second operator processing modules based on the DSP processor, wherein each second operator processing module is respectively configured to simulate operator operation of each second type of neural network layer.
In one aspect of the above image feature extraction method, the second operator processing module is further configured to perform parallel feature extraction on a plurality of lines of data of the input image respectively using a plurality of DSP processors.
In a second aspect, there is provided an image feature extraction apparatus, the apparatus comprising:
the configuration file generation module is configured to acquire an image feature extraction model based on a neural network, and generate a configuration file of the FPGA according to an operator of each neural network layer in the image feature extraction model;
the FPGA configuration module is configured to configure the FPGA according to the configuration file so as to form a plurality of operator processing modules capable of respectively simulating the operation of each operator on the FPGA and sequentially transmit line data of an input image to the operator processing modules corresponding to the operators in a data stream mode according to the sequence of the operation of each operator in the image feature extraction model;
the feature extraction module is configured to extract features of the image to be recognized by using the configured FPGA;
wherein each operator processing module is configured to perform parallel feature extraction on the plurality of input line data respectively.
In one embodiment of the image feature extraction apparatus, the configuration file generation module includes a model compression unit and a configuration file generation unit; the model compression unit is configured to perform low-bit quantization processing on the operator parameter of each operator and/or perform operator fusion on operators of a plurality of neural network layers; the configuration file generation unit is configured to generate a configuration file of the FPGA according to the image feature extraction model compressed by the model compression unit;
the FPGA configuration module comprises a parameter storage configuration unit, and the parameter storage configuration unit is configured to store operator parameters of each neural network layer respectively in the following ways:
judging whether the bit number of the operator parameter of the current neural network layer is less than or equal to a preset bit number threshold value or not; if yes, storing the operator parameters of the current neural network layer to an on-chip memory of the FPGA; and if not, storing the operator parameters of the current neural network layer to a preset external memory.
In an aspect of the above image feature extraction apparatus, the FPGA configuration module is further configured to perform the following operations:
acquiring operator parameters of each operator in the configuration file;
classifying the neural network layers according to the comparison result of the bit number of the operator parameter and a preset bit number threshold value to form a first type of neural network layer and a second type of neural network layer, wherein the bit number of the operator parameter in the first type of neural network layer is less than or equal to the preset bit number threshold value, and the bit number of the operator parameter in the second type of neural network layer is greater than the preset bit number threshold value;
configuring an LUT lookup table in the FPGA according to the operator parameters to form a plurality of first operator processing modules based on the LUT lookup table, each first operator processing module being configured to simulate operator operation of each first type of neural network layer;
configuring a DSP processor in the FPGA according to the operator parameters to form a plurality of second operator processing modules based on the DSP processor, wherein each second operator processing module is respectively configured to simulate operator operation of each second type of neural network layer.
In one aspect of the above image feature extraction device, the second operator processing module is further configured to perform parallel feature extraction on a plurality of lines of data of the input image using a plurality of DSP processors, respectively.
In a third aspect, a control device is provided, which comprises a processor and a storage device, wherein the storage device is suitable for storing a plurality of program codes, and the program codes are suitable for being loaded and run by the processor to execute the image feature extraction method of any one of the above-mentioned image feature extraction methods.
In a fourth aspect, a computer-readable storage medium is provided, in which a plurality of program codes are stored, the program codes being adapted to be loaded and run by a processor to execute the image feature extraction method according to any one of the above-mentioned aspects of the image feature extraction method.
One or more technical schemes of the invention at least have one or more of the following beneficial effects:
in the technical scheme of the invention, the configuration file of the FPGA can be generated according to the operator of each neural network layer in the image feature extraction model, and the FPGA is configured according to the configuration file, so that the configured FPGA can replace the image feature extraction model to extract the features of the image to be identified. Specifically, by configuring the FPGA, a plurality of operator processing modules capable of simulating operation of each operator respectively can be formed on the FPGA, and line data of an input image is sequentially transmitted to the operator processing module corresponding to each operator in a data stream manner according to a sequence of operation of each operator in the image feature extraction model, wherein each operator processing module is configured to perform parallel feature extraction on a plurality of line data input respectively. Through the steps, the neural network structure of the image feature extraction model can be deployed on the FPGA, so that the operation logic of the FPGA for extracting the features is consistent with the operation logic of the image feature extraction model for extracting the features; meanwhile, each operator can perform parallel feature extraction on a plurality of lines of data input by each operator respectively, the processing speed of feature extraction operation logic is improved, so that the feature extraction can be started by all the operator processing modules without acquiring a frame of complete input image and then performing image feature extraction, and when the acquisition of a frame of input image is completed, the operator processing modules can also synchronously complete the image feature extraction of the frame of input image, namely the image feature extraction is synchronously completed in the process of acquiring the input image, and the image feature extraction efficiency is remarkably improved.
Drawings
Embodiments of the invention are described below with reference to the accompanying drawings, in which:
fig. 1 is a flow chart illustrating the main steps of an image feature extraction method according to an embodiment of the present invention;
FIG. 2 is a flow diagram illustrating the main steps of a FPGA configuration method according to one embodiment of the present invention;
fig. 3 is a main configuration block diagram of an image feature extraction device according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a process in which a plurality of operator processing modules run in parallel, according to one embodiment of the invention;
fig. 5 is a schematic diagram of an application scenario of the present invention.
List of reference numerals:
11: a configuration file generation module; 12: an FPGA configuration module; 13: and a feature extraction module.
Detailed Description
Some embodiments of the invention are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are only for explaining the technical principle of the present invention, and are not intended to limit the scope of the present invention.
In the description of the present invention, a "module" or "processor" may include hardware, software, or a combination of both. A module may comprise hardware circuitry, various suitable sensors, communication ports, memory, may comprise software components such as program code, or may be a combination of software and hardware. The processor may be a central processing unit, microprocessor, image processor, digital signal processor, or any other suitable processor. The processor has data and/or signal processing functionality. The processor may be implemented in software, hardware, or a combination thereof. Non-transitory computer readable storage media include any suitable medium that can store program code, such as magnetic disks, hard disks, optical disks, flash memory, read-only memory, random-access memory, and the like. The term "a and/or B" denotes all possible combinations of a and B, such as a alone, B alone or a and B. The term "at least one A or B" or "at least one of A and B" means similar to "A and/or B" and may include only A, only B, or both A and B. The singular forms "a", "an" and "the" may include the plural forms as well.
Some terms to which the present invention relates are explained first.
The image feature extraction model based on the Neural network refers to a Neural network model which is constructed based on the Neural network (analog Neural network) and can extract image features so as to perform operations such as image recognition or image classification according to the image features. It should be noted that the image feature extraction model in the embodiment of the present invention may be a model independent from other models, or may be a part of other models. For example, the image feature extraction model may be an image feature extraction module in an image recognition model or an image classification model based on a neural network, and the image feature extraction model is an indispensable model structure of the image recognition model or the image classification model.
The FPGA refers to a Field Programmable Gate Array (Field Programmable Gate Array), the configuration file of the FPGA refers to a file including parameter configuration for each device in the FPGA, and the configuration file can be set according to a function requirement of using the FPGA, so that a corresponding function can be realized by operating the FPGA after the FPGA is configured according to the configuration file. It should be noted that, in the embodiment of the present invention, a conventional method for generating an FPGA configuration file may be adopted, and the configuration file of the FPGA is generated according to the obtained information, which is not described herein again for brevity of description.
The LUT lookup Table of the FPGA refers to a lookup Table (Look-Up-Table) preset on the FPGA and capable of configuring logic operation repeatedly, and different logic functions can be realized by programming different files to configure the contents of the lookup Table. The LUT is essentially a RAM, and for example, the LUT can be regarded as a RAM with 4-bit address lines, and true values of all possible results of the logic circuit are written into the RAM, so that each time a signal is input for logic operation, the input is equal to an address for table lookup, the content corresponding to the address is found, and then the address is output.
The DSP processor of the FPGA refers to a Digital Signal processor (Digital Signal processor) preset on the FPGA, and the number of the DSP processors may be one or more.
The operator of the neural network layer refers to a data operation mode executed by the neural network layer on input data. For example, if the neural network layer is a convolutional layer, then the operator of the convolutional layer is a convolution operation; if the neural network layer is a pooling layer, then the operators of the pooling layer are pooling operations. The operator parameters of the operator refer to parameters required for performing operator operation. For example: if the operator is a convolution operation, the operator parameters may include convolution weights for the convolution operation.
Referring to fig. 5, in an example of an application scenario of the present invention, a station is installed with a camera device and an image recognition system for recognizing a license plate number of a vehicle, where the image recognition system is a system constructed based on a neural network and capable of communicating with the camera device to obtain an image collected by the camera device for license plate number recognition. In order to improve the identification efficiency of the license plate number, an image feature extraction model in an image identification system can be obtained, a neural network structure in the image feature extraction model and an operator of each neural network layer in the neural network structure are obtained by adopting the image feature extraction method according to one embodiment of the invention, generating a configuration file of the FPGA according to an operator of a neural network layer, replacing an image feature extraction model with the FPGA configured by the configuration file, namely, connecting the configured FPGA with a camera device in a communication way, enabling the configured FPGA to directly acquire an image acquired by the camera device and extracting image features, meanwhile, the configured FPGA outputs the extracted image characteristics to a background server provided with an image recognition system, so that the background server can directly send the image characteristics to a characteristic identification module in the image identification system for license plate number identification according to the image characteristics. As shown in fig. 5, the FPGA configured by the configuration file may include devices such as an image preprocessing module, n operator processing modules (operator processing modules 1-n), and an external memory access module. The image preprocessing module can receive image data collected by the camera device, such as line data of an image, perform data preprocessing such as denoising on the image data, then send the processed image data to the operator processing module for feature extraction, and image features output by the operator processing module can be transmitted to a background server of the image recognition system through a data exchange device such as a communication device. The operator parameters of the neural network can be stored in an external memory when the FPGA is configured, and the FPGA can call the corresponding operator parameters from the external memory through an external memory access module when the FPGA is used for feature extraction. In addition, the configuration file can also be sent to the FPGA by the background server through the data exchange device and the FPGA is configured. The camera device can also send the acquired images to the background server through the data exchange device, so that the background server can perform other image processing operations by using the original images.
In the application scene, all the operator processing modules in the configured FPGA can run in parallel (simultaneously perform feature extraction on respective input data), and each operator processing module can perform parallel feature extraction on a plurality of line data of an input image, so that a camera device is not required to acquire a complete input image, only a part of line data of the input image is required to be acquired, the operator processing modules can start to perform feature extraction, when the camera device finishes acquisition of a frame of input image, the operator processing modules can also synchronously finish image feature extraction on the frame of input image, namely, the image feature extraction is synchronously finished in the process of acquiring the input image, so that the image feature extraction efficiency is obviously improved, and the license plate number identification efficiency is further improved.
Referring to fig. 1, fig. 1 is a flow chart illustrating main steps of an image feature extraction method according to an embodiment of the present invention. As shown in fig. 1, the image feature extraction method in the embodiment of the present invention mainly includes the following steps S101 to S103.
Step S101: and generating a configuration file of the FPGA according to the operator of each neural network layer in the image feature extraction model.
The meanings of the image feature extraction model, the operators of the neural network layer, the FPGA and the configuration file thereof in the embodiment of the invention can be referred to the term explanation, and are not described herein again.
The more complex the neural network structure is, the more the calculation amount of the feature extraction is increased, and the extraction efficiency of the feature extraction is reduced. Therefore, the image feature extraction model can be firstly subjected to model compression, and then the configuration file of the FPGA is generated according to the image feature extraction model after the model compression, so that the model structure of the image feature extraction model carried on the FPGA is simplified, the calculation pressure of the FPGA is reduced, and the image features of the input image can be extracted more quickly and accurately. Specifically, in one embodiment, the image feature extraction model may be model compressed by: and respectively carrying out low-bit quantization processing on the operator parameter of each operator and/or carrying out operator fusion on the operators of a plurality of neural network layers.
The low bit quantization process refers to reducing the number of bits of the operator parameter, for example, if the number of bits of the operator parameter is 32 bits, the number of bits can be reduced to less than 32 bits, such as 16 bits, 8 bits, etc., through the low bit quantization process. It should be noted that, in this embodiment, the number of bits of the operator parameter may be reduced by using a conventional bit quantization method in the field of data conversion, for example, a numerical mapping method is used to map the operator parameter into a numerical interval with a low number of bits. For brevity of description, detailed description of specific steps of the bit quantization method is omitted here.
Operator fusion refers to fusing/merging operators of multiple neural network layers into a single operator. For example: if the image feature extraction model comprises a convolution layer A and a pooling layer B which are connected, the convolution layer A outputs an operation result to the pooling layer B after performing convolution operation on input data, the pooling layer B performs pooling operation on the operation result output by the convolution layer A, then a convolution operator a of the convolution layer A and a pooling operator B of the pooling layer B can be fused into a single operator c, and the fused operator c can perform convolution operation and pooling operation on the input data in sequence.
Step S102: and configuring the FPGA according to the configuration file so as to form a plurality of operator processing modules capable of respectively simulating the operation of each operator on the FPGA and sequentially transmit line data of the input image to the operator processing module corresponding to each operator in a data stream mode according to the sequential operation sequence of each operator in the image feature extraction model. Wherein each operator processing module can be respectively configured to perform parallel feature extraction on a plurality of lines of data respectively input.
In the embodiment of the present invention, the operator processing module is a module capable of simulating operator operations of the neural network layer, for example, if an operator of a certain neural network layer is a convolution operator, the correspondingly formed operator processing module is capable of simulating an operation process of the convolution operator, and performing convolution operations on data (line data of the input image) input to the operator processing module. The number of operator processing modules formed on the FPGA can be determined by the number of neural network layers in the neural network structure of the image feature extraction model. For example, if the neural network structure includes a convolutional layer, a pooling layer, and a fully-connected layer connected in sequence, three operator processing modules may be formed on the FPGA, each configured to simulate operator operations of the convolutional layer, the pooling layer, and the fully-connected layer, respectively. In addition, in this embodiment, the operation mode of the operator processing module may be understood as an operation mode that simultaneously adopts an internal and external parallel operation mode, where the external parallel operation refers to that different operator processing modules are operated in parallel, that is, a plurality of operator processing modules formed on the FPGA are operated simultaneously. The internal parallel operation refers to that the operator processing module performs parallel processing on a plurality of input data, namely, the operator processing module performs processing on each input data simultaneously.
Referring to fig. 4, in one embodiment, four operator processing modules (operator processing modules 1 to 4) are formed on the FPGA after the FPGA is configured according to the configuration file, the operator processing modules 1 to 4 are respectively configured to simulate the operation of convolution operators 1 to 4 of the convolution layers 1 to 4, parallel feature extraction is performed on respective input data, and line data of an input image is sequentially transmitted to each operator processing module in a data stream manner.
At time t0, line data 1 of the input image is input to the operator processing module 1, and the operator processing module 1 performs convolution operation on the line data 1 by simulating the operation of the convolution operator 1 to extract the data features of the line data 1.
At time t1, line data 2 of the input image is input to the operator processing module 1, and line data 1 is input to the operator processing module 2 in a data stream form; the operator processing module 1 performs convolution operation on the line data 2 by simulating the operation of the convolution operator 1 so as to extract the data characteristics of the line data 2; the operator processing module 2 performs convolution operation on the line data 1 through operation of the simulation convolution operator 2 to extract data characteristics of the line data 1. At this time, the operator processing modules 1 and 2 are in a parallel operation state.
At time t2, line data 3 of the input image is input to the operator processing module 1, line data 1 is input to the operator processing module 3 in a data stream form, and line data 2 is input to the operator processing module 2 in a data stream form; the operator processing module 1 performs convolution operation on the line data 3 through the operation of the simulation convolution operator 1 to extract the data characteristics of the line data 3; the operator processing module 2 performs convolution operation on the line data 2 by simulating the operation of the convolution operator 2 so as to extract the data characteristics of the line data 2; the operator processing module 3 performs convolution operation on the line data 1 through the operation of the simulation convolution operator 3 to extract the data characteristics of the line data 1. At this time, the operator processing modules 1 to 3 are in a parallel operation state.
At time t3, line data 4 of the input image is input to the operator processing module 1, line data 1 is input to the operator processing module 4 in a data stream form, line data 2 is input to the operator processing module 3 in a data stream form, and line data 3 is input to the operator processing module 2 in a data stream form; the operator processing module 1 performs convolution operation on the line data 4 by simulating the operation of the convolution operator 1 so as to extract the data characteristics of the line data 4; the operator processing module 2 performs convolution operation on the line data 3 through the operation of the simulation convolution operator 2 to extract the data characteristics of the line data 3; the operator processing module 3 performs convolution operation on the line data 2 through the operation of the simulation convolution operator 3 to extract the data characteristics of the line data 2; the operator processing module 4 performs convolution operation on the line data 1 through operation of the simulation convolution operator 4 to extract data characteristics of the line data 1. At this time, the operator processing modules 1 to 4 are in a parallel operation state.
Further, in an implementation manner of the embodiment of the present invention, different configuration methods may be adopted to configure the FPGA according to a storage space that needs to be occupied by an operator parameter of the neural network layer, so as to form the operator processing module. Specifically, referring to fig. 2, in the present embodiment, the FPGA may be configured according to the following steps S201 to S204.
Step S201: and acquiring operator parameters of operators in each neural network layer in the configuration file.
Step S202: and classifying the neural network layers according to the comparison result of the bit number of the operator parameter and a preset bit number threshold value to form a first type of neural network layer and a second type of neural network layer, wherein the bit number of the operator parameter in the first type of neural network layer is less than or equal to the preset bit number threshold value, and the bit number of the operator parameter in the second type of neural network layer is greater than the preset bit number threshold value. It should be noted that, a person skilled in the art can flexibly set the size of the preset bit number threshold according to actual needs, for example, the bit number threshold may be set to 2 bits.
Step S203: configuring an LUT lookup table in the FPGA according to the operator parameters to form a plurality of first operator processing modules based on the LUT lookup table, each first operator processing module being respectively configurable to simulate operator operations of the first type of neural network layer. That is to say, for the first type of neural network layer in which the operator parameters need to occupy a smaller storage space, the LUT lookup table is used to form a corresponding operator processing module, and the operation of the operator processing module is simulated by performing table lookup on the LUT lookup table, so that the table lookup result can be used as the operation result of the operator processing module. Meanwhile, in the embodiment, the configured LUT can be subjected to table lookup by using a conventional LUT table lookup method in the field of FPGA technology, and details are not repeated herein for brevity of description.
Step S204: and configuring the DSP processor in the FPGA according to the operator parameters to form a plurality of second operator processing modules based on the DSP processor, wherein each second operator processing module can be respectively configured to simulate operator operation of a second type of neural network layer. That is to say, for the second type of neural network layer in which the operator parameters need to occupy a larger storage space, the DSP processor with higher computation processing capability is used to form a corresponding operator processing module, and the DSP processor is used to simulate the operator operation, so that the operation result of the DSP processor can be used as the operation result of the operator processing module.
Through the implementation manner described in step S201 to step S204, the operator processing modules can be formed by adopting different configuration methods according to the bit number of the operator parameter, so that the DSP processor with higher operation capability processes and simulates the operator requiring the operator parameter with a larger bit number, thereby improving the capability of simulating the operation of the operators and further improving the efficiency of the operator processing module for extracting the data features.
As can be seen from the foregoing description of the embodiments, the operator processing module may perform parallel processing on a plurality of input data, and in this embodiment, the operator processing module may be configured to include a plurality of DSP processors, and perform parallel processing on each input data by using the plurality of DSP processors, respectively, that is, in this embodiment, the second operator processing module may be further configured to perform parallel feature extraction on a plurality of pieces of line data of the input image by using the plurality of DSP processors, respectively.
Further, in an implementation manner of the embodiment of the present invention, in addition to configuring the operator processing module according to the configuration file, the storage location of the operator parameter may also be configured. Specifically, in the present embodiment, the operator parameters of each neural network layer may be stored according to the following steps: judging whether the bit number of the operator parameter of the current neural network layer is less than or equal to a preset bit number threshold value or not; if yes, storing the operator parameters of the current neural network layer to an on-chip memory of the FPGA; and if not, storing the operator parameters of the current neural network layer to a preset external memory.
The preset bit number threshold can be flexibly set by those skilled in the art according to actual needs, for example, the preset bit number threshold can be set to 2 bits.
The on-chip Memory of the FPGA refers to a Local Memory (Local Memory) of the FPGA, and is one of indispensable devices constituting the FPGA. The preset external memory refers to a memory which is arranged outside the FPGA and can be in communication connection with the FPGA, relative to the local memory of the FPGA. The on-chip memory of the FPGA may be fixed, so that when the number of operator parameters and the number of bits are large, the on-chip memory of the FPGA may not store all the operator parameters. In addition, if all the operator parameters are stored in the on-chip memory of the FPGA, when the operator processing module calls the operator parameters to perform operator operation, a large memory bandwidth pressure may be brought. In contrast, the operator parameters are stored in different storage positions according to the bit number of the operator parameters, so that the storage pressure and the memory bandwidth pressure of the on-chip memory of the FPGA can be effectively relieved.
Step S103: and performing feature extraction on the image to be recognized by using the configured FPGA, namely inputting the image to be recognized into the configured FPGA, wherein the FPGA can directly output the image features of the image to be recognized.
It should be noted that, although the foregoing embodiments describe each step in a specific sequence, those skilled in the art will understand that, in order to achieve the effect of the present invention, different steps do not necessarily need to be executed in such a sequence, and they may be executed simultaneously (in parallel) or in other sequences, and these changes are all within the protection scope of the present invention.
Furthermore, the invention also provides an image feature extraction device.
Referring to fig. 3, fig. 3 is a main structural block diagram of an image feature extraction apparatus according to an embodiment of the present invention. As shown in fig. 3, the image feature extraction device in the embodiment of the present invention mainly includes a configuration file generation module 11, an FPGA configuration module 12, and a feature extraction module 13. In some embodiments, one or more of the configuration file generation module 11, the FPGA configuration module 12 and the feature extraction module 13 may be combined together into one module. In some embodiments, the configuration file generation module 11 may be configured to obtain an image feature extraction model based on a neural network, and generate a configuration file of the FPGA according to an operator of each neural network layer in the image feature extraction model. The FPGA configuration module 12 may be configured to configure the FPGA according to the configuration file, so as to form a plurality of operator processing modules on the FPGA, which are capable of respectively simulating operations of each operator, and sequentially transmit line data of the input image to the operator processing module corresponding to each operator in a data stream manner according to an operation sequence of each operator in the image feature extraction model. Wherein each operator processing module is respectively configured to perform parallel feature extraction on a plurality of lines of data respectively input. The feature extraction module 13 may be configured to perform feature extraction on the image to be recognized by using the configured FPGA. In one embodiment, the description of the specific implementation function may refer to the description of step S101 to step S103.
In one embodiment, the configuration file generation module 11 may include a model compression unit and a configuration file generation unit, and the FPGA configuration module 12 may include a parameter storage configuration unit. In this embodiment, the model compression unit may be configured to perform low bit quantization processing on the operator parameter of each operator and/or perform operator fusion on the operators of the plurality of neural network layers, respectively. The configuration file generating unit may be configured to generate a configuration file of the FPGA for the image feature extraction model compressed by the model compressing unit. The parameter storage configuration unit may be configured to store the operator parameters of each neural network layer separately by: judging whether the bit number of the operator parameter of the current neural network layer is less than or equal to a preset bit number threshold value or not; if yes, storing the operator parameters of the current neural network layer to an on-chip memory of the FPGA; and if not, storing the operator parameters of the current neural network layer to a preset external memory. In one embodiment, the description of the specific implementation function may refer to steps S101 to S102.
In one embodiment, the FPGA configuration module 12 may be further configured to perform the following operations: acquiring operator parameters of operators in each neural network layer in the configuration file;
classifying the neural network layers according to the comparison result of the bit number of the operator parameter and a preset bit number threshold value to form a first type of neural network layer and a second type of neural network layer, wherein the bit number of the operator parameter in the first type of neural network layer is less than or equal to the preset bit number threshold value, and the bit number of the operator parameter in the second type of neural network layer is greater than the preset bit number threshold value; configuring an LUT lookup table in the FPGA according to the operator parameters to form a plurality of first operator processing modules based on the LUT lookup table, wherein each first operator processing module is respectively configured to simulate operator operation of each first type of neural network layer; and configuring the DSP processor in the FPGA according to the operator parameters to form a plurality of second operator processing modules based on the DSP processor, wherein each second operator processing module is respectively configured to simulate the operator operation of each second type of neural network layer. In one embodiment, the description of the specific implementation function may refer to steps S201 to S204.
In one embodiment, the second operator processing module may be further configured to perform parallel feature extraction on a plurality of line data of the input image using a plurality of DSP processors, respectively. In one embodiment, the description of the specific implementation function may be referred to in step S204.
The technical principles, the solved technical problems and the generated technical effects of the above-mentioned image feature extraction device for implementing the embodiment of the image feature extraction method shown in fig. 1-2 are similar, and it can be clearly understood by those skilled in the art that for convenience and simplicity of description, the specific working process and related description of the image feature extraction device may refer to the content described in the embodiment of the image feature extraction method, and no further description is provided herein.
It will be understood by those skilled in the art that all or part of the flow of the method according to the above-described embodiment may be implemented by a computer program, which may be stored in a computer-readable storage medium and used to implement the steps of the above-described embodiments of the method when the computer program is executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying said computer program code, media, usb disk, removable hard disk, magnetic diskette, optical disk, computer memory, read-only memory, random access memory, electrical carrier wave signals, telecommunication signals, software distribution media, etc. It should be noted that the computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as is required by legislation and patent practice.
Furthermore, the invention also provides a control device. In an embodiment of the control device according to the present invention, the control device comprises a processor and a storage device, the storage device may be configured to store a program for executing the image feature extraction method of the above-mentioned method embodiment, and the processor may be configured to execute the program in the storage device, the program including but not limited to the program for executing the image feature extraction method of the above-mentioned method embodiment. For convenience of explanation, only the parts related to the embodiments of the present invention are shown, and details of the specific techniques are not disclosed. The control device may be a control device apparatus formed including various electronic apparatuses.
Further, the invention also provides a computer readable storage medium. In one computer-readable storage medium embodiment according to the present invention, a computer-readable storage medium may be configured to store a program that executes the image feature extraction method of the above-described method embodiment, and the program may be loaded and executed by a processor to implement the above-described image feature extraction method. For convenience of explanation, only the parts related to the embodiments of the present invention are shown, and details of the specific techniques are not disclosed. The computer readable storage medium may be a storage device formed by including various electronic devices, and optionally, the computer readable storage medium is a non-transitory computer readable storage medium in the embodiment of the present invention.
Further, it should be understood that, since the configuration of each module is only for explaining the functional units of the apparatus of the present invention, the corresponding physical devices of the modules may be the processor itself, or a part of software, a part of hardware, or a part of a combination of software and hardware in the processor. Thus, the number of individual modules in the figures is merely illustrative.
Those skilled in the art will appreciate that the various modules in the apparatus may be adaptively split or combined. Such splitting or combining of specific modules does not cause the technical solutions to deviate from the principle of the present invention, and therefore, the technical solutions after splitting or combining will fall within the protection scope of the present invention.
So far, the technical solution of the present invention has been described with reference to one embodiment shown in the drawings, but it is easily understood by those skilled in the art that the scope of the present invention is obviously not limited to these specific embodiments. Equivalent changes or substitutions of related technical features can be made by those skilled in the art without departing from the principle of the invention, and the technical scheme after the changes or substitutions can fall into the protection scope of the invention.
Claims (10)
1. An image feature extraction method, characterized in that the method comprises:
acquiring an image feature extraction model based on a neural network, and generating a configuration file of an FPGA according to an operator of each neural network layer in the image feature extraction model;
configuring the FPGA according to the configuration file so as to form a plurality of operator processing modules capable of respectively simulating the operation of each operator on the FPGA and sequentially transmit line data of an input image to the operator processing module corresponding to each operator in a data stream mode according to the sequence of the operation of each operator in the image feature extraction model;
performing feature extraction on an image to be identified by using the configured FPGA;
wherein each operator processing module is configured to perform parallel feature extraction on the plurality of input line data respectively.
2. The image feature extraction method according to claim 1, wherein before the step of generating the configuration file of the FPGA according to the operator of each neural network layer in the image feature extraction model, the method further comprises:
respectively carrying out low-bit quantization processing on the operator parameter of each operator and/or carrying out operator fusion on the operators of the plurality of neural network layers;
and/or the like and/or,
the method further comprises storing operator parameters for each neural network layer separately by:
judging whether the bit number of the operator parameter of the current neural network layer is less than or equal to a preset bit number threshold value or not; if yes, storing the operator parameters of the current neural network layer to an on-chip memory of the FPGA; and if not, storing the operator parameters of the current neural network layer to a preset external memory.
3. The image feature extraction method according to claim 1, wherein the step of configuring the FPGA according to the configuration file specifically includes:
acquiring operator parameters of operators in each neural network layer in the configuration file;
classifying the neural network layers according to the comparison result of the bit number of the operator parameter and a preset bit number threshold value to form a first type of neural network layer and a second type of neural network layer, wherein the bit number of the operator parameter in the first type of neural network layer is less than or equal to the preset bit number threshold value, and the bit number of the operator parameter in the second type of neural network layer is greater than the preset bit number threshold value;
configuring an LUT lookup table in the FPGA according to the operator parameters to form a plurality of first operator processing modules based on the LUT lookup table, each first operator processing module being configured to simulate operator operation of each first type of neural network layer;
configuring a DSP processor in the FPGA according to the operator parameters to form a plurality of second operator processing modules based on the DSP processor, wherein each second operator processing module is respectively configured to simulate operator operation of each second type of neural network layer.
4. The image feature extraction method according to claim 3, wherein the second operator processing module is further configured to perform parallel feature extraction on a plurality of line data of the input image using a plurality of the DSP processors, respectively.
5. An image feature extraction device characterized by comprising:
the configuration file generation module is configured to acquire an image feature extraction model based on a neural network, and generate a configuration file of the FPGA according to an operator of each neural network layer in the image feature extraction model;
the FPGA configuration module is configured to configure the FPGA according to the configuration file so as to form a plurality of operator processing modules capable of respectively simulating the operation of each operator on the FPGA and sequentially transmit line data of an input image to the operator processing modules corresponding to the operators in a data stream mode according to the sequence of the operation of each operator in the image feature extraction model;
the feature extraction module is configured to extract features of the image to be recognized by using the configured FPGA;
wherein each operator processing module is configured to perform parallel feature extraction on the plurality of input line data respectively.
6. The image feature extraction device according to claim 5, wherein the profile generation module includes a model compression unit and a profile generation unit; the model compression unit is configured to perform low-bit quantization processing on the operator parameter of each operator and/or perform operator fusion on operators of a plurality of neural network layers; the configuration file generation unit is configured to generate a configuration file of the FPGA according to the image feature extraction model compressed by the model compression unit;
the FPGA configuration module comprises a parameter storage configuration unit, and the parameter storage configuration unit is configured to store operator parameters of each neural network layer respectively in the following ways:
judging whether the bit number of the operator parameter of the current neural network layer is less than or equal to a preset bit number threshold value or not; if yes, storing the operator parameters of the current neural network layer to an on-chip memory of the FPGA; and if not, storing the operator parameters of the current neural network layer to a preset external memory.
7. The image feature extraction device according to claim 5, wherein the FPGA configuration module is further configured to perform the following operations:
acquiring operator parameters of operators in each neural network layer in the configuration file;
classifying the neural network layers according to the comparison result of the bit number of the operator parameter and a preset bit number threshold value to form a first type of neural network layer and a second type of neural network layer, wherein the bit number of the operator parameter in the first type of neural network layer is less than or equal to the preset bit number threshold value, and the bit number of the operator parameter in the second type of neural network layer is greater than the preset bit number threshold value;
configuring an LUT lookup table in the FPGA according to the operator parameters to form a plurality of first operator processing modules based on the LUT lookup table, each first operator processing module being configured to simulate operator operation of each first type of neural network layer;
configuring a DSP processor in the FPGA according to the operator parameters to form a plurality of second operator processing modules based on the DSP processor, wherein each second operator processing module is respectively configured to simulate operator operation of each second type of neural network layer.
8. The image feature extraction device according to claim 7, wherein the second operator processing module is further configured to perform parallel feature extraction on a plurality of line data of the input image using a plurality of the DSP processors, respectively.
9. A control apparatus comprising a processor and a storage device adapted to store a plurality of program codes, wherein said program codes are adapted to be loaded and run by said processor to perform the image feature extraction method of any one of claims 1 to 4.
10. A computer-readable storage medium having stored therein a plurality of program codes, characterized in that the program codes are adapted to be loaded and run by a processor to perform the image feature extraction method of any one of claims 1 to 4.
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