CN113010419A - Program execution method and related device of RISC (reduced instruction-set computer) processor - Google Patents
Program execution method and related device of RISC (reduced instruction-set computer) processor Download PDFInfo
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Abstract
The application discloses a program execution method of a RISC processor, comprising the following steps: adopting a test program of the same kind as the program framework of the program to be executed to carry out hit rate test on the mapping relations of the plurality of caches so as to obtain the hit rate corresponding to each mapping relation of the caches; wherein the calculated amount of the test program is less than that of the program to be executed; setting a Cache mapping relation of the RISC processor according to the Cache mapping relation with the highest hit rate; and executing the program to be executed by adopting the RISC processor. Through hit rate testing, the RISC processor is set to the Cache mapping relation with the highest hit rate, so that the hit rate is improved, and the system performance is improved. The present application also discloses a program execution device of a RISC processor, a computing device and a computer readable storage medium having the above advantageous effects.
Description
Technical Field
The present application relates to the field of computing technologies, and in particular, to a program execution method, a program execution apparatus, a computing device, and a computer-readable storage medium for a RISC processor.
Background
With the continuous development of electronic science and technology, Reduced Instruction Set computers (RISC-V) chips are increasingly applied to mobile platforms and embedded fields, as opposed to Advanced RISC Machines (Advanced Reduced Instruction Set processors). RISC-V is an open instruction set architecture established based on the reduced instruction set computing principle. The RISC-V processor is applied in a plurality of specific fields, under a plurality of scenes, the RISC-V processor is taken as the processor and is specially used for processing one or a plurality of specific applications, such as matrix calculation (the matrix calculation is used in a plurality of fields), video monitoring and other specific scenes, and the RISC-V processor has the characteristics that the programs run on the RISC-V processor are relatively exclusive and have similar characteristics.
In the related technology, when the RISC-V processor processes data, the RISC-V processor searches the Cache first, if the data is temporarily stored in the Cache because of the previous operation, the data does not need to be read from the main memory any more — when the Cache has data required by a Central Processing Unit (CPU), the CPU fetches the data from the Cache, only a few clock cycles are needed, and when the Cache has no data required by the CPU, the data can only be read from the memory, and the time is usually dozens of even hundreds of clock cycles, which greatly hinders the system performance. However, the mapping relationship between the Cache and the memory in the RISC-V processor is fixed, which results in a reduced hit rate of the processor Cache in different application scenarios, and a reduced performance of the system.
Therefore, how to increase the hit rate of the RISC-V processor Cache is a major concern to those skilled in the art.
Disclosure of Invention
The application aims to provide a program execution method, a program execution device, a computing device and a computer readable storage medium of a RISC processor, the RISC processor is set to be a Cache mapping relation with the highest hit rate through hit rate testing, the hit rate is improved, and the system performance is improved.
To solve the above technical problem, the present application provides a program execution method for a RISC processor, comprising:
adopting a test program of the same kind as the program framework of the program to be executed to carry out hit rate test on the mapping relations of the plurality of caches so as to obtain the hit rate corresponding to each mapping relation of the caches; wherein the calculated amount of the test program is less than that of the program to be executed;
setting a Cache mapping relation of the RISC processor according to the Cache mapping relation with the highest hit rate;
and executing the program to be executed by adopting the RISC processor.
Optionally, performing hit rate test on the multiple Cache mapping relationships by using a test program corresponding to the program architecture of the program to be executed to obtain a hit rate corresponding to each Cache mapping relationship, where the hit rate test includes:
determining a current Cache mapping relation from the plurality of Cache mapping relations according to a preset sequence;
setting a Cache mapping relation of the RISC processor according to the current Cache mapping relation;
and executing the test program by adopting the RISC processor, and counting to obtain the hit rate.
Optionally, setting a Cache mapping relationship of the RISC processor according to the Cache mapping relationship with the highest hit rate, including:
setting a virtual address data searching mode of the RISC processor according to the Cache mapping relation with the highest hit rate;
and setting the memory data transfer mode of the RISC processor according to the Cache mapping relation with the highest hit rate.
Optionally, setting a Cache mapping relationship of the RISC processor according to the Cache mapping relationship with the highest hit rate, including:
and setting the Cache mapping relation by adopting a Cache controller corresponding to the RISC processor according to the Cache mapping relation with the highest hit rate.
Optionally, the matrix calculation size of the program to be executed is the same as the matrix calculation size of the test program (the program is not necessarily the matrix operation, and needs to be modified, and the matrix operation in the cross-bottom book is only an example).
Optionally, setting a Cache mapping relationship of the RISC processor according to the Cache mapping relationship with the highest hit rate, including:
and setting the number of blocks of the set associative mapping of the Cache mapping relation of the RISC processor according to the Cache mapping relation with the highest hit rate.
Optionally, the multiple Cache mapping relationships include direct mapping, fully associative mapping, and set associative mapping.
An embodiment of the present application further provides a program execution device for a RISC processor, including:
the mapping relation testing module is used for testing the hit rate of the mapping relations of the caches by adopting a testing program which is the same as the program framework of the program to be executed to obtain the hit rate corresponding to each mapping relation of the caches; wherein the calculated amount of the test program is less than that of the program to be executed;
the mapping relation adjusting module is used for setting the Cache mapping relation of the RISC processor according to the Cache mapping relation with the highest hit rate;
and the program execution module is used for executing the program to be executed by adopting the RISC processor.
An embodiment of the present application further provides a computing device, including:
a memory for storing a computer program;
a processor for implementing the steps of the program execution method as described above when executing the computer program.
Embodiments of the present application also provide a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the program execution method described above.
The present application provides a program execution method for a RISC processor, comprising: adopting a test program of the same kind as the program framework of the program to be executed to carry out hit rate test on the mapping relations of the plurality of caches so as to obtain the hit rate corresponding to each mapping relation of the caches; wherein the calculated amount of the test program is less than that of the program to be executed; setting a Cache mapping relation of the RISC processor according to the Cache mapping relation with the highest hit rate; and executing the program to be executed by adopting the RISC processor.
The method comprises the steps of performing hit rate test on Cache mapping relations through a test program corresponding to a program framework of a program to be executed to obtain hit rates under different Cache mapping relations, determining the hit rates of the program to be executed under different Cache mapping relations because the test program is similar to the program framework of the program to be executed, further setting the Cache mapping relations to be the highest hit rates, and finally executing the program to be executed to improve the hit rates in the executing process and improve the running performance of a system.
The present application further provides a program execution device of a RISC processor, a computing device and a computer readable storage medium, which have the above advantages and are not described herein again.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a block diagram of a program execution method of a RISC processor according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating a Cache mapping relationship of a first RISC processor according to an embodiment of the present disclosure;
FIG. 3 is a diagram illustrating a Cache mapping relationship of a second RISC processor according to an embodiment of the present application;
FIG. 4 is a diagram illustrating a Cache mapping relationship of a third RISC processor according to an embodiment of the present application;
FIG. 5 is a diagram illustrating a Cache mapping relationship of a fourth RISC processor according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of a program execution device of a RISC processor according to an embodiment of the present application.
Detailed Description
The core of the application is to provide a program execution method, a program execution device, a computing device and a computer readable storage medium of a RISC processor, the RISC processor is set to be a Cache mapping relation with the highest hit rate through hit rate testing, the hit rate is improved, and the system performance is improved.
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the related technology, when the RISC-V processor processes data, the RISC-V processor firstly searches in the Cache, if the data is temporarily stored in the Cache because the previous operation is read, the data does not need to be read from the main memory, when the Cache has the data required by the CPU, the CPU takes the data from the Cache, only a few clock cycles are needed, and when the Cache does not have the data required by the CPU, the data can only be read from the memory, and the time is usually dozens of even hundreds of clock cycles, thereby greatly deteriorating the system performance. However, the mapping relationship between the Cache and the memory in the RISC-V processor is fixed, which results in a reduced hit rate of the processor Cache in different application scenarios, and a reduced performance of the system.
Therefore, the application provides a program execution method of a RISC processor, which performs hit rate test on the Cache mapping relationship through a test program corresponding to a program architecture of a program to be executed to obtain hit rates under different Cache mapping relationships, and since the test program is similar to the program architecture of the program to be executed, the hit rates of the program to be executed under different Cache mapping relationships are determined, the Cache mapping relationship is further set to be the highest, and finally the program to be executed is executed, so that the hit rate in the execution process is improved, and the operation performance of the system is improved.
The following describes a program execution method of a RISC processor according to an embodiment of the present application.
Referring to fig. 1, fig. 1 is a block diagram illustrating a program execution method of a RISC processor according to an embodiment of the present disclosure.
In this embodiment, the method may include:
s101, performing hit rate test on a plurality of Cache mapping relations by adopting a test program of the same type as the program architecture of the program to be executed to obtain a hit rate corresponding to each Cache mapping relation; the calculation amount of the test program is less than that of the program to be executed;
therefore, the step aims to adopt the test program to carry out hit rate test on the mapping relations of the plurality of caches so as to determine the hit rate of the test program under different Cache mapping relations. Since the program structure of the test program and the program structure of the program to be executed are the same, that is, the program structures of the test program and the program structure of the program to be executed are the same, that is, the data processing modes of the test program and the program structure of the program to be executed are similar. Therefore, in this step, it is equivalent to perform hit rate test on the program to be executed in multiple Cache mapping relationships. And finally, obtaining the hit rate of the test program corresponding to each Cache mapping relation, which is equivalent to the hit rate of the program to be executed corresponding to each Cache mapping relation.
The method mainly aims to reduce the calculation amount of the test program in the execution process and improve the test speed. Therefore, the test program employed has the calculation characteristic of the program to be tested, and the calculation amount is smaller than the program to be tested. Therefore, the testing speed is improved on the premise of keeping the accuracy of the testing result.
The program structure of the test program and the program structure of the program to be executed are the same, that is, the calculation process of reading data and data is the same. The method is mainly used for keeping the same hit rate of the test program and the program to be executed under different Cache mapping relations.
In this step, a test program of the same kind as the program framework of the program to be executed is used to perform hit rate test on the multiple Cache mapping relationships, so as to obtain a process of the hit rate corresponding to each Cache mapping relationship, which may be a process of performing a circular test operation on the multiple Cache mapping relationships. For example, the Cache mapping relationship a is set as the current mapping relationship, the test program is executed to obtain the corresponding hit rate, the next Cache mapping relationship B is set as the current mapping relationship, the test program is executed to obtain the corresponding hit rate, and when all the Cache mapping relationships are tested, the hit rate corresponding to each Cache mapping relationship is obtained.
In order to improve the efficiency of testing each Cache mapping relationship, the process of testing each Cache mapping relationship may include:
step 1, determining a current Cache mapping relation from a plurality of Cache mapping relations according to a preset sequence;
step 2, setting a Cache mapping relation of the RISC processor according to the current Cache mapping relation;
and 3, executing the test program by adopting a RISC processor, and counting to obtain the hit rate.
It can be seen that the test process is mainly for performing hit rate test on each Cache mapping relationship. Because the testing program which is the same as the program to be tested is adopted for testing, the hit rate of the program to be executed under each Cache mapping relation can be obtained through the embodiment, so that the most suitable Cache mapping relation of the program to be executed can be determined.
In addition, when the program to be executed is a program related to matrix calculation, the matrix calculation size of the program to be executed is the same as that of the test program, and the program architecture similarity between the program to be executed and the test program is maintained.
S102, setting a Cache mapping relation of the RISC processor according to the Cache mapping relation with the highest hit rate;
on the basis of S101, this step is intended to set the Cache mapping relationship of the RISC processor according to the Cache mapping relationship with the highest hit rate, that is, the Cache mapping relationship with the highest hit rate is used as the Cache mapping relationship implemented in this embodiment.
The setting of the Cache mapping relationship mainly comprises two aspects, namely setting of a data searching mode and setting of a mode of moving memory data to the Cache. Specifically, one aspect is to set for a data lookup with a virtual address issued by the CPU. On the other hand, data of the corresponding address is moved from the memory. Therefore, when the mapping relation of the Cache is changed, the mode of the data searching process and the mode of data moving are modified.
In order to implement more appropriate setting operation on the mapping relationship of the Cache, the step may include:
step 1, setting a virtual address data searching mode of a RISC processor according to a Cache mapping relation with the highest hit rate;
and step 2, setting the memory data transfer mode of the RISC processor according to the Cache mapping relation with the highest hit rate.
Therefore, in the alternative scheme, how to set the Cache mapping relationship is mainly explained.
Furthermore, in some application scenarios, the RISC processor has no way to set the Cache mapping relationship, so that the Cache mapping relationship can be set through the Cache controller. The method can comprise the following steps: and setting the Cache mapping relation by adopting a Cache controller corresponding to the RISC processor according to the Cache mapping relation with the highest hit rate.
In addition, the plurality of Cache mapping relations comprise direct mapping, fully associative mapping and set associative mapping. Therefore, the Cache mapping relationship of the RISC processor can be set among these various Cache mapping relationships. Either from the direct-mapped setting to the fully associative mapping or from the fully associative mapping setting to the set associative mapping.
The set associative mapping is divided into 2-way set associative mapping, 4-way set associative mapping, 8-way set associative mapping and 16-way set associative mapping according to the number of data blocks in the set. Therefore, when the set associative mapping of different ways needs to be set, the number of blocks in the set of Cache mapping relation may be set. The process may include:
and setting the number of blocks of the set associative mapping of the Cache mapping relation of the RISC processor according to the Cache mapping relation with the highest hit rate.
And S103, executing the program to be executed by adopting the RISC processor.
On the basis of the S102, the to-be-executed program can be executed by adopting the RISC processor with the corresponding Cache mapping relation, the to-be-executed program is kept to be executed under the optimal Cache mapping relation, and the execution efficiency of the to-be-executed program is improved.
The mode of executing the program to be executed by the RISC processor may be any one of the program execution modes provided in the prior art.
In summary, in the embodiment, the hit rate of the to-be-executed program in different Cache mapping relationships is obtained by performing hit rate test on the Cache mapping relationship through the test program corresponding to the program architecture of the to-be-executed program, and since the test program is similar to the program architecture of the to-be-executed program, the hit rate of the to-be-executed program in different Cache mapping relationships is determined, the Cache mapping relationship is further set to be the highest hit rate, and finally the to-be-executed program is executed, so that the hit rate in the execution process is improved, and the operation performance of the system is improved.
The program execution method of the RISC processor provided in the present application is further described below by a specific embodiment.
In a specific implementation process, the multiple Cache mapping relationships may include:
referring to fig. 2, fig. 2 is a schematic diagram illustrating a Cache mapping relationship of a first RISC processor according to an embodiment of the present disclosure.
Fig. 2 is a direct mapping, which has simple hardware, low cost, fast address conversion speed, and does not involve the problem of replacement algorithm (replacement algorithm, i.e. the algorithm for transferring corresponding data in the memory to the Cache when the Cache is not hit). However, the mapping relation of the Cache is low in flexibility, the storage space of the Cache cannot be fully utilized, each main memory block only has one fixed position for storage, conflict is easy to generate, the efficiency of the Cache is reduced, and therefore the Cache is only suitable for being used by high-capacity caches. For example, if a program needs to refer to the 0 th block and the 8 th block in the main memory repeatedly, it is preferable to copy the 0 th block and the 8 th block of the main memory into the Cache at the same time, but since data can only be copied into the 0 th block of the Cache, even if other storage space in the Cache is free, the two blocks are continuously and alternately loaded into the Cache, which results in a reduction in hit rate.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating a Cache mapping relationship of a second RISC processor according to an embodiment of the present application.
FIG. 3 is a fully associative mapping, that is, any block in the main memory can be mapped to any block position in the Cache. The fully associative mapping mode is flexible, each block of the main memory can be mapped into any block of the Cache, the utilization rate of the Cache is high, the block conflict probability is low, and any block of the main memory can be called as long as a certain block of the Cache is eliminated. However, because the design and implementation of the Cache comparison circuit are difficult, this approach is only suitable for small-capacity caches.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating a Cache mapping relationship of a third RISC processor according to an embodiment of the present application.
Fig. 4 is a compromise solution of actually direct mapping and fully associative mapping in group-to-group mapping, where the main memory and the Cache are both grouped, the number of blocks in one group in the main memory is the same as the number of groups in the Cache, direct mapping is used between groups, and fully associative mapping is used in a group. That is, the Cache is divided into u groups, each group of v blocks, and which group in the Cache the main memory block is stored into is fixed, but which block in the group is stored into is flexible. Further, the group link map in fig. 4 is a two-way group link map.
Referring to fig. 5, fig. 5 is a schematic diagram illustrating a Cache mapping relationship of a fourth RISC processor according to an embodiment of the present application.
FIG. 5 is a four way set associative map. The commonly used Cache with a group-associative structure has 2, 4, 8 and 16 blocks in each group, which are called 2-way, 4-way, 8-way and 16-way group-associative mapping.
The number of Cache groups in the set associative mapping determines the hit rate of the Cache to a great extent. That is to say, for the same Cache and memory, when the a program is run, because of the structural relationship of the a program, the Cache and memory slave mapping relationship shown in fig. 4 is adopted, the hit rate of the Cache is high, and the Cache hit rate is low by adopting the mapping relationship shown in fig. 5. However, when the program B is executed, the hit rate of the Cache is relatively low by using the mapping relationship between the Cache and the memory shown in fig. 4, but the hit rate of the Cache is relatively high by using the mapping relationship shown in fig. 5.
However, in the related processor architecture, the mapping relationship between the Cache and the memory is fixed, and the fixed program architecture cannot enable all programs to achieve a high hit rate. As the application of RISC-V as a special processor becomes more and more extensive, the program structure running on RISC-V is single. Therefore, in the implementation, the mapping relation between the Cache and the memory is adjusted according to the test result, so that the mapping between the Cache and the memory is in the optimal state, even if the hit rate of the Cache is the highest in the current application program, and the system performance is greatly improved.
Based on the above description of the Cache mapping relationship, this embodiment may include:
step 1, in the assembly code of the starting program, a RISC-V Core internal register X28 is appointed to be used as a special register for adjusting the mapping structure of the Cache and the memory, namely, in other assembly codes of the starting, the X28 register is not used.
The X28 register is selected because it is a temporal/temporary register in RISC-V Core, although other ones of the temporary registers may be selected.
And step 2, the CPU executes reset operation, sets the register X28 to be 1, and the assembly code executes a jump instruction and runs a test program.
The test program, i.e. the program architecture, is the same as, but simpler than, the program to be executed. For example, if the size of the matrix in the program to be executed is 10 × 10, and the loop is 100 times, then the test program may be configured to calculate the size for the matrix 10 × 10, and loop 10 times.
And step 3, when detecting that the X28 is 1, the hit rate counting module starts working, communicates with the Cache controller, and counts the hit rate of the Cache for the operation of the current test program. After the current test program runs, X28 is set to 0.
And 4, adjusting the mapping relation by the Cache controller, wherein the initial default mapping relation is that the Cache is connected by two groups, and then 4/8/16 groups are connected in sequence (respectively corresponding to the 2/3/4 th execution of the test program).
The mapping relationship is adjusted (set), and the functions are improved on the existing Cache controller. The method mainly comprises two aspects, namely, data with virtual addresses sent by a CPU is searched, and if the data is connected by two sets. And secondly, carrying out data movement from the corresponding address in the memory. By analogy, if it is the running test program 2, the query and move process is as shown in fig. 5 (corresponding to 4-way set associative mapping).
And 5, judging whether the test program is finished for 4 times, and if not, skipping to the step 2 to continue execution. If the test procedure is completed 4 times, step 6 is performed.
And 6, after the 4-time test program is completed, determining the final mapping relation between the Cache and the memory by the hit rate statistical module according to the mapping relation corresponding to the highest value of the running result of the 4-time test program, namely resetting the Cache controller.
And 7, the assembler executes the jump to the program to be executed which is really executed, and because the optimal Cache mapping relation exists at the moment, the Cache hit rate of the program to be executed which runs on the current RISC-V Core can be ensured to be the highest, and the system performance is the highest.
The embodiment can perform hit rate test on the Cache mapping relationship through the test program corresponding to the program architecture of the program to be executed to obtain hit rates under different Cache mapping relationships, and because the test program is similar to the program architecture of the program to be executed, the hit rates of the program to be executed under different Cache mapping relationships are determined, the Cache mapping relationship is further set to be the highest hit rate, and finally the program to be executed is executed, so that the hit rate in the execution process is improved, and the operation performance of the system is improved.
The program executing device of the RISC processor provided in the embodiments of the present application is introduced below, and the program executing device of the RISC processor described below and the program executing method of the RISC processor described above may be referred to correspondingly.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a program execution device of a RISC processor according to an embodiment of the present application.
In this embodiment, the apparatus may include:
the mapping relation testing module 100 is configured to perform hit rate testing on the multiple Cache mapping relations by using a testing program of the same type as a program architecture of a program to be executed, so as to obtain a hit rate corresponding to each Cache mapping relation; the calculation amount of the test program is less than that of the program to be executed;
the mapping relation adjusting module 200 is configured to set a Cache mapping relation of the RISC processor according to the Cache mapping relation with the highest hit rate;
and a program executing module 300 for executing the program to be executed by the RISC processor.
An embodiment of the present application further provides a computing device, including:
a memory for storing a computer program;
a processor for implementing the steps of the above program execution method when executing the computer program.
Embodiments of the present application further provide a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps of the above program execution method.
The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The program executing method, the program executing apparatus, the computing device and the computer readable storage medium of the RISC processor provided in the present application are described in detail above. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
Claims (10)
1. A program execution method for a RISC processor, comprising:
adopting a test program of the same kind as the program framework of the program to be executed to carry out hit rate test on the mapping relations of the plurality of caches so as to obtain the hit rate corresponding to each mapping relation of the caches; wherein the calculated amount of the test program is less than that of the program to be executed;
setting a Cache mapping relation of the RISC processor according to the Cache mapping relation with the highest hit rate;
and executing the program to be executed by adopting the RISC processor.
2. The program execution method of claim 1, wherein performing hit rate testing on the plurality of Cache mapping relationships by using a test program corresponding to a program architecture of the program to be executed to obtain a hit rate corresponding to each Cache mapping relationship, comprises:
determining a current Cache mapping relation from the plurality of Cache mapping relations according to a preset sequence;
setting a Cache mapping relation of the RISC processor according to the current Cache mapping relation;
and executing the test program by adopting the RISC processor, and counting to obtain the hit rate.
3. The program execution method of claim 1, wherein setting a Cache mapping relationship of a RISC processor according to the Cache mapping relationship with the highest hit rate comprises:
setting a virtual address data searching mode of the RISC processor according to the Cache mapping relation with the highest hit rate;
and setting the memory data transfer mode of the RISC processor according to the Cache mapping relation with the highest hit rate.
4. The program execution method of claim 1, wherein setting a Cache mapping relationship of a RISC processor according to the Cache mapping relationship with the highest hit rate comprises:
and setting the Cache mapping relation by adopting a Cache controller corresponding to the RISC processor according to the Cache mapping relation with the highest hit rate.
5. The program execution method of claim 1, wherein the matrix calculation size of the program to be executed is the same as the matrix calculation size of the test program.
6. The program execution method of claim 1, wherein setting a Cache mapping relationship of a RISC processor according to the Cache mapping relationship with the highest hit rate comprises:
and setting the number of blocks of the set associative mapping of the Cache mapping relation of the RISC processor according to the Cache mapping relation with the highest hit rate.
7. The program execution method of claim 1, wherein the plurality of Cache mappings comprises direct mappings, fully associative mappings, and set associative mappings.
8. A program executing apparatus of a RISC processor, comprising:
the mapping relation testing module is used for testing the hit rate of the mapping relations of the caches by adopting a testing program which is the same as the program framework of the program to be executed to obtain the hit rate corresponding to each mapping relation of the caches; wherein the calculated amount of the test program is less than that of the program to be executed;
the mapping relation adjusting module is used for setting the Cache mapping relation of the RISC processor according to the Cache mapping relation with the highest hit rate;
and the program execution module is used for executing the program to be executed by adopting the RISC processor.
9. A computing device, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the program execution method of any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, which computer program, when being executed by a processor, realizes the steps of the program execution method according to any one of claims 1 to 7.
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