CN112995337B - High-performance processor chip-based high-performance Internet of things hardware platform and method - Google Patents
High-performance processor chip-based high-performance Internet of things hardware platform and method Download PDFInfo
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Abstract
The invention provides a high-performance Internet of things hardware platform and a high-performance Internet of things hardware platform method based on a high-performance processor chip. The scheme comprises a C3000 processor chip, a peripheral interface, a COM debugging interface, a LAN Controller interface, a 88E6193 bridge chip, a first optical fiber interface, a second optical fiber interface, a first network port, a second network port, a third network port, a fourth network port, a first forwarding chip and a second forwarding chip; the external interface of the C3000 processor chip includes the peripheral interface, the COM debug interface, and the LAN Controller interface, the LAN Controller interface is electrically connected to the 88E6193 bridge, and the 88E6193 bridge is electrically connected to the first optical fiber interface, the second optical fiber interface, the first network port, the second network port, the third network port, the fourth network port, the first forwarding chip, and the second forwarding chip. According to the scheme, the interface expansion is carried out on the C3000 processor, and data compression is carried out on transmission data with low importance and large data flow, so that efficient data transmission of the Internet of things is realized.
Description
Technical Field
The invention relates to the technical field of electronic circuit products, in particular to a high-performance Internet of things hardware platform and a high-performance Internet of things hardware platform method based on a high-performance processor chip.
Background
The internet of things is that any object is connected with a network through information sensing equipment according to an agreed protocol, and the object performs information exchange and communication through an information transmission medium so as to realize functions of intelligent identification, positioning, tracking, supervision and the like.
With the continuous development of the internet of things technology, the requirements for the transmission speed and the number of transmission interfaces are also increasing. However, before the technology of the invention, the existing technology carries out data transmission of the internet of things through the C3000 processor, only the peripheral interface of the C3000 processor is relied on in the transmission process, and independent data interface expansion is not carried out, so that the situations of few transmission interfaces and insufficient transmission speed often occur in use.
Disclosure of Invention
In view of the above problems, the invention provides a high-performance internet of things hardware platform and a high-performance internet of things hardware method based on a high-performance processor chip, which realize efficient internet of things data transmission by performing data interface expansion on a C3000 processor and performing data compression on transmission data with low importance and large data flow on the basis.
According to a first aspect of the embodiments of the present invention, a high performance internet of things hardware platform based on a high performance processor chip is provided.
In one or more embodiments, preferably, the high-performance internet of things hardware platform based on the high-performance processor chip includes a C3000 processor chip, a peripheral interface, a COM debug interface, a LAN Controller interface, an 88E6193 bridge chip, a first optical fiber interface, a second optical fiber interface, a first network interface, a second network interface, a third network interface, a fourth network interface, a first forwarding chip, and a second forwarding chip; the external interface of the C3000 processor chip includes the peripheral interface, the COM debug interface, and the LAN Controller interface, the LAN Controller interface is electrically connected to the 88E6193 bridge, and the 88E6193 bridge is electrically connected to the first optical fiber interface, the second optical fiber interface, the first network port, the second network port, the third network port, the fourth network port, the first forwarding chip, and the second forwarding chip.
In one or more embodiments, preferably, the first optical fiber interface and the second optical fiber interface all use SFP + tera optical communication interfaces;
the first forwarding chip is connected with 2 gigabit Ethernet communication interfaces;
the second forwarding chip is connected with 2 gigabit Ethernet communication interfaces.
In one or more embodiments, preferably, the peripheral interfaces include 1 UDIMM memory slot supporting DDR4, 1 embedded memory of 8GB, 2 tera optical communication interfaces, 1 USB2.0, and 6 SATA interfaces.
In one or more embodiments, preferably, the first port, the second port, the third port, and the fourth port are respectively connected to RJ45 interface gigabit ports.
According to a second aspect of the embodiments of the present invention, a working method of a high-performance internet-of-things hardware platform based on a high-performance processor chip is provided.
In one or more embodiments, preferably, the operating method of the high-performance internet of things hardware platform based on the high-performance processor chip includes:
acquiring Internet of things data by using the C3000 processor chip to generate first data, second data and third data;
acquiring a data transmission rate, a data output interface and a data checksum stored in the third data, performing verification according to the third data, and generating a verification passing command;
analyzing the importance degree and the data type according to the data flow threshold value and the importance degree threshold value stored in the C3000 processor chip to generate a compression command or a non-compression command;
generating target dimension compressed data according to the compression command and the inspection passing command;
and sending the target dimension compressed data through a data output interface after acquiring the target dimension compressed data, wherein the data output interface comprises one or more of a tera optical communication interface, a gigabit Ethernet communication interface, a USB2.0 interface and a SATA interface.
In one or more embodiments, preferably, the obtaining internet of things data by using the C3000 processor chip to generate first data, second data, and third data specifically includes:
acquiring the data of the Internet of things by using the C3000 processor chip, wherein the data of the Internet of things comprises a data frame head, transmission data of the Internet of things and a data frame tail;
extracting the data frame head in the data of the Internet of things, and storing the data frame head as the first data;
extracting the transmission data of the internet of things in the data of the internet of things, and storing the transmission data of the internet of things as the second data;
and extracting the data frame tail in the data of the Internet of things, and storing the data frame tail as third data.
In one or more embodiments, preferably, the obtaining a data transmission rate, a data output interface, and a data checksum stored in the third data, performing a checksum verification according to the third data, and generating a verification pass command specifically includes:
acquiring the data transmission rate, the data output interface and the data checksum stored in the third data;
acquiring the third data, summing the information in the third data, and storing as checksum inspection data;
and outputting the checking pass command when the checking sum checking data is judged to be the same as the data checking sum.
In one or more embodiments, preferably, the analyzing the importance degree and the data type according to the data flow threshold and the importance degree threshold stored in the C3000 processor chip, and generating the compression command or the non-compression command specifically includes:
acquiring the data flow threshold and the importance threshold stored in the C3000 processor chip;
acquiring the data type and the data importance degree stored in the first data;
when the data type is judged to be one of an image and a video, the importance degree of the data is read;
when the data type is judged to be other types except for images and videos, the non-compression command is sent out;
when the importance degree of the data is judged to be smaller than the importance degree threshold value, the compression command is sent out;
and sending the non-compression command when the importance degree of the data is judged to be more than or equal to the importance degree threshold value.
In one or more embodiments, preferably, the generating the target dimension compressed data according to the compression command and the check pass command specifically includes:
when the uncompressed command and the check pass command are received, sending the second data directly to the data output interface;
when the compression command and the inspection passing command are received, and the data transmission rate is judged to be larger than the data flow threshold value, calculating the data dimension of the second data;
calculating a compression dimension of the second data by using a first calculation formula;
taking the nearest integer of the compression dimensionality as a target compression dimensionality;
compressing the second data into the target dimension compressed data;
the first calculation formula is:
D=m*Lim/Speed
wherein,Dis a dimension of compression of the second data,mis the data dimension of the second data,Limin order to be the data traffic threshold value,Speedis the data transmission rate.
In one or more embodiments, preferably, the compressing the second data into the target dimension compressed data specifically includes:
acquiring the second data and storing as input datax 1 x 2 …x m] ；
Obtaining the target compression dimension as a data fidelity thresholdγ；
Calculating a characteristic value of the input data by a second calculation formulaλ i ；
Sorting the characteristic phasors according to the size of the characteristic value of the input data, and determining a transformation matrix in the form of a third calculation formula, wherein the sorting relation of the size of the characteristic value isλ 1 >λ 2 >λ 3 …λ m ；
Compressing the input data according to a fourth calculation formulax 1 x 2 …x m]Outputting the target dimension compressed data;
the second calculation formula is:
X T X=[x 1 x 2 …x m] T [x 1 x 2 …x m]
wherein,mis the data dimension of the second data,Xis a matrix of the input datax 1 x 2 …x m]，x 1 x 2 …x mSampling data vectors from 1 st to m th of the monitoring indexes respectively;
the third calculation formula is:
P=[e 1 e 2 ···e D ]
wherein,Pfor the purpose of the transformation matrix,Dis a dimension of compression of the second data,λ i is arranged in descending order asiThe eigenvalues of the matrix of (a),e i as a characteristic valueλ i A corresponding feature vector;
the fourth calculation formula is:
Y=PX=[e 1 e 2 ···e D ] T X
wherein,Ycompressing data [ y ] for the target dimension1 y2 …y D]，DIs a dimension of compression of the second data,y i a first step of compressing data for the compressed target dimensioniThe number of the data is one,Xis a matrix of the input datax 1 x 2 …x m]，mIs the data dimension of the second data,e i as a characteristic valueλ i The corresponding feature vector is used as a basis for determining the feature vector,Pis the transformation matrix.
The technical scheme provided by the embodiment of the invention can have the following beneficial effects:
1) through LAN Controller interface connection 88E6193 bridge piece, promoted the peripheral hardware data transmission ability of C3000 processor chip, promoted the quantity of the optical communication interface and the network communication interface of peripheral hardware, made the application scene increase, more be fit for multiclass data transmission condition.
2) By obtaining all the data of the Internet of things and carrying out data compression according to the importance degree of the data and the reduction of the data flow, the data transmission efficiency of the Internet of things is improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a structural diagram of a high-performance internet of things hardware platform based on a high-performance processor chip according to an embodiment of the present invention.
Fig. 2 is a schematic hardware structure diagram of a high-performance internet of things hardware platform based on a high-performance processor chip according to an embodiment of the present invention.
Fig. 3 is a flowchart of an operating method of a high-performance internet of things hardware platform based on a high-performance processor chip according to an embodiment of the present invention.
Fig. 4 is a flowchart of acquiring internet-of-things data by using the C3000 processor chip to generate first data, second data, and third data in the working method of the high-performance internet-of-things hardware platform based on the high-performance processor chip according to an embodiment of the present invention.
Fig. 5 is a flowchart of acquiring a data transmission rate, a data output interface, and a data checksum stored in the third data, performing verification according to the third data, and generating a verification passing command in the operating method of the high-performance internet of things hardware platform based on the high-performance processor chip according to an embodiment of the present invention.
Fig. 6 is a flowchart of generating a compression command or an uncompression command according to an importance degree and a data type analysis based on a data traffic threshold and an importance degree threshold stored in the C3000 processor chip in a working method of a high-performance internet of things hardware platform based on a high-performance processor chip according to an embodiment of the present invention.
Fig. 7 is a flowchart of generating target dimension compressed data according to the compression command and the verification pass command in the operating method of the high-performance internet of things hardware platform based on the high-performance processor chip according to an embodiment of the present invention.
Fig. 8 is a flowchart of compressing second data into target dimension compressed data in the working method of the high-performance internet of things hardware platform based on the high-performance processor chip according to an embodiment of the present invention.
Detailed Description
In some of the flows described in the present specification and claims and in the above figures, a number of operations are included that occur in a particular order, but it should be clearly understood that these operations may be performed out of order or in parallel as they occur herein, with the order of the operations being indicated as 101, 102, etc. merely to distinguish between the various operations, and the order of the operations by themselves does not represent any order of performance. Additionally, the flows may include more or fewer operations, and the operations may be performed sequentially or in parallel. It should be noted that, the descriptions of "first", "second", etc. in this document are used for distinguishing different messages, devices, modules, etc., and do not represent a sequential order, nor limit the types of "first" and "second" to be different.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The internet of things is that any object is connected with a network through information sensing equipment according to an agreed protocol, and the object performs information exchange and communication through an information transmission medium so as to realize functions of intelligent identification, positioning, tracking, supervision and the like.
With the continuous development of the internet of things technology, the requirements for the transmission speed and the number of transmission interfaces are also increasing. However, before the technology of the invention, the existing technology carries out data transmission of the internet of things through the C3000 processor, only the peripheral interface of the C3000 processor is relied on in the transmission process, and independent data interface expansion is not carried out, so that the situations of few transmission interfaces and insufficient transmission speed often occur in use.
The embodiment of the invention provides a high-performance Internet of things hardware platform and a high-performance Internet of things hardware method based on a high-performance processor chip. According to the scheme, the data interface expansion is carried out on the C3000 processor, and on the basis, data compression is carried out on transmission data with low importance and large data flow, so that efficient data transmission of the Internet of things is realized.
According to a first aspect of the embodiments of the present invention, a high performance internet of things hardware platform based on a high performance processor chip is provided.
Fig. 1 is a structural diagram of a high-performance internet of things hardware platform based on a high-performance processor chip according to an embodiment of the present invention.
As shown in fig. 1, in one or more embodiments, preferably, the high-performance processor chip-based high-performance internet of things hardware platform includes a C3000 processor chip 101, a peripheral interface 102, a COM debug interface 103, a LAN Controller interface 104, an 88E6193 bridge chip 105, a first fiber interface 106, a second fiber interface 107, a first network port 108, a second network port 109, a third network port 110, a fourth network port 111, a first forwarding chip 112, and a second forwarding chip 113; the external interfaces of the C3000 processor chip 101 include the peripheral interface 102, the COM debug interface 103, and the LAN Controller interface 104, where the LAN Controller interface 104 is electrically connected to the 88E6193 bridge chip 105, and the 88E6193 bridge chip 105 is electrically connected to the first optical fiber interface 106, the second optical fiber interface 107, the first network port 108, the second network port 109, the third network port 110, the fourth network port 111, the first forwarding chip 112, and the second forwarding chip 113.
In the embodiment of the present invention, the first-type interface is used to directly connect with the peripheral of the C3000 processor chip, and then the LAN Controller interface is used to expand the signal, and after the expansion, the signal is respectively connected with the first network port, the second network port, the third network port, the fourth network port, the first optical fiber interface, the second optical fiber interface, the first forwarding chip, and the second forwarding chip, so that all data output is directly expanded.
Fig. 2 is a schematic hardware structure diagram of a high-performance internet of things hardware platform based on a high-performance processor chip according to an embodiment of the present invention.
As shown in fig. 2, in one or more embodiments, preferably, all of the first optical fiber interface 106 and the second optical fiber interface 107 adopt SFP + tera optical communication interfaces;
the first forwarding chip 111 is connected to an ethernet communication interface of 2 gigabytes;
the second forwarding chip 112 is connected to 2 gigabit ethernet communication interfaces.
In the embodiment of the invention, two tera optical communication interfaces are directly expanded by using the optical fiber interface, so that high-speed information transmission can be directly carried out, and further, in order to expand more Ethernet communication interfaces, one interface is respectively connected with two tera Ethernet in a forwarding chip, so that the expansion of the interfaces is realized.
In one or more embodiments, preferably, the peripheral interfaces include 1 UDIMM memory slot supporting DDR4, 1 embedded memory of 8GB, 2 tera optical communication interfaces, 1 USB2.0, and 6 SATA interfaces.
In the embodiment of the invention, the original C3000 processor chip is corresponding to the maximum data transmission interface, so that the external communication interface of the original processor is not wasted, and the maximum possibility of data processing is guaranteed.
In one or more embodiments, preferably, the first port 108, the second port 109, the third port 110, and the fourth port 111 are respectively connected to RJ45 interface gigabit ports.
In the embodiment of the invention, the 88E6193 bridge piece can directly expand to obtain 4 gigabit ports by virtue of four ports of the bridge piece.
According to a second aspect of the embodiments of the present invention, a working method of a high-performance internet-of-things hardware platform based on a high-performance processor chip is provided.
Fig. 3 is a flowchart of an operating method of a high-performance internet of things hardware platform based on a high-performance processor chip according to an embodiment of the present invention.
As shown in fig. 3, in one or more embodiments, preferably, the operating method of the high-performance internet of things hardware platform based on the high-performance processor chip includes:
s301, acquiring Internet of things data by using the C3000 processor chip, and generating first data, second data and third data;
s302, acquiring a data transmission rate, a data output interface and a data checksum stored in the third data, performing verification according to the third data, and generating a verification passing command;
s303, analyzing the importance degree and the data type according to the data flow threshold value and the importance degree threshold value stored in the C3000 processor chip to generate a compression command or a non-compression command;
s304, generating target dimension compressed data according to the compression command and the check passing command;
and S305, after the target dimension compressed data is obtained, sending the data through a data output interface, wherein the data output interface comprises one or more of a tera optical communication interface, a gigabit Ethernet communication interface, a USB2.0 interface and a SATA interface.
In the embodiment of the invention, a corresponding flow threshold value is set for the C3000 processor chip, then automatic dimensionality reduction is carried out by taking the flow threshold value as a boundary, and the dimensionality reduction amplitude set by the C3000 processor chip is directly related to the threshold value. The final effect can be that the C3000 processor generates more data compression for video and image, and the transmission speed is guaranteed.
Fig. 4 is a flowchart of acquiring internet-of-things data by using the C3000 processor chip to generate first data, second data, and third data in the working method of the high-performance internet-of-things hardware platform based on the high-performance processor chip according to an embodiment of the present invention.
As shown in fig. 4, in one or more embodiments, preferably, the acquiring internet of things data by using the C3000 processor chip to generate first data, second data, and third data specifically includes:
s401, acquiring the data of the Internet of things by using the C3000 processor chip, wherein the data of the Internet of things comprises a data frame head, transmission data of the Internet of things and a data frame tail;
s402, extracting the data frame head in the data of the Internet of things, and storing the data frame head as the first data;
s403, extracting the Internet of things transmission data in the Internet of things data, and storing the Internet of things transmission data as the second data;
s404, extracting the data frame tail in the data of the Internet of things, and storing the data frame tail as third data.
In the embodiment of the invention, the obtained data of the Internet of things is stored into three types of data, wherein the first data is mainly used for monitoring subsequent data, the second data is actually transmitted data of the Internet of things, and the third data is used for verifying and transmitting rate information.
Fig. 5 is a flowchart of acquiring a data transmission rate, a data output interface, and a data checksum stored in the third data, performing verification according to the third data, and generating a verification passing command in the operating method of the high-performance internet of things hardware platform based on the high-performance processor chip according to an embodiment of the present invention.
As shown in fig. 5, in one or more embodiments, preferably, the acquiring a data transmission rate, a data output interface, and a data checksum stored in the third data, performing a checksum verification according to the third data, and generating a verification pass command specifically includes:
s501, acquiring the data transmission rate, the data output interface and the data checksum stored in the third data;
s502, acquiring the third data, summing information in the third data, and storing as checksum inspection data;
and S503, outputting the checking pass command when the check sum checking data is judged to be the same as the data check sum.
In the embodiment of the invention, the third data is used for checking the sum, so that the conditions of output disorder and the like can be avoided in the data transmission process, when the data is disordered, the data cannot be successfully checked, and the data cannot be processed.
Fig. 6 is a flowchart of generating a compression command or an uncompression command according to an importance degree and a data type analysis based on a data traffic threshold and an importance degree threshold stored in the C3000 processor chip in a working method of a high-performance internet of things hardware platform based on a high-performance processor chip according to an embodiment of the present invention.
As shown in fig. 6, in one or more embodiments, preferably, the analyzing the importance level and the data type according to the data flow threshold and the importance level threshold stored in the C3000 processor chip to generate the compression command or the non-compression command specifically includes:
s601, acquiring the data flow threshold and the importance threshold stored in the C3000 processor chip;
s602, acquiring the data type and the data importance degree stored in the first data;
s603, when the data type is judged to be one of an image and a video, reading the importance degree of the data;
s604, when the data type is judged to be other types except for images and videos, the non-compression command is sent out;
s605, sending the compression command when the importance degree of the data is judged to be smaller than the importance degree threshold value;
and S606, sending the non-compression command when the importance degree of the data is judged to be more than or equal to the importance degree threshold value.
In the embodiment of the invention, the flow margin and the importance degree are utilized to judge whether to compress, and by the method, a compression command is sent out on unimportant data, and the important data is ensured to be original data. And secondly, when the data flow threshold is not reached, the flow of the data of the internet of things sent at this time is proved to be small, and compression can be omitted. However, when the data transmission speed is high, data compression is required to ensure that the C3000 processor is not used excessively.
Fig. 7 is a flowchart of generating target dimension compressed data according to the compression command and the verification pass command in the operating method of the high-performance internet of things hardware platform based on the high-performance processor chip according to an embodiment of the present invention.
As shown in fig. 7, in one or more embodiments, preferably, the generating target dimension compressed data according to the compression command and the verification pass command specifically includes:
s701, when the non-compression command and the check passing command are received, the second data are directly sent to the data output interface;
s702, when the compression command and the inspection passing command are received, and the data transmission rate is judged to be larger than the data flow threshold value, calculating the data dimension of the second data;
s703, calculating the compression dimension of the second data by using a first calculation formula;
s704, taking the integer with the nearest compression dimension as a target compression dimension;
s705, compressing the second data into the target dimension compressed data;
the first calculation formula is:
D=m*Lim/Speed
wherein,Dis a dimension of compression of the second data,mis the data dimension of the second data,Limin order to be the data traffic threshold value,Speedis the data transmission rate.
In the embodiment of the invention, when the non-compression command and the check pass command are received, the output is directly sent out, but when the received command is compressed data, the data compression dimension is extracted according to the first calculation formula.
Fig. 8 is a flowchart of compressing second data into target dimension compressed data in the working method of the high-performance internet of things hardware platform based on the high-performance processor chip according to an embodiment of the present invention.
As shown in fig. 8, in one or more embodiments, preferably, the compressing the second data into the target dimension compressed data specifically includes:
s801, acquiring the second data and storing the second data as input data [ 2 ]x 1 x 2 …x m] ；
S802, obtaining the target compression dimension as a data fidelity threshold valueγ；
S803, calculating the characteristic value of the input data through a second calculation formulaλ i ；
S804, sorting the characteristic phasors according to the size of the characteristic value of the input data, and determining a transformation matrix in the form of a third calculation formula, wherein the sorting relation of the size of the characteristic value isλ 1 >λ 2 >λ 3 …λ m ；
S805, compressing the input data [ 2 ] according to a fourth calculation formulax 1 x 2 …x m]Outputting the target dimension compressed data;
the second calculation formula is:
X T X=[x 1 x 2 …x m] T [x 1 x 2 …x m]
wherein,mis the data dimension of the second data,Xis a matrix of the input datax 1 x 2 …x m]，x 1 x 2 …x mSampling data vectors from 1 st to m th of the monitoring indexes respectively;
the third calculation formula is:
P=[e 1 e 2 ···e D ]
wherein,Pfor the purpose of the transformation matrix,Dis a dimension of compression of the second data,λ i is arranged in descending order asiThe eigenvalues of the matrix of (a),e i as a characteristic valueλ i A corresponding feature vector;
the fourth calculation formula is:
Y=PX=[e 1 e 2 ···e D ] T X
wherein,Ycompressing data [ y ] for the target dimension1 y2 …y D]，DIs a dimension of compression of the second data,y i a first step of compressing data for the compressed target dimensioniThe number of the data is one,Xis a matrix of the input datax 1 x 2 …x m]，mIs the data dimension of the second data,e i as a characteristic valueλ i The corresponding feature vector is used as a basis for determining the feature vector,Pis the transformation matrix.
The technical scheme provided by the embodiment of the invention can have the following beneficial effects:
1) through LAN Controller interface connection 88E6193 bridge piece, promoted the peripheral hardware data transmission ability of C3000 processor chip, promoted the quantity of the optical communication interface and the network communication interface of peripheral hardware, made the application scene increase, more be fit for multiclass data transmission condition.
2) By obtaining all the data of the Internet of things and carrying out data compression according to the importance degree of the data and the reduction of the data flow, the data transmission efficiency of the Internet of things is improved.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A high-performance Internet of things hardware platform based on a high-performance processor chip is characterized by comprising a C3000 processor chip, an external interface, a COM debugging interface, a LAN Controller interface, a 88E6193 bridge chip, a first optical fiber interface, a second optical fiber interface, a first network port, a second network port, a third network port, a fourth network port, a first forwarding chip and a second forwarding chip; the external interface of the C3000 processor chip includes the peripheral interface, the COM debug interface, and the LAN Controller interface, the LAN Controller interface is electrically connected to the 88E6193 bridge, and the 88E6193 bridge is electrically connected to the first optical fiber interface, the second optical fiber interface, the first network port, the second network port, the third network port, the fourth network port, the first forwarding chip, and the second forwarding chip;
the C3000 processor chip is used for storing a data flow threshold value and an importance threshold value, analyzing importance and data types and generating a compression command or a non-compression command; and generating target dimension compressed data according to the compression command and the inspection passing command, and sending the target dimension compressed data through a data output interface after acquiring the target dimension compressed data.
2. The high-performance processor chip-based hardware platform of the internet of things as claimed in claim 1, wherein the first optical fiber interface and the second optical fiber interface are all SFP + tera optical communication interfaces;
the first forwarding chip is connected with 2 gigabit Ethernet communication interfaces;
the second forwarding chip is connected with 2 gigabit Ethernet communication interfaces.
3. The high-performance processor chip-based hardware platform of the internet of things as claimed in claim 1, wherein the peripheral interfaces include 1 UDIMM memory slot supporting DDR4, 1 embedded memory of 8GB, 2 gigabit optical communication interfaces, 1 USB2.0, and 6 SATA interfaces.
4. The high-performance processor chip-based hardware platform of the internet of things as claimed in claim 1, wherein the first port, the second port, the third port and the fourth port are respectively connected to an RJ45 interface gigabit port.
5. The working method of the high-performance internet of things hardware platform based on the high-performance processor chip is characterized by comprising the following steps of:
acquiring Internet of things data by using the C3000 processor chip to generate first data, second data and third data;
acquiring a data transmission rate, a data output interface and a data checksum stored in the third data, performing verification according to the third data, and generating a verification passing command;
analyzing the importance degree and the data type according to the data flow threshold value and the importance degree threshold value stored in the C3000 processor chip to generate a compression command or a non-compression command;
generating target dimension compressed data according to the compression command and the inspection passing command;
after the target dimension compressed data is obtained, sending the data through a data output interface, wherein the data output interface comprises one or more of a tera optical communication interface, a gigabit Ethernet communication interface, a USB2.0 interface and a SATA interface;
generating target dimension compressed data according to the compression command and the verification passing command, specifically, calculating a data dimension and a compression dimension of the second data, and directly sending the second data to the data output interface;
according to the data flow threshold value and the importance threshold value stored in the C3000 processor chip, analyzing the importance degree and the data type to generate a compression command or a non-compression command, specifically including obtaining the data type and the data importance degree stored in the first data.
6. The working method of the high-performance internet of things hardware platform based on the high-performance processor chip as claimed in claim 5, wherein the obtaining of the internet of things data by using the C3000 processor chip to generate the first data, the second data and the third data specifically comprises:
acquiring the data of the Internet of things by using the C3000 processor chip, wherein the data of the Internet of things comprises a data frame head, transmission data of the Internet of things and a data frame tail;
extracting the data frame head in the data of the Internet of things, and storing the data frame head as the first data;
extracting the transmission data of the internet of things in the data of the internet of things, and storing the transmission data of the internet of things as the second data;
and extracting the data frame tail in the data of the Internet of things, and storing the data frame tail as third data.
7. The operating method of the high-performance processor chip-based hardware platform of internet of things as claimed in claim 5, wherein the obtaining of the data transmission rate, the data output interface, and the data checksum stored in the third data, performing the verification and generating the verification pass command according to the third data specifically comprises:
acquiring the data transmission rate, the data output interface and the data checksum stored in the third data;
acquiring the third data, summing the information in the third data, and storing as checksum inspection data;
and outputting the checking pass command when the checking sum checking data is judged to be the same as the data checking sum.
8. The operating method of the high-performance internet of things hardware platform based on the high-performance processor chip as claimed in claim 5, wherein the analyzing the importance degree and the data type according to the data traffic threshold and the importance degree threshold stored in the C3000 processor chip, and generating the compression command or the non-compression command specifically includes:
acquiring the data flow threshold and the importance threshold stored in the C3000 processor chip;
acquiring the data type and the data importance degree stored in the first data;
when the data type is judged to be one of an image and a video, the importance degree of the data is read;
when the data type is judged to be other types except for images and videos, the non-compression command is sent out;
when the importance degree of the data is judged to be smaller than the importance degree threshold value, the compression command is sent out;
and sending the non-compression command when the importance degree of the data is judged to be more than or equal to the importance degree threshold value.
9. The operating method of the high-performance processor chip-based high-performance internet of things hardware platform according to claim 5, wherein the generating of the target dimension compressed data according to the compression command and the check pass command specifically includes:
when the uncompressed command and the check pass command are received, sending the second data directly to the data output interface;
when the compression command and the inspection passing command are received, and the data transmission rate is judged to be larger than the data flow threshold value, calculating the data dimension of the second data;
calculating a compression dimension of the second data by using a first calculation formula;
taking the nearest integer of the compression dimensionality as a target compression dimensionality;
compressing the second data into the target dimension compressed data;
the first calculation formula is:
D=m*Lim/Speed
wherein,Dis a dimension of compression of the second data,mis the data dimension of the second data,Limin order to be the data traffic threshold value,Speedis the data transmission rate.
10. The operating method of the high-performance internet of things hardware platform based on the high-performance processor chip as claimed in claim 9, wherein the compressing of the second data into target dimension compressed data specifically includes:
acquiring the second data and storing as input datax 1 x 2 …x m] ；
Obtaining the target compression dimension as a data fidelity thresholdγ；
Calculating a characteristic value of the input data by a second calculation formulaλ i ；
Sorting the characteristic phasors according to the size of the characteristic value of the input data, and determining a transformation matrix in the form of a third calculation formula, wherein the sorting relation of the size of the characteristic value isλ 1 >λ 2 >λ 3 …λ m ；
Compressing the input data according to a fourth calculation formulax 1 x 2 …x m]Outputting the target dimension compressed data;
the second calculation formula is:
X T X=[x 1 x 2 …x m] T [x 1 x 2 …x m]
wherein,mis the data dimension of the second data,Xis a matrix of the input datax 1 x 2 …x m]，x 1 x 2 …x mSampling data vectors from 1 st to m th of the monitoring indexes respectively;
the third calculation formula is:
P=[e1 e2 ···eD]
wherein,Pfor the purpose of the transformation matrix,Dis a dimension of compression of the second data,λ i is arranged in descending order asiThe eigenvalues of the matrix of (a),e i as a characteristic valueλ i A corresponding feature vector;
the fourth calculation formula is:
Y=PX=[e 1 e 2 ···e D ] T X
wherein,Ycompressing data [ y ] for the target dimension1 y2 …y D]，DIs a dimension of compression of the second data,y i a first step of compressing data for the compressed target dimensioniThe number of the data is one,Xis a matrix of the input datax 1 x 2 …x m]，mIs the data dimension of the second data,e i as a characteristic valueλ i The corresponding feature vector is used as a basis for determining the feature vector,Pis the transformation matrix.
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