CN112995067A - Coarse-grained reconfigurable data processing architecture and data processing method thereof - Google Patents
Coarse-grained reconfigurable data processing architecture and data processing method thereof Download PDFInfo
- Publication number
- CN112995067A CN112995067A CN202110537440.0A CN202110537440A CN112995067A CN 112995067 A CN112995067 A CN 112995067A CN 202110537440 A CN202110537440 A CN 202110537440A CN 112995067 A CN112995067 A CN 112995067A
- Authority
- CN
- China
- Prior art keywords
- data
- coarse
- forwarding
- grained reconfigurable
- isomorphic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
- H04L47/62—Queue scheduling characterised by scheduling criteria
- H04L47/625—Queue scheduling characterised by scheduling criteria for service slots or service orders
- H04L47/6275—Queue scheduling characterised by scheduling criteria for service slots or service orders based on priority
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/46—Interconnection of networks
- H04L12/4633—Interconnection of networks using encapsulation techniques, e.g. tunneling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3009—Header conversion, routing tables or routing tags
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Security & Cryptography (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The technical scheme adopted by the invention is as follows: a coarse-grained reconfigurable data processing architecture and a data processing method thereof comprise a coarse-grained reconfigurable computing array and a data exchange module which are connected in sequence; the coarse-grained reconfigurable computing array comprises a first preset number of isomorphic coarse-grained reconfigurable array cores, and each isomorphic coarse-grained reconfigurable array core is electrically connected with the data exchange module through an independent port; the isomorphic coarse-grained reconfigurable array core is used for receiving forwarding data, analyzing and processing the forwarding data after the forwarding data are segmented according to the headers and layer by layer, and obtaining priority information and forwarding target information of the forwarding data; the isomorphic coarse-grained reconfigurable array core sends forwarding data and the priority information to a data exchange module; and the data exchange module determines the forwarding sequence of the forwarding data according to the priority information and transmits the forwarding data to the corresponding target isomorphic coarse-grained reconfigurable array core according to the forwarding sequence.
Description
Technical Field
The invention belongs to the technical field of data processing, and particularly relates to a coarse-grained reconfigurable data processing architecture and a data processing method thereof.
Background
In the existing ship information system, the interaction of data among massive nodes enables the bandwidth requirement of the gateway to be increased in multiples, and a data processing framework used by the traditional gateway cannot be optimally designed according to the requirement, so that data delay caused by too low bandwidth is easy to occur when data are transmitted, and the real-time performance and the reliability of data transmission are low.
Disclosure of Invention
The present invention is directed to solve the above-mentioned drawbacks of the background art, and provides a coarse-grained reconfigurable data processing architecture and a data processing method thereof, so as to enhance the gateway bandwidth and improve the real-time performance and reliability of data transmission.
The technical scheme adopted by the invention is as follows: a coarse-grained reconfigurable data processing architecture, characterized by: the system comprises a coarse-grained reconfigurable computing array and a data exchange module which are connected in sequence; the coarse-grained reconfigurable computing array comprises a first preset number of isomorphic coarse-grained reconfigurable array cores, and each isomorphic coarse-grained reconfigurable array core is electrically connected with the data exchange module through a data sending port; the isomorphic coarse-grained reconfigurable array core is used for receiving forwarding data, analyzing and processing the forwarding data after the forwarding data are segmented according to the headers and layer by layer, and obtaining priority information and forwarding target information of the forwarding data; the isomorphic coarse-grained reconfigurable array core sends forwarding data and the priority information to a data exchange module; and the data exchange module determines the forwarding sequence of the forwarding data according to the priority information and transmits the forwarding data to the corresponding target isomorphic coarse-grained reconfigurable array core according to the forwarding sequence. The coarse-grained reconfigurable data processing architecture is arranged in a chip, and each array is also connected among modules in the chip and performs information interaction through electric connection.
In the technical scheme, the isomorphic coarse-grained reconfigurable array core receives corresponding bus data and/or corresponding network protocol data as forwarding data; and the target isomorphic coarse-grained reconfigurable array core forwards the processed forwarding data to a target bus or a target network.
In the above technical solution, the isomorphic coarse-grained reconfigurable array core includes a shared register file, and a plurality of coarse-grained reconfigurable cores electrically connected to the shared register file, respectively; the shared register file is used for data transmission among the coarse-grained reconfigurable cores; each coarse-grained reconfigurable core is configured as a receiving stream processor for receiving data, or a transmitting stream processor for transmitting data, or a very-long instruction word processing unit for data parsing and packaging processing.
In the above technical solution, the received stream processor distributes each part of header data received to each corresponding coarse-grained reconfigurable core of header processing, and completes a corresponding forwarding operation according to an operation result of the coarse-grained reconfigurable core of header processing; the sending flow processor integrates the header and the message for sending; and the ultra-long instruction word processing unit analyzes and processes the divided forwarding data to obtain priority information and forwarding target information of the forwarding data.
In the above technical solution, the data exchange module includes a third preset number of arbiters;
the arbiter is connected with a data sending port of the isomorphic coarse-grained reconfigurable array core and is used for sequentially transmitting the forwarding data to the corresponding target isomorphic coarse-grained reconfigurable array core according to the priority information of each forwarding data; and the data sending port of each isomorphic coarse-grained reconfigurable array core is connected with an arbiter, the arbiter selects the highest-level data to be sent to the target isomorphic coarse-grained reconfigurable array core preferentially according to the priority information of the data requested to be forwarded, and the data of the same level are sent in sequence according to the time information.
A data processing method of a coarse-grained reconfigurable data processing architecture is characterized by comprising the following steps:
receiving forwarding data by using a current isomorphic coarse-grained reconfigurable array core, and performing layer-by-layer segmentation processing on the forwarding data according to a header;
the isomorphic coarse-grained reconfigurable array core analyzes and processes the forwarding data after the segmentation processing to obtain priority information and forwarding target information of the forwarding data;
the isomorphic coarse-grained reconfigurable array core transmits the forwarding data and the priority information to a data exchange module,
and the data exchange module determines the forwarding sequence of the forwarding data according to the priority information and transmits the forwarding data to the corresponding target isomorphic coarse-grained reconfigurable array core according to the forwarding sequence.
In the above technical solution, the method further comprises the following steps:
receiving the forwarding data by the target isomorphic coarse-grained reconfigurable array core, and generating a header of the forwarding data;
and combining the forwarding data and the header by the target isomorphic coarse-grained reconfigurable array core, generating a forwarding message and sending the forwarding message to a target bus or a target network.
The invention also provides a gateway, which is characterized by comprising a memory, a processor and the coarse-grained reconfigurable data processing architecture, wherein the memory stores a computer program, and the computer program enables the gateway to execute the data processing method of the coarse-grained reconfigurable data processing architecture when running on the processor.
The invention also provides a readable storage medium, which is characterized by storing a computer program, wherein the computer program executes the data processing method of the coarse-grained reconfigurable data processing architecture when the computer program runs on a processor.
The invention has the beneficial effects that: the coarse-grained reconfigurable data processing architecture is composed of a coarse-grained reconfigurable computing array and a data exchange module, can flexibly deal with encapsulation and analysis of various bus data and network protocols, fully utilizes task-level parallelism, thread-level parallelism, instruction-level parallelism and inherent flow characteristics of gateway data in the gateway processing process to enhance the gateway bandwidth, and improves the real-time performance and reliability of data transmission.
Drawings
Fig. 1 is a schematic structural diagram of a coarse-grained reconfigurable data processing architecture according to embodiment 1 of the present invention;
FIG. 2 is a schematic structural diagram of a homogeneous coarse-grained reconfigurable array core provided in embodiment 2 of the present invention;
fig. 3 is a schematic structural diagram of a data exchange module provided in embodiment 3 of the present invention;
fig. 4 is a flowchart of a coarse-grained reconfigurable data processing method according to embodiment 4 of the present invention;
fig. 5 is a flowchart of another coarse-grained reconfigurable data processing method according to embodiment 4 of the present invention;
fig. 6 is a schematic structural diagram of a coarse-grained reconfigurable data processing apparatus according to embodiment 5 of the present invention.
Detailed Description
The invention will be further described in detail with reference to the following drawings and specific examples, which are not intended to limit the invention, but are for clear understanding.
Fig. 1 is a schematic structural diagram of a coarse-grained reconfigurable data processing architecture according to embodiment 1 of the present invention.
The coarse-grained reconfigurable data processing architecture 100 comprises a coarse-grained reconfigurable computing array 110 and a data exchange module 120 which are connected in sequence;
the coarse-grained reconfigurable computing array 110 comprises a first preset number of isomorphic coarse-grained reconfigurable array cores 111, and each isomorphic coarse-grained reconfigurable array core 111 is connected with the data exchange module 120 through a data sending port and is used for receiving corresponding bus data and/or corresponding network protocol data to perform data analysis or encapsulation processing;
in the embodiment of the invention, in the ship information system, various buses and networks are connected in the gateway, and a large amount of gateway data are transmitted when the buses and the networks carry out information interaction, so that a plurality of task-level data, thread-level data and instruction-level data are processed in parallel in the gateway data operation process, the interactive data among the different buses and the networks can be flexibly processed through the coarse-grained reconfigurable data processing architecture 100, and various bus data and network protocols can be flexibly packaged and analyzed through a coarse-grained reconfigurable processor in the coarse-grained reconfigurable data processing architecture 100, so that the reliability of the ship information system is improved.
In the embodiment of the present invention, the Coarse-Grained Reconfigurable computing Array 110 in the Coarse-Grained Reconfigurable data processing architecture 100 is formed by tightly coupling a plurality of Homogeneous Coarse-Grained Reconfigurable Array cores 111 (HCGRA cores, Homogeneous Coarse-Grained Reconfigurable Array cores 111), and according to the bus data and network data to be processed, the Homogeneous Coarse-Grained Reconfigurable Array cores 111 can be expanded, that is, each of the different Homogeneous Coarse-Grained Reconfigurable Array cores 111 performs an analysis and encapsulation operation on one path of bus data or network protocol data according to the user requirement, so as to face the situation that buses and network protocols in a ship information system are various in variety, different in bandwidth, and different in processing method. Each isomorphic coarse-grained reconfigurable array core 111 is connected with the data exchange module 120 through an independent receiving port and an independent sending port, so that each isomorphic coarse-grained reconfigurable array core 111 is parallel, and the bandwidth and the delay performance of the gateway can be enhanced by fully utilizing task-level parallelism, thread-level parallelism, instruction-level parallelism and inherent stream characteristics of gateway data in the gateway processing process.
The data exchange module 120 is configured to transmit the data after the analysis or encapsulation processing performed by the isomorphic coarse-grained reconfigurable array core 111 to the target isomorphic coarse-grained reconfigurable array core 111 according to the priority information of the data, so that the target isomorphic coarse-grained reconfigurable array core 111 forwards the processed data to a target bus or a target network.
In the embodiment of the present invention, the data exchange module 120, that is, a Switch Fabric, is a special IP core for efficiently forwarding data, and in a ship information system, data forwarding performance has a great influence on forwarding delay and reliability of the entire gateway, the data exchange module 120 may determine priority of data during interaction between the isomorphic coarse grain reconfigurable array cores 111, and may preferentially transmit key data into the target isomorphic coarse grain reconfigurable array core 111 for processing according to priority information of the data, and data with the same priority may be sequentially transmitted into the target isomorphic coarse grain reconfigurable array core 111 for processing according to a forwarding time sequence, so as to improve real-time performance and reliability of data transmission in the coarse grain reconfigurable data processing architecture 100. Moreover, when the isomorphic coarse-grained reconfigurable array cores 111 are interconnected through the data exchange module 120 to complete data transmission, there is no conflict of data paths, so as to perform parallel data transmission.
In the embodiment of the invention, a coarse-grained reconfigurable data processing architecture consisting of a coarse-grained reconfigurable computing array and a data exchange module can flexibly deal with the encapsulation and analysis of various bus data and network protocols, and the bandwidth and the delay performance of a gateway are enhanced by fully utilizing the task-level parallelism, the thread-level parallelism, the instruction-level parallelism and the inherent flow characteristics of the gateway data in the gateway processing process, and the real-time performance and the reliability of data transmission are improved.
Fig. 2 is a schematic structural diagram of a homogeneous coarse-grained reconfigurable array core provided in embodiment 2 of the present invention.
The homogeneous coarse-grained reconfigurable array core 200 comprises a shared register file 210 and a plurality of coarse-grained reconfigurable cores 220 respectively connected with the shared register file 210;
the shared register file 210 is used for data transmission between the coarse-grained reconfigurable cores 220;
in the embodiment of the present invention, each coarse-grained reconfigurable core 220 in the isomorphic coarse-grained reconfigurable array core 200 implements inter-core data interaction (SRF, Shared Register Files, 210) through the Shared Register file 210.
Each of the coarse-grained reconfigurable cores 220 can be configured as a receive stream processor for data reception, or a transmit stream processor for data transmission, or a very long instruction word processing unit for data parsing and encapsulation processing.
In the embodiment of the present invention, the Coarse-Grained Reconfigurable Core 220 (CGR Core, Coarse-Grained Reconfigurable Core) supports dynamic reconfiguration, so that the Coarse-Grained Reconfigurable Core 220 therein is configured as a Stream Processor (SP), and the mode is divided into a receiving Stream Processor for receiving data and a transmitting Stream Processor for transmitting data. The receiving stream processor distributes the received header data of each part to each corresponding coarse-grained reconfigurable core 220 of the header processing, and completes corresponding forwarding operation according to the operation result of the coarse-grained reconfigurable core 220 of the header processing. And the transmit stream processor may integrate the header and the message for transmission.
In the embodiment of the present invention, the coarse-grained reconfigurable core 220 except for the open-flow processor may be configured as a Very Long Instruction Word processing unit (VLIW PE) for data parsing and packaging processing, so as to fully utilize the inherent Instruction level parallelism in the header processing Process.
As a preferred embodiment, the plurality of coarse-grained reconfigurable cores 220 in the homogeneous coarse-grained reconfigurable array core 200 are configured to include a receiving stream processor, a transmitting stream processor, and a second predetermined number of very long instruction word processing units.
Fig. 3 is a schematic structural diagram of a data exchange module according to embodiment 3 of the present invention.
The data exchange module 300 comprises a third predetermined number of arbiters 310; the arbiter 310 is connected to the data sending port 320 of the isomorphic coarse-grained reconfigurable array core, and configured to sequentially transmit the forwarding data to the corresponding target isomorphic coarse-grained reconfigurable array core according to the priority information of each forwarding data.
In the embodiment of the present invention, the data sending port 320 of each homogeneous coarse-grained reconfigurable array core is connected to a corresponding arbiter 310. That is, in order to ensure the real-time transmission reliability of the key data, the data transmission port 320 of each isomorphic coarse-grained reconfigurable array core is connected with an arbiter 310, the arbiter 310 selects the highest-level data to be preferentially transmitted to the target isomorphic coarse-grained reconfigurable array core according to the priority information of the data requested to be forwarded, and the data of the same level is sequentially transmitted according to the time information.
Fig. 4 is a flowchart of a coarse-grained reconfigurable data processing method according to embodiment 4 of the present invention, where the method includes the following steps:
step S41: and receiving forwarding data by using the current isomorphic coarse-grained reconfigurable array core, and performing layer division processing on the forwarding data according to a header.
In the embodiment of the invention, the receiving stream processor in the current isomorphic coarse-grained reconfigurable array core can be used for receiving the forwarding data through the coarse-grained reconfigurable data processing architecture, and the forwarding data is segmented and processed according to the header layer by the receiving stream processor. And transmitting the segmented forwarding data to each ultra-long instruction word processing unit in the current isomorphic coarse-grained reconfigurable array core through a shared register file in the current isomorphic coarse-grained reconfigurable array core.
Step S42: and analyzing the segmented forwarding data to obtain priority information and forwarding target information of the forwarding data.
In the embodiment of the present invention, each of the very-long instruction word processing units may be controlled to perform parsing processing on the forwarding data after being segmented, so as to obtain priority information and forwarding target information of the forwarding data.
Step S43: and transmitting the forwarding data and the priority information to a data exchange module, determining a forwarding sequence of the forwarding data according to the priority information, and transmitting the forwarding data to a corresponding target isomorphic coarse-grained reconfigurable array core according to the forwarding sequence.
In the embodiment of the present invention, the forwarding data and the priority information may be transmitted to an arbiter corresponding to the forwarding target information in the data exchange module through the receive stream processor. And determining the forwarding sequence of the forwarding data according to the priority information through the arbiter, and transmitting the forwarding data to the corresponding target isomorphic coarse-grained reconfigurable array core according to the forwarding sequence.
Fig. 5 is a flowchart of another coarse-grained reconfigurable data processing method according to embodiment 4 of the present invention, where the method further includes the following steps:
step S44: and receiving the forwarding data by using a target isomorphic coarse-grained reconfigurable array core, and generating a header of the forwarding data.
In the embodiment of the invention, the forwarding data transmitted by the arbiter can be received by using a sending stream processor in the target isomorphic coarse-grained reconfigurable array core, and data receiving information is transmitted to a very-long instruction word processing unit in the target isomorphic coarse-grained reconfigurable array core.
Step S45: and combining the forwarding data and the header through the target isomorphic coarse-grained reconfigurable array core to generate a forwarding message and sending the forwarding message to a target bus or a target network.
In the embodiment of the invention, the header of the forwarding data can be generated by a very long instruction word processing unit in the target isomorphic coarse-grained reconfigurable array core according to the data receiving information. And combining the forwarding data and the header by the sending flow processor to generate a forwarding message and sending the forwarding message to a target bus or a target network.
Fig. 6 is a schematic structural diagram of a coarse-grained reconfigurable data processing apparatus according to embodiment 5 of the present invention.
The coarse-grained reconfigurable data processing apparatus 600 includes:
the data receiving module 610 is configured to receive forwarding data by using a current isomorphic coarse-grained reconfigurable array core, and perform layer-wise segmentation processing on the forwarding data according to a header;
a data analysis module 620, configured to analyze the segmented forwarding data to obtain priority information and forwarding target information of the forwarding data;
the data forwarding module 630 is configured to transmit the forwarding data and the priority information to a data exchange module, determine a forwarding order of the forwarding data according to the priority information, and transmit the forwarding data to a corresponding target isomorphic coarse-grained reconfigurable array core according to the forwarding order.
In the embodiment of the present invention, for more detailed description of functions of the modules, reference may be made to contents of corresponding parts in the foregoing embodiment, which are not described herein again.
In addition, the present invention further provides a gateway, where the gateway includes a memory, a processor, and the coarse-grained reconfigurable data processing architecture, where the memory may be used to store a computer program, and the processor executes the computer program, so as to enable the gateway to execute the functions of the above method or each module in the coarse-grained reconfigurable data processing apparatus.
The memory may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, a phonebook, etc.) created according to the use of the gateway, and the like. Further, the memory may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.
The present embodiment also provides a readable storage medium for storing a computer program used in the above gateway.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative and, for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, each functional module or unit in each embodiment of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention or a part of the technical solution that contributes to the prior art in essence can be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A coarse-grained reconfigurable data processing architecture, characterized by: the system comprises a coarse-grained reconfigurable computing array and a data exchange module which are connected in sequence; the coarse-grained reconfigurable computing array comprises a first preset number of isomorphic coarse-grained reconfigurable array cores, and each isomorphic coarse-grained reconfigurable array core is electrically connected with the data exchange module through a data sending port; the isomorphic coarse-grained reconfigurable array core is used for receiving forwarding data, analyzing and processing the forwarding data after the forwarding data are segmented according to the headers and layer by layer, and obtaining priority information and forwarding target information of the forwarding data; the isomorphic coarse-grained reconfigurable array core sends forwarding data and the priority information to a data exchange module; and the data exchange module determines the forwarding sequence of the forwarding data according to the priority information and transmits the forwarding data to the corresponding target isomorphic coarse-grained reconfigurable array core according to the forwarding sequence.
2. The coarse-grained reconfigurable data processing architecture according to claim 1, characterized in that: the isomorphic coarse-grained reconfigurable array core receives corresponding bus data and/or corresponding network protocol data as forwarding data; and the target isomorphic coarse-grained reconfigurable array core forwards the processed forwarding data to a target bus or a target network.
3. The coarse-grained reconfigurable data processing architecture according to claim 1, characterized in that: the isomorphic coarse-grained reconfigurable array core comprises a shared register file and a plurality of coarse-grained reconfigurable cores which are respectively and electrically connected with the shared register file; the shared register file is used for data transmission among the coarse-grained reconfigurable cores; each coarse-grained reconfigurable core is configured as a receiving stream processor for receiving data, or a transmitting stream processor for transmitting data, or a very-long instruction word processing unit for data parsing and packaging processing.
4. A coarse-grained reconfigurable data processing architecture according to claim 3, characterized in that: the receiving flow processor distributes the received header data of each part to each corresponding coarse-grained reconfigurable core of header processing, and completes corresponding forwarding operation according to the operation result of the coarse-grained reconfigurable core of header processing; the sending flow processor integrates the header and the message for sending; and the ultra-long instruction word processing unit analyzes and processes the divided forwarding data to obtain priority information and forwarding target information of the forwarding data.
5. The coarse-grained reconfigurable data processing architecture according to claim 1, characterized in that: the data exchange module comprises a third preset number of arbiters;
the arbiter is connected with a data sending port of the isomorphic coarse-grained reconfigurable array core and is used for sequentially transmitting the forwarding data to the corresponding target isomorphic coarse-grained reconfigurable array core according to the priority information of each forwarding data; and the data sending port of each isomorphic coarse-grained reconfigurable array core is connected with an arbiter, the arbiter selects the highest-level data to be sent to the target isomorphic coarse-grained reconfigurable array core preferentially according to the priority information of the data requested to be forwarded, and the data of the same level are sent in sequence according to the time information.
6. The data processing method of the coarse-grained reconfigurable data processing architecture according to claim 1, characterized by comprising the following steps:
receiving forwarding data by using an isomorphic coarse-grained reconfigurable array core, and performing layer-by-layer segmentation processing on the forwarding data according to a header;
the isomorphic coarse-grained reconfigurable array core analyzes and processes the forwarding data after the segmentation processing to obtain priority information and forwarding target information of the forwarding data;
the isomorphic coarse-grained reconfigurable array core transmits the forwarding data and the priority information to a data exchange module,
and the data exchange module determines the forwarding sequence of the forwarding data according to the priority information and transmits the forwarding data to the corresponding target isomorphic coarse-grained reconfigurable array core according to the forwarding sequence.
7. The data processing method of the coarse-grained reconfigurable data processing architecture according to claim 6, further comprising the steps of:
receiving the forwarding data by the target isomorphic coarse-grained reconfigurable array core, and generating a header of the forwarding data;
and combining the forwarding data and the header by the target isomorphic coarse-grained reconfigurable array core, generating a forwarding message and sending the forwarding message to a target bus or a target network.
8. A gateway comprising a memory, a processor and the coarse-grained reconfigurable data processing architecture of any one of claims 1 to 5, the memory storing a computer program which, when run on the processor, causes the gateway to perform the data processing method of the coarse-grained reconfigurable data processing architecture of claim 6 or 7.
9. A readable storage medium, characterized in that it stores a computer program which, when run on a processor, performs the data processing method of the coarse-grained reconfigurable data processing architecture according to claim 6 or 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110537440.0A CN112995067B (en) | 2021-05-18 | 2021-05-18 | Coarse-grained reconfigurable data processing architecture and data processing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110537440.0A CN112995067B (en) | 2021-05-18 | 2021-05-18 | Coarse-grained reconfigurable data processing architecture and data processing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112995067A true CN112995067A (en) | 2021-06-18 |
| CN112995067B CN112995067B (en) | 2021-09-07 |
Family
ID=76336739
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110537440.0A Active CN112995067B (en) | 2021-05-18 | 2021-05-18 | Coarse-grained reconfigurable data processing architecture and data processing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112995067B (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103984560A (en) * | 2014-05-30 | 2014-08-13 | 东南大学 | Embedded reconfigurable system based on large-scale coarseness and processing method thereof |
| CN203982379U (en) * | 2014-04-18 | 2014-12-03 | 东南大学 | For the multimode data transmission connectors of coarseness dynamic reconfigurable array |
| CN205212923U (en) * | 2015-11-02 | 2016-05-04 | 上海唐舜电信科技有限公司 | Restructural network media phone terminal |
| CN108805266A (en) * | 2018-05-21 | 2018-11-13 | 南京大学 | A kind of restructural CNN high concurrents convolution accelerator |
| CN108833299A (en) * | 2017-12-27 | 2018-11-16 | 北京时代民芯科技有限公司 | A kind of large scale network data processing method based on restructural exchange chip framework |
| CN109302357A (en) * | 2018-08-03 | 2019-02-01 | 西安交通大学 | A kind of on piece interconnection architecture towards deep learning reconfigurable processor |
| CN110494851A (en) * | 2017-03-14 | 2019-11-22 | 珠海市芯动力科技有限公司 | Restructural parallel processing |
| US20200220951A1 (en) * | 2016-07-08 | 2020-07-09 | Mentor Graphics Corporation | System for processing messages of data stream |
| CN112269757A (en) * | 2020-09-30 | 2021-01-26 | 北京清微智能科技有限公司 | Computational array in coarse-grained reconfigurable processor and reconfigurable processor |
| CN112463719A (en) * | 2020-12-04 | 2021-03-09 | 上海交通大学 | In-memory computing method realized based on coarse-grained reconfigurable array |
| CN112486907A (en) * | 2020-12-18 | 2021-03-12 | 清华大学 | Hardware implementation method for multi-layer circulation task on reconfigurable processor |
| CN112732639A (en) * | 2021-04-01 | 2021-04-30 | 南京大学 | Coarse-grained dynamic reconfigurable processor and data processing method thereof |
-
2021
- 2021-05-18 CN CN202110537440.0A patent/CN112995067B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203982379U (en) * | 2014-04-18 | 2014-12-03 | 东南大学 | For the multimode data transmission connectors of coarseness dynamic reconfigurable array |
| CN103984560A (en) * | 2014-05-30 | 2014-08-13 | 东南大学 | Embedded reconfigurable system based on large-scale coarseness and processing method thereof |
| CN205212923U (en) * | 2015-11-02 | 2016-05-04 | 上海唐舜电信科技有限公司 | Restructural network media phone terminal |
| US20200220951A1 (en) * | 2016-07-08 | 2020-07-09 | Mentor Graphics Corporation | System for processing messages of data stream |
| CN110494851A (en) * | 2017-03-14 | 2019-11-22 | 珠海市芯动力科技有限公司 | Restructural parallel processing |
| CN108833299A (en) * | 2017-12-27 | 2018-11-16 | 北京时代民芯科技有限公司 | A kind of large scale network data processing method based on restructural exchange chip framework |
| CN108805266A (en) * | 2018-05-21 | 2018-11-13 | 南京大学 | A kind of restructural CNN high concurrents convolution accelerator |
| CN109302357A (en) * | 2018-08-03 | 2019-02-01 | 西安交通大学 | A kind of on piece interconnection architecture towards deep learning reconfigurable processor |
| CN112269757A (en) * | 2020-09-30 | 2021-01-26 | 北京清微智能科技有限公司 | Computational array in coarse-grained reconfigurable processor and reconfigurable processor |
| CN112463719A (en) * | 2020-12-04 | 2021-03-09 | 上海交通大学 | In-memory computing method realized based on coarse-grained reconfigurable array |
| CN112486907A (en) * | 2020-12-18 | 2021-03-12 | 清华大学 | Hardware implementation method for multi-layer circulation task on reconfigurable processor |
| CN112732639A (en) * | 2021-04-01 | 2021-04-30 | 南京大学 | Coarse-grained dynamic reconfigurable processor and data processing method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 山蕊: "数据驱动可重构阵列处理器体系结构研究", 《中国博士学位论文全文数据库 信息科技辑》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112995067B (en) | 2021-09-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103023693B (en) | A kind of user behaviors log data management system and method | |
| CN110297944B (en) | Distributed XML data processing method and system | |
| CN110741573A (en) | Method and system for selectively propagating transactions using network coding in a blockchain network | |
| CN109525803B (en) | Video structuring processing device and method based on FPGA and artificial intelligence | |
| CN105094981B (en) | A kind of method and device of data processing | |
| CN109213828B (en) | Block generation method, device, equipment and storage medium | |
| CN108011850B (en) | Data packet reassembly method and apparatus, computer device, and readable medium | |
| CN110532294A (en) | Ticket merging method, device, equipment and computer readable storage medium | |
| CN110708363A (en) | File transmission method, system, electronic equipment and storage medium | |
| CN109993286B (en) | Sparse neural network computing method and related product | |
| CN112995067B (en) | Coarse-grained reconfigurable data processing architecture and data processing method thereof | |
| CN107870921B (en) | Log data processing method and device | |
| US9715477B2 (en) | Shared-bandwidth multiple target remote copy | |
| CN109246331A (en) | A kind of method for processing video frequency and system | |
| US7424653B2 (en) | System and method for error capture and logging in computer systems | |
| US20040236982A1 (en) | System and method for in-order queue draining | |
| CN105912477B (en) | A kind of method, apparatus and system that catalogue is read | |
| JP5410301B2 (en) | Distributed processing system, distributed processing method, and program | |
| CN109241362B (en) | Block generation method, device, equipment and storage medium | |
| CN114579054A (en) | Data processing method and device, electronic equipment and computer readable medium | |
| CN114490458A (en) | Data transmission method, chip, server and storage medium | |
| CN109918325B (en) | Interface conversion bridge based on Avalon bus, interface conversion method and system | |
| CN115904488A (en) | Data transmission method, system, device and equipment | |
| CN113992493A (en) | Video processing method, system, device and storage medium | |
| CN112615773A (en) | Message processing method and system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |