CN112994498A - Seven-level inverter circuit, inverter and control method - Google Patents
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
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- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/12—Arrangements for reducing harmonics from ac input or output
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Abstract
The present disclosure provides a seven-level inverter circuit, an inverter and a control method, wherein the seven-level inverter circuit includes: the T-type three-level inverter outputs three levels and is cascaded with the H-bridge circuit to realize that each phase outputs seven levels; the three phases of the T-type three-level inverter share two direct-current side capacitors, and each phase is provided with a suspension capacitor. According to the technical scheme, only the zero common-mode voltage vector is selected as the candidate vector, so that the common-mode voltage of the inverter is well reduced.
Description
Technical Field
The disclosure belongs to the technical field of inverter control, and particularly relates to a seven-level inverter circuit, an inverter and a control method.
Background
The statements in this section merely provide background information related to the present disclosure and may not necessarily constitute prior art.
At present, the power generation of renewable energy sources such as wind energy, solar energy and the like is rapidly developed due to the increasing shortage of energy sources and serious environmental pollution. The grid-connected inverter is used as an interface between a renewable energy system and a power grid, and the performance of the grid-connected inverter directly influences the quality of electric energy output by a power generation system.
Multi-level inverters have been widely used industrially in recent years due to their particular advantages as compared to low-level inverters. The advantages of the multilevel inverter mainly include: the improved output waveform has better quality, can reduce electromagnetic interference, can use fewer filters to reduce the volume of equipment and the like. However, in the current research, the multi-level inverter also brings some problems, such as difficulty in controlling the balance of the capacitor voltage, unstable neutral point voltage, complex inverter system, and the like.
Disclosure of Invention
In order to overcome the defects of the prior art, the present disclosure provides a seven-level inverter circuit, which can balance the voltage of a neutral point and the voltage of a floating capacitor and reduce the common-mode voltage.
In order to achieve the above object, one or more embodiments of the present disclosure provide the following technical solutions:
in a first aspect, a seven-level inverter circuit is disclosed, comprising: the T-type three-level inverter outputs three levels and is cascaded with the H-bridge circuit to realize that each phase outputs seven levels; the three phases of the T-type three-level inverter share two direct-current side capacitors, and each phase H bridge is provided with a suspension capacitor;
the upper capacitor voltage and the lower capacitor voltage of the direct-current side voltage of the T-type three-level inverter are equal to each other, so that neutral point voltage balance is achieved.
According to the further technical scheme, the T-type three-level inverter comprises two capacitors on a direct current side, four switching tubes are arranged on each phase of bridge arm, the voltage on the direct current side is Udc (4E), and three voltage levels of-Udc/2, 0 and Udc/2 can be output by each phase by adjusting the on-off of the switching tubes. The T-type three-level inverter has smaller conduction loss, not only has the common advantages of the three-level inverter, but also solves the problem of unbalanced heat distribution of the power device of the traditional three-level inverter.
According to the technical scheme, the H-bridge circuit comprises three branches connected in parallel, the first branch and the second branch are two switching tubes connected in series, and the third branch is a suspension capacitor. By controlling the voltage of the floating capacitor to be E, two voltage levels of-E and E can be output by the H-bridge circuit.
In a second aspect, a control method for a seven-level inverter circuit is disclosed, which includes:
the three-phase sampling current is subjected to Clark conversion to obtain a current under a two-phase static coordinate system;
the three-phase network side sampling voltage is subjected to coordinate transformation to obtain a voltage value under a two-phase static coordinate system;
obtaining current at the next moment by a Lagrange extrapolation method, calculating a reference voltage value at the next moment by discretized model predictive control, and calculating two minimum voltage vectors serving as candidate vectors by a cost function;
and selecting a specific switch state according to the requirements of the neutral point potential balance and the suspension capacitor voltage balance (the neutral point potential should be kept at 0, namely the difference between the upper capacitor voltage and the lower capacitor voltage at the direct current side is 0, and the suspension voltage capacitor voltage should be controlled at E), and finally applying the specific switch state to each switch to output seven levels.
The method disclosed by the invention takes the zero common mode voltage as a voltage candidate vector, synthesizes a reference voltage vector by using two voltage vectors, and calculates two voltage vectors with the minimum value function in the zero common mode voltage vector by using a model prediction method; the floating capacitor voltage is controlled to be able to output seven levels.
According to the further technical scheme, in the control of neutral point voltage balance and suspension capacitor voltage balance, the suspension capacitor voltage balance priority is higher than that of the neutral point voltage balance.
According to the further technical scheme, a direct-current side power supply is Udc (4E), the specific value is 600V, the T-type three-level inverter can output three levels of-2E, 0 and 2E, and the three levels are matched with an H bridge circuit to realize that each phase outputs seven levels, specifically: -3E, -2E, -E, 0, E, 2E, 3E.
According to the further technical scheme, when the output levels are-E and E, the corresponding switch states are respectively used for controlling the voltage of the floating capacitor.
In a further embodiment, the cost function is expressed as
g＝|Vα(k+1)-Vα|2+|Vβ(k+1)-Vβ|2
In a third aspect, a seven-level inverter is disclosed, which comprises seven-level inverter circuits, wherein a plurality of seven-level inverter circuits are connected in parallel on the side of a common direct current bus.
In a fourth aspect, a frequency converter is disclosed, comprising: the input end of the rectifying circuit is connected with a power grid, the output end of the rectifying circuit is connected with a common direct current bus, and the seven-level inverter circuits are connected in parallel on the common direct current bus.
The above one or more technical solutions have the following beneficial effects:
according to the technical scheme, only the zero common-mode voltage vector is selected as the candidate vector, so that the common-mode voltage of the inverter is well reduced.
The technical scheme effectively controls the neutral point potential balance and prevents the problems of unbalanced output level, waveform distortion and the like.
According to the technical scheme, the T-type three-level inverter and the H-bridge circuit are cascaded, and high-level output is achieved through fewer switches.
The technical scheme is simple to implement, strong in expansibility of a cascade system, simple to apply and strong in practicability.
Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure and are not to limit the disclosure.
FIG. 1 is a diagram of a cascaded seven-level inverter topology;
FIG. 2 is a zero common mode voltage space vector diagram;
FIG. 3 is a model predictive control portion;
FIG. 4 is a current path corresponding to the output voltage of each level of the phase a;
FIG. 5 is a block diagram of a decoupling control neutral point voltage and floating capacitor voltage balancing process;
FIG. 6 is a waveform of the output three-phase voltage of the seven-level inverter;
FIG. 7 is a seven level inverter neutral voltage waveform;
FIG. 8 is a seven level inverter three phase floating capacitor voltage waveform;
FIG. 9 is a three-phase current waveform of a seven-level inverter;
FIG. 10 shows seven level inverter output line voltage UabA waveform;
fig. 11 is a seven-level inverter common-mode voltage waveform.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
The embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict.
Example one
The embodiment discloses a seven-level inverter circuit, and fig. 1 is a topological structure diagram of a cascaded seven-level inverter, which comprises a T-type three-level inverter and a circuit boardEach phase of the H-bridge circuit and the T-type three-level inverter comprises four IGBT tubes, can output three levels of-2E, 0 and 2E, and has a DC side power supply voltage U dc4E, the voltage of two capacitors at the direct current side is respectively 2E, and the voltage U of a suspension capacitor of the H-bridge circuitaf、Ubf、UcfAnd the current flows through different paths according to different switch states, and can realize seven levels output by each phase by matching with four IGBT tubes of the H-bridge circuit, so that seven levels of-3E, -2E, -E, 0, E, 2E and 3E can be obtained respectively. The simulation experiment parameters are set as follows: u shapedcFilter inductance L, 600V, 4EF10mH, filter resistance RF0.5 Ω, dc-side capacitance Cd1＝C d21000 muF, floating capacitance Ca＝Cb＝C c1000 muf, 20 Ω load resistance R, 3mH load inductance L, and network voltage Vg＝340V。
Each phase comprises 8 IGBT (insulated gate bipolar transistor) tubes, three phases share two direct-current side capacitors, and each H bridge of each phase is provided with a suspension capacitor Ujf(j＝a,b,c)。
Table 1 shows seven levels for the a-phase output and 12 corresponding switch states.
TABLE 1
Fig. 2 is a zero common mode voltage vector diagram. The common mode voltage is defined as:
the common mode voltage will cause leakage current, increase system loss, generate higher harmonics, and cause harm to the inverter and even human body. In addition, the common mode voltage also induces a shaft voltage,the insulation of the motor is reduced, and the service life of the motor is shortened. To reduce the common mode voltage, the present invention therefore selects only the zero common mode voltage vector as the candidate vector, for a total of 37 zero common mode voltage vectors. For example, if the integer 0-6 represents the output voltages-3E to 3E, and the abc three-phase output voltages are 3, 3 and 3, i.e., 0E and 0E, respectively, the sum of the three-phase voltages is 0, and the space voltage vector 000 is a zero common-mode voltage vector. In FIG. 2, the unit length on the α axis is represented by 1/3E, and the unit length on the β axis is represented by
The invention only adopts 37 zero common mode voltages as voltage candidate vectors, calculates two candidate vectors closest to a reference voltage vector by using model predictive control, synthesizes the reference voltage vector by using the two sections of voltage vectors, and has an analysis process as shown in figure 3. DC side voltage UdcThe value of (A) is 4E, and the DC side capacitor voltage should be controlled at Ucd1＝2E，Ucd2If the upper capacitor voltage is not equal to the lower capacitor voltage, the midpoint potential may be unbalanced, which may affect the output voltage and may cause a large harmonic component in the output current.
Model Predictive Control (MPC) is a new type of predictive control strategy, and has recently received wide attention from both domestic and foreign scholars. (see fig. 3 for details) model predictive control first builds a system model that predicts future behavior. To predict future behavior, a cost function is typically constructed, and to minimize this cost function, the best variables for the next sampling period are selected. Therefore, a cost function is calculated by Model Predictive Control (MPC), and two voltage vectors having the smallest cost function are obtained among the 37 zero common-mode voltage vectors. In order to ensure that seven levels can be output, the voltage U of the floating capacitoraf、Ubf、UcfShould be controlled to be E (U)dcAnd/4) or so. When the output levels are-E and E, the corresponding switch states can be used to control the floating capacitor voltage, respectively, and the detailed control analysis is illustrated in fig. 4 and fig. 5. For controlling the priority of neutral point voltage balance and suspended capacitor voltage balance, ABCThe phases share the dc side capacitance and either phase can be used to control the midpoint voltage balance, so the floating capacitor voltage balance should be preferentially controlled.
FIG. 3 is a model predictive control block diagram. Voltage V at the time of outputting k +1α(k+1)、Vβ(k +1) can be predicted as the voltage V at the time of k +1α(k+1)、Vβ(k +1), the current grid voltage e of the current sampleα、eβAnd obtaining the switching state of the three-phase grid-connected inverter and the direct-current bus voltage. After predicting the voltage at the moment k +1α(k+1)、Vβ(k +1), a cost function g is constructed to evaluate each voltage vector of the three-phase grid-connected inverter. Which two of these voltage vectors minimizes the cost function will be applied in the next sampling period. By making the derivative of the cost function 0, the respective action time of the two voltage vectors can be obtained. The specific process is as follows.
According to the circuit topology, can obtain
Through alpha-beta coordinate transformation, the method can obtain
In a sampling period TsIn, the current can be represented as discretized
Further can obtain
Taking the time calculated by the analog-digital converter and the algorithm into consideration, translating the discrete time equation of the model by one step to obtain the time delay
Considering the sampling period to be constant, the current at time k +1 can be expressed as
i(k+1)＝3i(k)-3i(k-1)+i(k-2) (7)
Can also obtain
The cost function is expressed as
g＝|Vα(k+1)-Vα|2+|Vβ(k+1)-Vβ|2 (9)
Two voltage vectors V1(k +1) and V2(k +1) with minimum g are obtained, and the action time is T1(k +1) and T2(k +1) let dg/dT1(k +1) ═ 0, and the first segment voltage vector action time can be found to be
From T1(k+1)+T2(k+1)＝TSCan obtain
T2(k+1)＝TS-T1 (11)
FIG. 4 shows the corresponding current paths for phase a with output voltages E and-E, and it can be seen that when the output voltage U isaAt E, two switch states S7, S8 can be used to decrease and increase the flying capacitor voltage U, respectivelyafWhen outputting the voltage Uaat-E, the same two switch states S4, S3 respectively decrease and increase the floating capacitor voltage UafTherefore, the voltage U of the floating capacitor can be controlled according to the voltageaf. At the moment, the neutral point voltage and the floating capacitor voltage need to be controlledThe rows are decoupled.
Fig. 5 is a block diagram of the decoupling control neutral point voltage and floating capacitor voltage balancing process. In formula 10, V is represented by phase ac2Is the lower end capacitor voltage of the DC side, Vc1For the DC side upper end capacitor voltage, there should be V to keep the neutral point voltage balancedc2-Vc1＝0。VFCFor the floating capacitor voltage, V should be present to keep the floating capacitor voltage balancedFC-Udc/4＝0。ΔVFCThe margin of the allowable deviation of the floating capacitance is provided. When the deviation of the voltage of the floating capacitor exceeds the allowable margin range delta VFCThe floating capacitor voltage balance should be controlled preferentially. When the voltage deviation of the suspension capacitor is within the allowable margin range delta VFCAnd controlling the neutral point voltage balance.
The specific control process is as follows: when U is turneda-3E, switch state S0 is selected; when U is turnedaWhen is-2E, if sigaNot less than 0, selecting switch state S1, if siga<0, select switch state S2; when U is turnedaWhen being-E, if sigaAt least 0, selecting switch state S4, and if siga<0, then switch state S3 is selected; when U is turnedaWhen equal to 0, if sigaNot less than 0, selecting switch state S5, if siga<0, select switch state S6; when U is turnedaWhen equal to E, if sigaNot less than 0, selecting switch state S7, if siga<0, select switch state S8; when U is turnedaWhen 2E, if sigaNot less than 0, selecting switch state S9, if siga<0, select switch state S10; when U is turnedaWhen 3E, switch state S11 is selected.
Fig. 6 is a waveform of the seven-level inverter output phase voltages. As can be seen from the voltage waveforms, each phase voltage achieves seven levels with amplitudes ranging from-3E (-450V) to 3E (450V).
Fig. 7 is a seven level inverter neutral voltage waveform. From the voltage waveform, the neutral point voltage can be seenBetter control fluctuates above and below 0. Fig. 8 is a three-phase floating capacitor voltage waveform. The voltage waveform shows that the voltage U of the suspension capacitoraf、Ubf、UcfAll are controlled to be about E (150V). Fig. 9 is a three-phase current waveform of the seven-level inverter. As can be seen from the current waveform, the distortion of the output current is small. Fig. 10 is a seven-level inverter output line voltage waveform. Fig. 11 is a seven-level inverter common-mode voltage waveform. As can be seen from the voltage waveform, the common mode voltage is well controlled to be about 0.
Example two
The present embodiment aims to provide a two-stage model prediction control method for a seven-level inverter, and specifically, abc three-phase sampling current is subjected to Clark transformation to obtain a current i under a two-phase stationary coordinate systemα(k) And iβ(k) Coordinate transformation is carried out on the abc three-phase network side sampling voltage to obtain a voltage value e under a two-phase static coordinate systemα(k) And eβ(k) Obtaining the current i by Lagrange extrapolationα(k +1) and iβ(k +1), and calculating the reference voltage value u at the next moment by the discretized model predictive control formulaα(k +1) and uβ(k +1), two voltage vectors with the minimum g are calculated through a cost function g and serve as candidate vectors, specific switch states are specifically selected according to the requirements of neutral point potential balance and suspension capacitor voltage balance, and finally the switch states are applied to each switch, and the switch state selection is shown in fig. 5.
In the space voltage vector diagram, only 37 zero common-mode voltage vectors are used as candidate vectors, and the problem of common-mode voltage is effectively solved.
The steps involved in the apparatus of the above embodiment correspond to the first embodiment of the method, and the detailed description thereof can be found in the relevant description of the first embodiment. The term "computer-readable storage medium" should be taken to include a single medium or multiple media containing one or more sets of instructions; it should also be understood to include any medium that is capable of storing, encoding or carrying a set of instructions for execution by a processor and that cause the processor to perform any of the methods of the present disclosure.
Those skilled in the art will appreciate that the modules or steps of the present disclosure described above can be implemented using general purpose computer means, or alternatively, they can be implemented using program code executable by computing means, whereby the modules or steps may be stored in memory means for execution by the computing means, or separately fabricated into individual integrated circuit modules, or multiple modules or steps thereof may be fabricated into a single integrated circuit module. The present disclosure is not limited to any specific combination of hardware and software.
The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.
Although the present disclosure has been described with reference to specific embodiments, it should be understood that the scope of the present disclosure is not limited thereto, and those skilled in the art will appreciate that various modifications and changes can be made without departing from the spirit and scope of the present disclosure.
Claims (10)
1. A seven-level inverter circuit, comprising: the T-type three-level inverter outputs three levels and is cascaded with the H-bridge circuit to realize that each phase outputs seven levels; the three phases of the T-type three-level inverter share two direct-current side capacitors, and each phase is provided with a suspension capacitor;
the upper capacitor voltage and the lower capacitor voltage of the direct-current side voltage of the T-type three-level inverter are equal to each other, so that neutral point voltage balance is achieved.
2. The seven-level inverter circuit as claimed in claim 1, wherein the T-type three-level inverter comprises two capacitors on the dc side, four switching tubes on each phase bridge arm, the dc side voltage is Udc, and three voltage levels of-Udc/2, 0 and Udc/2 are realized by adjusting the on/off of the switching tubes.
3. The seven-level inverter circuit according to claim 1, wherein the H-bridge circuit comprises three branches connected in parallel, the first branch and the second branch are two switching tubes connected in series, the third branch is a floating capacitor, and the voltage of the floating capacitor is controlled to be E, so that two voltage levels of-E and E of the H-bridge circuit are realized.
4. A control method of a seven-level inverter circuit is characterized by comprising the following steps:
the three-phase sampling current is subjected to Clark conversion to obtain a current under a two-phase static coordinate system;
the three-phase network side sampling voltage is subjected to coordinate transformation to obtain a voltage value under a two-phase static coordinate system;
obtaining current at the next moment by a Lagrange extrapolation method, calculating a reference voltage value at the next moment by discretized model predictive control, and calculating two minimum voltage vectors serving as candidate vectors by a cost function;
and selecting a specific switch state according to the requirements of neutral point potential balance and suspension capacitor voltage balance, and finally applying the switch state to each switch to output seven levels.
5. The method as claimed in claim 4, wherein in controlling the neutral point voltage balance and the floating capacitor voltage balance, the floating capacitor voltage balance priority is higher than the neutral point voltage balance.
6. The method for controlling the seven-level inverter circuit according to claim 4, wherein the dc side power supply is 4E, the T-type three-level inverter can output three levels of-2E, 0 and 2E, and the seven-level inverter is matched with the H-bridge circuit to realize seven levels output per phase, specifically: -3E, -2E, -E, 0, E, 2E, 3E.
7. The method as claimed in claim 4, wherein the corresponding switch states are used to control the floating capacitor voltage when the output level is-E and E, respectively.
8. The method as claimed in claim 4, wherein the cost function is expressed as
g＝|Vα(k+1)-Vα|2+|Vβ(k+1)-Vβ|2。
9. A seven-level inverter comprising the seven-level inverter circuit according to any one of claims 1 to 3, wherein a plurality of the seven-level inverter circuits are connected in parallel on the common dc bus side.
10. A frequency converter is characterized by comprising: a rectifying circuit and a plurality of seven-level inverter circuits as claimed in any one of claims 1 to 3, wherein the input end of the rectifying circuit is connected with the power grid, the output end of the rectifying circuit is connected with the common DC bus, and the plurality of seven-level inverter circuits are connected in parallel with the common DC bus.
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| 耿俊利等: "基于SVPWM调制的混合级联七电平逆变器优化控制策略", 《电网技术》 * |
| 耿俊利等: "基于SVPWM调制的混合级联七电平逆变器优化控制策略", 《电网技术》, vol. 39, no. 02, 5 February 2015 (2015-02-05), pages 327 - 333 * |
| 虞汉阳: "基于H桥单元的组合拓扑系统若干关键技术研究", 《中国优秀博硕士学位论文全文数据库（博士） 工程科技II辑》 * |
| 虞汉阳: "基于H桥单元的组合拓扑系统若干关键技术研究", 《中国优秀博硕士学位论文全文数据库（博士） 工程科技II辑》, 15 April 2019 (2019-04-15), pages 46 - 51 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116436329A (en) * | 2023-05-10 | 2023-07-14 | 苏州大学 | Three-phase four-bridge arm hybrid seven-level energy storage converter |
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