CN112992835A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN112992835A CN112992835A CN201911301083.7A CN201911301083A CN112992835A CN 112992835 A CN112992835 A CN 112992835A CN 201911301083 A CN201911301083 A CN 201911301083A CN 112992835 A CN112992835 A CN 112992835A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4885—Wire-like parts or pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4885—Wire-like parts or pins
- H01L21/4889—Connection or disconnection of other leads to or from wire-like parts, e.g. wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention relates to a semiconductor device and a manufacturing method thereof. Wherein the semiconductor device includes a semiconductor element, the semiconductor element including: the chip comprises a first side surface and a second side surface which are oppositely arranged, wherein the first side surface is provided with at least one electrode area and a non-electrode area, and each electrode area of the at least one electrode area is internally provided with an electrode; the at least one electrode region includes a first electrode region; the adhesive film layer is arranged on the non-electrode area; the first electric connector comprises a first joint part, the first joint part is adhered to the film layer, the first electric connector, the first electrode area and the film layer around the first electrode area form a cavity together, and a through hole is formed in the position, corresponding to the cavity, of the first electric connector; and the conductive connector is arranged in the cavity and the through hole and used for connecting the first electric connector with the chip. The invention can relieve the overflow of the conductive bonding material and the generation of voids or bubbles, so that the connection between the chip and the first electric connector is tighter and the reliability is improved.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
With the development of integration, modularization and miniaturization of electronic integrated circuits, the requirements for chip packaging are higher and higher. The heating problem of the power device is one of the most main problems in the semiconductor industry, and therefore people have conducted related exploration, and from the beginning, the lead is welded to the attachment of the radiating fin, and then the radiating effect is greatly improved through the copper bridge radiating structure.
Although the heat dissipation effect is obviously improved by adopting the copper bridge heat dissipation structure, the problems of untight joint between the chip and the copper bridge and the like are caused by glue overflow and cavities existing between the chip and the copper bridge in the packaging process, and the product failure can occur along with the increase of the service time.
Disclosure of Invention
Some embodiments of the present invention provide a semiconductor device and a method for fabricating the same for alleviating the problem of bonding non-tightness.
Some embodiments of the present invention provide a semiconductor device comprising a semiconductor component, the semiconductor component comprising:
the chip comprises a first side surface and a second side surface which are oppositely arranged, wherein the first side surface is provided with at least one electrode area and a non-electrode area, and an electrode is arranged in each electrode area of the at least one electrode area; the at least one electrode region comprises a first electrode region;
the glue film layer is arranged on the non-electrode area;
the first electric connector comprises a first joint part, the first joint part is adhered to the film layer, the first electric connector, the first electrode area and the film layer around the first electrode area jointly form a cavity, and a through hole is formed in the position of the first electric connector corresponding to the cavity; and
and the conductive connector is arranged in the cavity and the through hole and is used for connecting the first electric connector with the chip.
In some embodiments, the through-hole has a cross-sectional area smaller than a cross-sectional area of the cavity.
In some embodiments, the semiconductor assembly further comprises a lead frame mounted on a side of the chip remote from the adhesive film layer, and a first conductive bonding layer disposed between the chip and the lead frame, the chip being bonded to the lead frame by the first conductive bonding layer.
In some embodiments, the semiconductor assembly further includes a first lead and a second conductive bonding layer disposed on the first lead, and the first electrical connector further includes a second bonding portion bonded to the first lead by the second conductive bonding layer.
In some embodiments, the first lead and the lead frame are located at the same horizontal plane, and a corner is formed between the first joint part and the second joint part of the first electric connector.
In some embodiments, the semiconductor assembly further comprises a second lead, a third conductive bonding layer disposed on the second lead, the at least one electrode region comprises a second electrode region, a fourth conductive bonding layer disposed on the second electrode region, a first end of the second electrical connector is joined to the second lead by the third conductive bonding layer, and a second end of the second electrical connector is joined to the second electrode region by the fourth conductive bonding layer.
In some embodiments, further comprising an encapsulation material encapsulating the semiconductor assembly, wherein the first electrical connections comprise external junctions exposing the encapsulation material.
In some embodiments, the first electrical connector further comprises a plating layer provided on an external junction surface of the first electrical connector.
In some embodiments, the first electrode region is provided with an emitter, the second side is provided with a collector, and the second electrode region is provided with a gate.
In some embodiments, the material of the glue film layer comprises epoxy or silicone.
In some embodiments, the material of the first electrical connector comprises copper, iron-nickel alloy, or copper-nickel alloy.
In some embodiments, the material of the conductive bonding member includes solder paste, silver paste, or conductive paste.
In some embodiments, the encapsulation material comprises an epoxy.
Some embodiments of the present invention provide a method for manufacturing the semiconductor device, which includes:
step S10: arranging an adhesive film layer on a non-electrode area of the chip;
step S20: bonding a first joint part of the first electric connector with the adhesive film layer;
step S30: and injecting a conductive bonding material into the cavity through the through hole until the cavity and the through hole are filled with the conductive bonding material, and curing the conductive bonding material to form the conductive bonding member.
In some embodiments, step S10 further includes disposing a first conductive bonding layer on the lead frame;
further included between the step S10 and the step S20 is a step S11: and placing the chip on the first conductive bonding layer, attaching the second side face of the chip to the first conductive bonding layer, and curing the first conductive bonding layer at high temperature to bond the chip and the lead frame.
In some embodiments, between step S11 and step S20, further comprising step S12: arranging a second conductive bonding layer on the first pin; arranging a third conductive bonding layer on the second pin, wherein at least one electrode region comprises a second electrode region, and arranging a fourth conductive bonding layer on the second electrode region;
step S20 further includes bonding a second bonding portion of the first electrical connector to the first lead through the second conductive bonding layer; and jointing the first end of the second electric connecting piece with the second pin through a third conductive bonding layer, and jointing the second end of the second electric connecting piece with the second electrode area through a fourth conductive bonding layer.
In some embodiments, step S30 is followed by step S40: packaging the semiconductor assembly assembled in the previous step; and the external connection surface of the first electric connector is exposed from the package, the external connection part of the first pin and the external connection part of the second pin are exposed from the package, and the external connection part of the third pin arranged on the lead frame is exposed from the package.
In some embodiments, step S50 is further included after step S40: and arranging an electroplated layer on the external connection surface of the first electric connector.
Based on the technical scheme, the invention at least has the following beneficial effects:
in some embodiments, by disposing a film layer on the non-electrode region of the chip, the first joint portion of the first electrical connector is bonded to the film layer, and the film layer has a buffer effect on the chip and the first electrical connector; through the through hole that sets up on the first electric connector to injecting the electrically conductive combined material in the cavity between first electric connector and the first electrode region, can alleviate the problem that the electrically conductive combined material spills over all around, and the through hole can be with the air escape in the cavity, alleviate the cavity or the bubble problem that the in-process that injects the electrically conductive combined material produced, alleviate the influence that the pressure impact caused to the chip, make the joint between chip and the first electric connector more abundant inseparable, the electrical property is more reliable, the reliability of power semiconductor device has been improved greatly.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
fig. 1 is a schematic cross-sectional view of a semiconductor device provided in accordance with some embodiments of the present invention;
fig. 2 is a schematic top view of a semiconductor device provided in accordance with some embodiments of the present invention;
FIG. 3 is a schematic top view of a semiconductor device provided in accordance with some embodiments of the present invention without a plating layer;
FIG. 4 is a schematic diagram of a first side of a chip provided in accordance with some embodiments of the invention;
FIG. 5 is a schematic cross-sectional view of a chip with an adhesive film layer disposed on a first side thereof according to some embodiments of the invention;
FIG. 6 is a schematic cross-sectional view of bonding a chip to a leadframe provided in accordance with some embodiments of the invention;
fig. 7 is a schematic top view of a chip bonded to a leadframe provided in accordance with some embodiments of the invention;
fig. 8 is a schematic top view of a conductive bonding layer disposed on a chip and a lead according to some embodiments of the invention;
FIG. 9 is a schematic top view of a first electrical connector and a second electrical connector provided in accordance with some embodiments of the invention;
fig. 10 is a schematic cross-sectional view of a first electrical connector and a second electrical connector provided in accordance with some embodiments of the present invention.
The reference numbers in the drawings illustrate the following:
1-chip; 11-a first side; 12-a second side; 13-electrode region; 131-a first electrode region; 132-a second electrode zone; 14-a non-electrode region;
2-a glue film layer;
3-a first electrical connection; 31-a first engagement; 311-first site; 312-second site; 32-a second engagement; 33-a via hole; 34-a cavity;
4-a conductive bond;
5-a lead frame;
61-a first electrically conductive bonding layer; 62-a second electrically conductive bonding layer; 63-a third electrically conductive bonding layer; 64-a fourth electrically conductive bonding layer;
71-a first pin; 72-a second pin; 73-a third pin;
8-a second electrical connection;
9-electroplating layer;
100-a semiconductor component; 200-packaging material.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments. It is to be understood that the described embodiments are merely a few embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without any inventive step, are within the scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate orientations or positional relationships based on those shown in the drawings, and are used merely for convenience in describing the present invention and for simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be taken as limiting the scope of the present invention.
As shown in fig. 1, a semiconductor device according to some embodiments includes a semiconductor device 100. The semiconductor assembly 100 includes a chip 1, an adhesive film layer 2, a first electrical connector 3, and a conductive bond 4.
The chip 1 is also known as a microcircuit, microchip or integrated circuit.
As shown in fig. 5, the chip 1 includes a first side 11 and a second side 12 disposed opposite to each other. As shown in fig. 4, the first side 11 is provided with non-electrode areas 14 and at least one electrode area 13, and an electrode is provided in each electrode area 13 of the at least one electrode area 13. The at least one electrode region 13 includes a first electrode region 131 and a second electrode region 132.
As shown in fig. 5, the adhesive film layer 2 is provided on the non-electrode region 14. In some embodiments, the material of the glue film layer 2 comprises epoxy resin or silicon gel.
The adhesive film layer 2 has flexibility and adhesiveness, has compressive strength and insulation property in a high-temperature curing state, can provide physical and electrical protection, and prevents the chip 1 from being impacted by an external environment.
As shown in fig. 1, the first electrical connector 3 includes a first joint portion 31, and a part of the first joint portion 31 is bonded to the adhesive film layer 2. As shown in fig. 10, the first electrical connector 3, the first electrode region 131, and the film layer 2 around the first electrode region 131 together form a cavity 34, and a through hole 33 is formed at a position of the first electrical connector 3 corresponding to the cavity 34.
In some embodiments, the material of the first electrical connector 3 comprises copper, iron-nickel alloy or copper-nickel alloy.
In some embodiments, the first electrical connection 3 comprises a copper bridge.
As shown in fig. 1, the conductive bonding member 4 is disposed in the cavity 34 and the through hole 33, and bonds the first electrical connector 3 with the chip 1.
In some embodiments, the material of the conductive bonding member 4 includes solder paste, conductive silver paste, conductive adhesive, or the like.
In some embodiments, the non-electrode region 14 of the chip 1 is provided with the adhesive film layer 2, the first joint portion 31 of the first electrical connector 3 is adhered to the adhesive film layer 2, the first electrical connector 3, the first electrode region 131 and the adhesive film layer 2 around the first electrode region 131 together form a cavity 34, a through hole 33 is formed in a position of the first electrical connector 3 corresponding to the cavity 34, then a conductive bonding material is injected into the cavity 34 through the through hole 33, the conductive bonding material is injected into the cavity 34 to relieve the conductive bonding material from overflowing to the periphery, the through hole 33 can exhaust air, the problem of cavities or bubbles generated in the process of injecting the conductive bonding material is relieved, pressure impact on the chip 1 is relieved, and the bonding between the chip 1 and the first electrical connector 3 is more sufficient and compact, and the electrical performance is more reliable.
Moreover, set up glued membrane layer 2 at chip 1's non-electrode zone 14, first joint portion 31 and the glued membrane layer 2 bonding of first electric connector 3, glued membrane layer 2 has the cushioning effect to chip 1 and first electric connector 3, makes the pressure impact that produces chip 1 reduce, has improved power semiconductor device's reliability greatly.
In some embodiments, as shown in FIG. 10, the cross-sectional area of the through-hole 33 is less than the cross-sectional area of the cavity 34. The section here is a section formed by cross-section of the assembly shown in fig. 10, that is, the cross-sectional area of the through-hole 33 is smaller than the cross-sectional area of the cavity 34.
In some embodiments, the through-holes 33 comprise circular holes. Optionally, the circular holes have a diameter in the range of 0.5mm to 2 mm.
In some embodiments, as shown in fig. 6, the semiconductor assembly 100 further includes a lead frame 5 and a first conductive bonding layer 61, the lead frame 5 is disposed on a side of the chip 1 away from the adhesive film layer 2, the first conductive bonding layer 61 is disposed between the chip 1 and the lead frame 5, and the chip 1 is bonded to the lead frame 5 through the first conductive bonding layer 61.
In some embodiments, the material of the first conductive bonding layer 61 includes solder paste, conductive silver paste, conductive paste, or the like.
The lead frame 5 is a carrier for carrying the chip 1 and the integrated circuit thereof, and is also used as a leading-out terminal for electrically connecting with an external lead, so as to form a key structural member of a loop.
The electrode areas 13 of the chip 1 are bonded to the first electrical connections 3 by means of an electrically conductive bond 4 and the second side 12 of the chip 1 is bonded to the lead frame 5 by means of a first electrically conductive bonding layer 61.
In some embodiments, as shown in fig. 1, the semiconductor assembly 100 further includes a first lead 71 and a second conductive bonding layer 62, the second conductive bonding layer 62 is disposed on the first lead 71, the first electrical connector 3 further includes a second bonding portion 32, and the second bonding portion 32 is bonded to the first lead 71 through the second conductive bonding layer 62.
In some embodiments, the material of the second conductive bonding layer 62 includes solder paste, conductive silver paste, conductive paste, or the like.
In some embodiments, the first lead 71 and the lead frame 5 are located at the same horizontal plane, and a corner is formed between the first joint portion 31 and the second joint portion 32 of the first electrical connector 3.
Since the first lead 71 and the surface of the lead frame 5 have lead portions and are not strictly planar, the first lead 71 and the lead frame 5 are substantially located on the same horizontal plane.
In the positional relationship shown in fig. 1, the height of the first junction 31 of the first electrical connector 3 is higher than that of the first lead 71, the first end of the second junction 32 is connected to the first junction 31, and the second end of the second junction 32 is joined to the first lead 71 by the second conductive bonding layer 62, and thus, a corner is formed between the first junction 31 and the second junction 32 of the first electrical connector 3. Optionally, the angle of the corner between the first junction 31 and the second junction 32 of the first electrical connector 3 is 90 degrees.
In some embodiments, as shown in fig. 9, the semiconductor assembly 100 further includes a second lead 72, a third conductive bonding layer 63, a fourth conductive bonding layer 64, and a second electrical connector 8, the third conductive bonding layer 63 being disposed on the second lead 72. As shown in fig. 7 and 8, the at least one electrode region 13 includes a second electrode region 132, and the fourth conductive bonding layer 64 is provided on the second electrode region 132. As shown in fig. 9, a first end of the second electrical connector 8 is joined to the second lead 72 by a third electrically conductive bonding layer 63, and a second end of the second electrical connector 8 is joined to the second electrode region 132 by a fourth electrically conductive bonding layer 64.
In some embodiments, the material of the third and fourth conductive bonding layers 63 and 64 includes solder paste, conductive silver paste, conductive paste, or the like.
In some embodiments, as shown in fig. 3, the first joint 31 of the first electrical connector 3 includes a first portion 311 and a second portion 312, an area of the first portion 311 is larger than an area of the second portion 312, the first portion 311 is located opposite to the chip 1, a partial region of the first portion 311 is bonded to the adhesive film layer 2, and the through hole 34 is disposed in a region of the first portion 311 corresponding to the cavity 34. The second portion 312 has an area smaller than that of the first portion 311, and has functions of avoiding the second electrode regions 132 and reducing material consumption, as shown in fig. 9.
In some embodiments, as shown in fig. 1, the semiconductor device further comprises an encapsulation material 200, the encapsulation material 200 encapsulating the semiconductor assembly 100, wherein the first electrical connection 3 comprises an outer junction exposed from the encapsulation material 200. The outer junction surface is a surface of the first bonding portion 31 on a side away from the chip 1.
The first electric connector 3 is used as a leading-out terminal to realize electric connection with the outside and main heat dissipation of the device.
The packaging material 200 is used for sealing the whole integrated circuit chip, isolating the influence of physical environment on the normal operation of the circuit, and simultaneously enabling the chip to be molded in a plastic package mode to form an independent device.
In some embodiments, the encapsulation material 200 includes an epoxy.
In some embodiments, as shown in fig. 2, the semiconductor device further comprises a plated layer 9, the plated layer 9 being provided at an outer junction of the first electrical connection 3.
In order to better arrange the electroplated layer 9, the external connection surface of the first electric connecting piece 3 is polished to make the external connection surface of the first electric connecting piece 3 smooth and flat, and then the external connection surface of the first electric connecting piece 3 is electroplated to form the electroplated layer 9.
In some embodiments, the first electrode regions 131 are provided with electrodes that are emitters through which current flows. The second side 12 is provided with a collector. The second electrode region 132 is provided with an electrode as a gate electrode, and the gate electrode is a driving control electrode.
In some embodiments, chip 1 comprises an IGBT chip. Igbt (insulated Gate Bipolar transistor), insulated Gate Bipolar transistor.
In some embodiments, in the positional relationship shown in fig. 1 and 10, the top of the lead frame 5 is provided with the first conductive bonding layer 61, the top of the first conductive bonding layer 61 is provided with the chip 1, the non-electrode region 14 on the top of the chip 1 is provided with the adhesive film layer 2, the top of the adhesive film layer 2 is provided with the first bonding portion 31 of the first electrical connector 3, the through hole 33 provided in the first bonding portion 31 is communicated with the cavity 34, and the conductive bonding material is injected into the through hole 33 and the cavity 34 and cured at a high temperature to form the conductive bonding member 4.
In the positional relationship shown in fig. 9, the first lead 71 and the second lead 72 are provided on one side of the lead frame 5, and the distance between the first lead 71 and the lead frame 5 is substantially equal to the distance between the second lead 72 and the lead frame 5. In the positional relationship shown in fig. 1 and 10, the first lead 71, the second lead 72, and the lead frame 5 are located substantially on the same horizontal plane.
Some embodiments provide a method of manufacturing a semiconductor device, comprising:
step S10: the adhesive film layer 2 is disposed on the non-electrode region 14 of the chip 1 as shown in fig. 5.
Step S20: the first joint 31 of the first electrical connector 3 is bonded to the adhesive film layer 2 as shown in fig. 10.
Step S30: the conductive bonding material is injected into the cavity 34 through the via 33 until the cavity 34 and the via 33 are filled with the conductive bonding material, and the conductive bonding material is cured to form the conductive bond 4, as shown in fig. 1.
In some embodiments, step S10 further includes disposing a first conductive bonding layer 61 on the lead frame 5.
Between step S10 and step S20, step S11 is further included: the chip 1 is placed on the first conductive bonding layer 61 with the second side 12 of the chip 1 attached to the first conductive bonding layer 61, and the first conductive bonding layer 61 is cured at a high temperature to bond the chip 1 to the lead frame 5, as shown in fig. 6.
In some embodiments, between step S11 and step S20, further comprising step S12: providing a second conductive bonding layer 62 on the first lead 71; a third conductive bonding layer 63 is disposed on the second lead 72 as shown in fig. 8. The at least one electrode region 13 includes a second electrode region 132, and a fourth conductive bonding layer 64 is disposed on the second electrode region 132, as shown in fig. 7 and 8.
Step S20 further includes bonding second bonding portion 32 of first electrical connector 3 to first lead 71 through second conductive bonding layer 62; a first end of the second electrical connector 8 is joined to the second lead 72 by a third electrically conductive bonding layer 63 and a second end of the second electrical connector 8 is joined to the second electrode region 132 by a fourth electrically conductive bonding layer 64, as shown in fig. 9.
In some embodiments, step S30 is followed by step S40: packaging the semiconductor assembly 100 assembled in the previous step, as shown in fig. 1; the external connection surface of the first electrical connector 3 is exposed from the package, the external connection portions of the first leads 71 and the second leads 72 are exposed from the package, and the external connection portion of the third leads 73 provided on the lead frame 5 is exposed from the package.
In some embodiments, step S50 is further included after step S40: a plating layer 9 is provided on the outer peripheral surface of the first electrical connector 3, as shown in fig. 2.
In some embodiments, a method of fabricating a semiconductor device includes:
step S1: arranging an adhesive film layer 2 on the non-electrode area 14 of the chip 1, as shown in fig. 5; a first conductive bonding layer 61 is disposed on the lead frame 5.
Step S2: the chip 1 is placed on the first conductive bonding layer 61 with the second side 12 of the chip 1 attached to the first conductive bonding layer 61, and the first conductive bonding layer 61 is cured at a high temperature to bond the chip 1 to the lead frame 5, as shown in fig. 6.
Step S3: providing a second conductive bonding layer 62 on the first lead 71; the third conductive bonding layer 63 is disposed on the second leads 72, and the fourth conductive bonding layer 64 is disposed on the second electrode regions 132, as shown in fig. 7 and 8.
Step S4: bonding the first bonding part 31 of the first electric connector 3 with the adhesive film layer 2, and bonding the second bonding part 32 of the first electric connector 3 with the first pin 71 through the second conductive bonding layer 62; a first end of second electrical connector 8 is bonded to second lead 72 by third electrically conductive bonding layer 63 and a second end of second electrical connector 8 is bonded to die 1 by fourth electrically conductive bonding layer 64, as shown in fig. 9 and 10.
Step S5: and injecting a conductive bonding material into the cavity 34 through the through hole 33 until the cavity 34 and the through hole 33 are filled with the conductive bonding material, and curing the conductive bonding material at a high temperature to form the conductive bonding member 4, so that the first electric connecting member 3 is more fully bonded with the chip 1.
Step S6: all the components assembled in steps S1 to S5 are packaged with the package material 200, the external connection surface of the first electrical connector 3 is exposed from the package, the external connection portions of the first leads 71 and the external connection portions of the second leads 72 are exposed from the package material 200, the external connection portion of the third lead 73 provided on the lead frame 5 is exposed from the package material 200, and the package material 200 is completely reacted by curing after the plastic molding, as shown in fig. 3.
Step S7: a plating layer 9 is provided on the outer peripheral surface of the first electrical connector 3 to improve the oxidation resistance and solderability of the first electrical connector 3, as shown in fig. 2.
Step S8: and (4) polishing the electroplated layer 9 after electroplating to ensure that the surface is smooth and flat.
Based on the above embodiments, the present disclosure provides the adhesive film layer 2 on the non-electrode region 14 of the chip 1, the first joint portion 31 of the first electrical connector 3 is adhered to the adhesive film layer 2, and the adhesive film layer 2 has a buffer effect on the chip 1 and the first electrical connector 3; through the through-hole 33 that sets up on the first electric connector 3 to injecting electrically conductive combined material in the cavity 34 between first electric connector 3 and the first electrode region 131, can alleviate the problem that electrically conductive combined material overflows all around, and the through-hole 33 can be discharged the air, alleviate the problem of the cavity or the bubble that produce of the in-process of injecting electrically conductive combined material, alleviate the influence that causes the pressure impact to chip 1, make the joint between chip 1 and the first electric connector 3 more abundant inseparable, the electrical property is more reliable, the reliability of power semiconductor device has been improved greatly.
In the description of the present invention, it should be understood that the terms "first", "second", "third", etc. are used to define the components, and are used only for the convenience of distinguishing the components, and if not otherwise stated, the terms have no special meaning, and thus, should not be construed as limiting the scope of the present invention.
Furthermore, the technical features of one embodiment may be combined with one or more other embodiments advantageously without explicit negatives.
Finally, it should be noted that the above examples are only used to illustrate the technical solutions of the present invention and not to limit the same; although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art will understand that: modifications to the specific embodiments of the invention or equivalent substitutions for parts of the technical features may be made; without departing from the spirit of the present invention, it is intended to cover all aspects of the invention as defined by the appended claims.
Claims (18)
1. A semiconductor device comprising a semiconductor component (100), the semiconductor component (100) comprising:
the chip (1) comprises a first side surface (11) and a second side surface (12) which are oppositely arranged, wherein the first side surface (11) is provided with at least one electrode area (13) and a non-electrode area (14), and an electrode is arranged in each electrode area (13) of the at least one electrode area (13); the at least one electrode zone (13) comprises a first electrode zone (131);
the adhesive film layer (2) is arranged on the non-electrode area (14);
the first electric connector (3) comprises a first joint part (31), the first joint part (31) is adhered to the adhesive film layer (2), the first electric connector (3), the first electrode regions (131) and the adhesive film layer (2) around the first electrode regions (131) jointly form a cavity (34), and through holes (33) are formed in positions, corresponding to the cavity (34), of the first electric connector (3); and
and the conductive bonding part (4) is arranged in the cavity (34) and the through hole (33) and is used for bonding the first electric connector (3) with the chip (1).
2. The semiconductor device according to claim 1, wherein a cross-sectional area of the through-hole (33) is smaller than a cross-sectional area of the cavity (34).
3. The semiconductor device according to claim 1, wherein the semiconductor assembly (100) further comprises a lead frame (5) and a first electrically conductive bonding layer (61), the lead frame (5) being provided on a side of the chip (1) remote from the adhesive film layer (2), the first electrically conductive bonding layer (61) being provided between the chip (1) and the lead frame (5), the chip (1) being bonded to the lead frame (5) through the first electrically conductive bonding layer (61).
4. The semiconductor device according to claim 3, wherein the semiconductor assembly (100) further comprises a first lead (71) and a second electrically conductive bonding layer (62), the second electrically conductive bonding layer (62) being provided to the first lead (71), the first electrical connector (3) further comprising a second bonding portion (32), the second bonding portion (32) being bonded to the first lead (71) through the second electrically conductive bonding layer (62).
5. A semiconductor device according to claim 4, characterized in that the first lead (71) is located at the same level as the lead frame (5), and a corner is formed between the first joint (31) and the second joint (32) of the first electrical connection (3).
6. A semiconductor device as claimed in claim 1, characterized in that the semiconductor component (100) further comprises a second lead (72), a third electrically conductive bonding layer (63), a fourth electrically conductive bonding layer (64) and a second electrical connector (8), the third electrically conductive bonding layer (63) being provided at the second lead (72), the at least one electrode zone (13) comprising a second electrode zone (132), the fourth electrically conductive bonding layer (64) being provided at the second electrode zone (132), a first end of the second electrical connector (8) being joined to the second lead (72) via the third electrically conductive bonding layer (63), and a second end of the second electrical connector (8) being joined to the second electrode zone (132) via the fourth electrically conductive bonding layer (64).
7. The semiconductor device according to claim 1, further comprising an encapsulation material (200), the encapsulation material (200) encapsulating the semiconductor assembly (100), wherein the first electrical connection (3) comprises an external connection surface exposing the encapsulation material (200).
8. A semiconductor device according to claim 7, further comprising a plated layer (9), said plated layer (9) being provided at an outer junction of said first electrical connection (3).
9. A semiconductor device as claimed in claim 6, characterized in that the electrode provided in the first electrode region (131) is an emitter electrode, the second side (12) is provided with a collector electrode, and the electrode provided in the second electrode region (132) is a gate electrode.
10. The semiconductor device according to claim 1, wherein a material of the adhesive film layer (2) includes an epoxy resin or a silicone.
11. A semiconductor device as claimed in claim 1, characterized in that the material of the first electrical connection (3) comprises copper, iron-nickel alloy or copper-nickel alloy.
12. The semiconductor device according to claim 1, wherein the material of the conductive bonding member (4) comprises solder paste, silver paste or conductive paste.
13. The semiconductor device of claim 7, wherein the encapsulation material (200) comprises an epoxy.
14. A method for manufacturing a semiconductor device according to claim 1, comprising:
step S10: arranging a film layer (2) on a non-electrode area (14) of the chip (1);
step S20: bonding a first joint part (31) of the first electric connector (3) with the adhesive film layer (2);
step S30: and injecting the conductive bonding material into the cavity (34) through the through hole (33) until the cavity (34) and the through hole (33) are filled with the conductive bonding material, and curing the conductive bonding material to form the conductive bonding member (4).
15. The method for manufacturing a semiconductor device according to claim 14, further comprising the steps of providing a first conductive bonding layer (61) on the lead frame (5) in step S10;
further included between the step S10 and the step S20 is a step S11: and placing the chip (1) on the first conductive bonding layer (61), attaching the second side (12) of the chip (1) to the first conductive bonding layer (61), and curing the first conductive bonding layer (61) at high temperature to bond the chip (1) and the lead frame (5).
16. The method for manufacturing a semiconductor device according to claim 15, further comprising, between the step S11 and the step S20, a step S12 of: providing a second conductive bonding layer (62) on the first lead (71); providing a third electrically conductive bonding layer (63) on the second lead (72), the at least one electrode region (13) comprising a second electrode region (132), and providing a fourth electrically conductive bonding layer (64) on the second electrode region (132);
step S20 further includes bonding the second bonding portion (32) of the first electrical connector (3) to the first lead (71) through the second conductive bonding layer (62); a first end of the second electrical connector (8) is joined to the second lead (72) by a third electrically conductive bonding layer (63) and a second end of the second electrical connector (8) is joined to the second electrode region (132) by a fourth electrically conductive bonding layer (64).
17. The method for manufacturing a semiconductor device according to claim 16, further comprising, after the step S30, a step 40 of: packaging the semiconductor assembly (100) assembled in the previous step; the external connection surface of the first electric connector (3) is exposed from the package, the external connection part of the first lead (71) and the external connection part of the second lead (72) are exposed from the package, and the external connection part of the third lead (73) arranged on the lead frame (5) is exposed from the package.
18. The method for manufacturing a semiconductor device according to claim 17, further comprising, after the step S40, a step S50: an electroplated layer (9) is arranged on the external connection surface of the first electric connector (3).
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| US20110227205A1 (en) * | 2010-03-18 | 2011-09-22 | Jun Lu | Multi-layer lead frame package and method of fabrication |
| CN103325755A (en) * | 2012-03-21 | 2013-09-25 | 南茂科技股份有限公司 | Semiconductor packaging structure |
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