CN112992255A

CN112992255A - Smart memory device test resources

Info

Publication number: CN112992255A
Application number: CN202011496987.2A
Authority: CN
Inventors: G·D·哈默
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2019-12-18
Filing date: 2020-12-17
Publication date: 2021-06-18

Abstract

The present disclosure relates to smart memory device test resources. A memory device test resource includes a special purpose processing device of the memory device test resource configured to facilitate testing of a memory device of a memory subsystem coupled to the memory device test resource. The memory device test resources further include: a memory subsystem interface port coupled to the special purpose processing device and configured to couple the memory device test resources to the processing device; a test condition component coupled to the special purpose processing device and configured to generate a test condition at the memory device test resource; and a test resource monitoring component coupled to the dedicated processing device and configured to monitor one or more conditions at the memory device test resources.

Description

Smart memory device test resources

Technical Field

Embodiments of the present disclosure relate generally to memory subsystems and, more particularly, to smart memory device test resources.

Background

The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, a host system may utilize a memory subsystem, storing data at and retrieving data from a memory device.

Disclosure of Invention

In one aspect, the present disclosure is directed to a memory device test resource, comprising: a dedicated processing device of the memory device test resources, the dedicated processing device configured to facilitate testing of memory devices of a memory subsystem coupled to the memory device test resources; a memory subsystem interface port coupled to the special purpose processing device and configured to couple the memory device test resources to the memory subsystem; a test condition component coupled to the special purpose processing device and configured to generate a test condition at the memory device test resource; a test resource monitoring component coupled to the dedicated processing device and configured to monitor one or more conditions at the memory device test resources.

In another aspect, the present disclosure is directed to a system comprising: a memory device; and a processing device operatively coupled to the memory device, the processing device performing operations comprising: receiving, from a requestor, a first request to perform a test for a memory device of a memory subsystem at a memory device test rack, wherein the memory device test rack comprises a plurality of memory device test resources, each memory device test resource comprising a separate processing device; transmitting a second request to each separate processing device to determine which memory device test resources of the plurality of memory device test resources are available to perform the test of the memory devices of the memory subsystem; receiving a response from each individual processing device, the response including an indication of whether each of the plurality of memory device test resources is available to perform the test; determining available memory device test resources of the memory device test rack to perform the test based on the responses received from each individual processing device; and transmitting an indication of the available memory device test resources to the requestor.

In another aspect, the present disclosure relates to a test rack comprising: a first memory device test resource comprising a first processing device, wherein the first processing device is configured to facilitate performance of a test of a memory device of a memory subsystem coupled to the first memory device test resource; and a second memory device test resource comprising a second processing device, wherein the second processing device is configured to facilitate execution of the test at the memory device of the memory subsystem coupled to the second memory device test resource in response to the first processing device of the first memory device test resource being unavailable to facilitate execution of the test.

Drawings

The present disclosure will be understood more fully from the detailed description provided below and from the accompanying drawings of various embodiments of the disclosure.

FIG. 1 illustrates an example computing system including a memory subsystem in accordance with some embodiments of the present disclosure.

FIG. 2 is a test platform for performing testing of memory devices according to some embodiments of the present disclosure.

FIG. 3 is an example memory device test resource of a memory device test rack according to some embodiments of the present disclosure.

FIG. 4 is an example connection of a memory subsystem to memory device test resources according to some embodiments of the present disclosure.

FIG. 5 is a flow diagram of an example method of a smart memory device testing resources, in accordance with some embodiments of the present disclosure.

FIG. 6 is a flow diagram of an example method of a memory subsystem interfacing with smart memory device test resources in accordance with some embodiments of the present disclosure.

FIG. 7 is a flow diagram of an example method of a resource allocator of each processing device operatively coupled to test resources of a test rack in accordance with some embodiments of the present disclosure.

FIG. 8 is a block diagram of an example computer system in which embodiments of the present disclosure may operate.

Detailed Description

Aspects of the present disclosure relate to a smart memory device test resource. The memory subsystem may be a memory device, a memory module, or a mixture of memory devices and memory modules. Examples of memory devices and memory modules are described below in conjunction with FIG. 1. In general, a host system may utilize a memory subsystem that includes one or more components (e.g., memory devices) that store data. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

Memory devices used in a memory subsystem may be tested before use in the memory subsystem. In a conventional testing process, the memory device may be placed in a chamber (e.g., an oven) where the memory device is tested under various temperature conditions. For example, one chamber may be used at a time to test multiple memory devices at a particular temperature. The test procedure may indicate various operations performed on the memory device at a particular temperature. These operations include, but are not limited to, read operations, write operations, and/or erase operations. The performance and behavior of the memory device can be observed while the testing process is being performed. For example, performance characteristics (e.g., read or write latency) and reliability of data stored on a memory device may be measured and recorded during and after a test procedure. However, because the chamber can only place the memory device at a single temperature at any particular time, testing the memory device at many different temperatures may require a significant amount of time because the testing process needs to be performed for each target test temperature. In addition, the chamber can only perform a single test procedure at a time. Thus, if the testing process of the memory device to be tested has many different conditions, performing different tests on the memory device under different operating conditions (e.g., different temperatures) may require a significant amount of time.

In some conventional memory device test systems, a memory device may be tested using a test component that includes a temperature control component. The temperature control component is used to subject the memory device to a particular temperature condition. In some test components, only the temperature control component is included, and during memory device testing, the memory device is not affected by any other conditions. A plurality of test elements may be contained in a test rack, wherein each test element of the test rack is coupled to a local test module. The local test module may facilitate testing of each memory subsystem of a test assembly coupled to the test rack. For example, the local test module causes various operations to be performed on the memory device at a plurality of test components under one or more temperature conditions. Because the local test modules facilitate testing each memory subsystem of a test assembly coupled to the test rack, the entire test rack is unusable when a single local test module is serviced or fails.

In some cases, each test rack may contain hundreds of test components. The local test module may maintain a record of a plurality of test components available for memory device testing. Because a record of a test component may contain hundreds of entries (i.e., one entry for each test component), the local test module may use significant memory resources to maintain the record. The local test module may reference a record of available test components in response to each request for memory device testing at the memory rack. Each reference recorded may increase the latency of the test process at the test rack, thereby increasing the latency of the overall test system.

Aspects of the present disclosure address the above and other deficiencies by providing smart memory device test resources. The distributed test platform may include a plurality of memory device test racks. Each test rack may include a plurality of test resources, where each test resource includes a processing device dedicated to facilitating testing of the memory devices at the test resource. The processing device may facilitate testing of memory devices included in a memory subsystem coupled to the memory device test resources. Each test resource further includes one or more test condition components, one or more test resource monitoring components, and a memory subsystem interface port. A memory subsystem containing a memory device to be tested may be coupled to a test resource by interfacing with a memory subsystem interface port. In response to detecting that the memory subsystem is coupled to the test resource, the processing device of the test resource may transmit a test instruction to the memory subsystem, the test instruction including one or more operations to be performed at the memory device. A memory subsystem controller of the memory subsystem may cause the one or more operations to be performed at the memory device. The memory subsystem controller may generate a set of test results for each operation performed at the memory device. After performing the operation at the memory subsystem, the memory subsystem controller transmits the set of test results to the processing device of the memory device test resource.

Each test resource contains a test condition component. The test condition component may include at least one of a temperature controller or a voltage controller. The temperature controller is configured to control a temperature of the memory device during testing. The voltage controller is configured to control a voltage of a power supply signal provided to the memory subsystem during testing. The processing device of the test resource may cause one or more conditions to occur at the test resource. For example, at least one of the temperature controller or the voltage controller may cause the first condition to occur before initiating the test at the memory device. During testing of the memory device, the temperature controller and/or the voltage controller may cause a second condition to occur. In response to detecting that the second condition has occurred, the memory subsystem controller may generate a second set of test results, where the second set of test results relates to performance of operations performed at the memory device operating at the second condition.

Advantages of the present disclosure include, but are not limited to, a reduction in the amount of time a test platform uses to perform testing of a memory device. Because many different tests may be performed at the test platform to test many different conditions (e.g., different temperatures, voltages of different power supply signals, etc.) during the performance of many different sequences of operations, the testing of the memory device may be considered more stable because the reliability and performance of the memory device may be tested by performing many different and parallel tests. Furthermore, because the processing device of each test resource facilitates testing of the memory device, one or more other test resources may be used to test the memory device when a particular test resource or a portion of the test resources are unavailable (e.g., for maintenance, etc.). Further, a record of available test resources is not maintained for each test resource of the test rack, and thus the record is not referenced in response to each request to test the memory device at the test resource of the test rack. Thus, each test of each memory device may be performed in less time, thereby reducing overall system latency. The reliability of the memory device is also increased because any possible defects can be identified and subsequently resolved when designing or manufacturing the memory device for customer use.

Because each test resource contains a dedicated processing device, the memory device can be tested at a test resource removed from the test board of the test rack. For example, an operator of the test platform may remove the test resources from the test boards of the test rack. The operator may provide power and network connectivity to the test resource (e.g., by connecting the test resource to a computing device). The memory subsystem may be coupled to the test resource in response to the test resource receiving the power supply and the network connection. Testing of the memory devices included in the coupled memory subsystem may be performed when the test resources are disconnected from the test board of the test rack.

FIG. 1 illustrates an example computing system 100 that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such devices.

Memory subsystem 110 may be a memory device, a memory module, or a mixture of memory devices and memory modules. Examples of storage devices include Solid State Drives (SSDs), flash drives, Universal Serial Bus (USB) flash drives, embedded multimedia controller (eMMC) drives, Universal Flash Storage (UFS) drives, Secure Digital (SD) cards, and Hard Disk Drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an aircraft, drone, train, automobile, or other vehicle), an internet of things (IoT) -enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or networked business device), or such computing device including memory and processing devices.

The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, host system 120 is coupled to different types of memory subsystems 110. FIG. 1 shows one example of a host system 120 coupled to one memory subsystem 110. As used herein, "coupled to" or "coupled with … …" generally refers to a connection between components that may be an indirect communicative connection or a direct communicative connection (e.g., without intervening components), whether wired or wireless, including electrical, optical, magnetic, etc. connections.

The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The memory subsystem 110 is used by the host system 120, for example, to write data to the memory subsystem 110 and to read data from the memory subsystem 110.

The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a Universal Serial Bus (USB) interface, a fibre channel, serial attached SCSI (sas), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), and so forth. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. The host system 120 may further utilize an NVM express (NVMe) interface to access components (e.g., the memory device 130) when the memory subsystem 110 is coupled with the host system 120 over a PCIe interface. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. By way of example, FIG. 1 illustrates a memory subsystem 110. In general, host system 120 may access multiple memory subsystems via the same communication connection, multiple separate communication connections, and/or a combination of communication connections.

Memory devices

130, 140 may include different types of non-volatile memory devices and/or any combination of volatile memory devices. Volatile memory devices, such as memory device 140, may be, but are not limited to, Random Access Memory (RAM), such as Dynamic Random Access Memory (DRAM) and Synchronous Dynamic Random Access Memory (SDRAM).

Some examples of non-volatile memory devices, such as memory device 130, include NAND (NAND) type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory devices, which are cross-point arrays of non-volatile memory cells. A non-volatile memory cross-point array may perform bit storage based on changes in body resistance in conjunction with a stackable cross-meshed data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memories can perform in-place write operations in which non-volatile memory cells can be programmed if they have been previously erased. The NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

Each of memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a Single Level Cell (SLC), can store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, as well as an MLC portion, a TLC portion, or a QLC portion of a memory cell. The memory cells of memory device 130 may be grouped into pages, which may refer to logical units of the memory device for storing data. In some types of memory (e.g., NAND), pages may be grouped to form blocks.

Although non-volatile memory devices are described, such as 3D cross-point non-volatile memory cell arrays and NAND-type flash memories (e.g., 2D NAND, 3D NAND), memory device 130 may be based on any other type of non-volatile memory, such as Read Only Memory (ROM), Phase Change Memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), Magnetic Random Access Memory (MRAM), Spin Transfer Torque (STT) -MRAM, conductive bridge ram (cbram), Resistive Random Access Memory (RRAM), oxide-based RRAM (oxram), NOR (NOR) flash memory, Electrically Erasable Programmable Read Only Memory (EEPROM).

Memory subsystem controller 115 (or controller 115 for simplicity) may communicate with memory device 130 to perform operations, such as reading data, writing data, or erasing data at memory device 130, and other such operations. Memory subsystem controller 115 may include hardware such as one or more integrated circuits and/or discrete components, buffer memory, or a combination thereof. The hardware may comprise digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. Memory subsystem controller 115 may be a microcontroller, special purpose logic circuitry (e.g., a Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), etc.), or other suitable processor.

Memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the example shown, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, and so forth. Local memory 119 may also include Read Only Memory (ROM) for storing microcode. Although the example memory subsystem 110 in fig. 1 is shown to contain memory subsystem controller 115, in another embodiment of the present disclosure, memory subsystem 110 does not contain memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

In general, memory subsystem controller 115 may receive commands or operations from host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to memory device 130. Memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and Error Correction Code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., Logical Block Addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with memory device 130. Memory subsystem controller 115 may further include host interface circuitry for communicating with host system 120 via a physical host interface. Host interface circuitry may convert commands received from the host system into command instructions to access memory device 130 and convert responses associated with memory device 130 into information for host system 120.

Memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that may receive an address from memory subsystem controller 115 and decode the address to access memory device 130.

In some embodiments, memory device 130 includes a local media controller 135 used in conjunction with memory subsystem controller 115 to perform operations on one or more memory units of memory device 130. An external controller (e.g., memory subsystem controller 115) may manage memory device 130 externally (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is an original memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed nand (mnand) device.

Memory subsystem 110 includes a test component 113 that performs tests on memory devices (e.g., memory device 130) of subsystem 110. The memory subsystem 110 may be coupled to a memory device test resource of a test rack, such as the memory device test resource 310 of FIG. 3. Each memory device test resource of the test rack may include a processing device dedicated to facilitating testing of the memory device at the memory device test resource. The testing component 113 receives one or more instructions from a processing device testing a resource to perform a test at the memory device 130. The test instructions may include one or more operations to be performed at the memory device 130, such as read operations, write operations, and/or erase operations. The test component 113 causes the one or more operations to be performed at the memory device 130. During the performance of the one or more operations, the test component 113 collects data related to the performance of the one or more operations. The testing component 113 generates a first set of test results based on data collected during the performance of the one or more operations. In some embodiments, testing component 113 detects that one or more conditions of memory subsystem 110 have changed during performance of the one or more operations at memory device 130. For example, during performance of the one or more operations, the temperature of the memory subsystem 110 may be increased from a first temperature to a second temperature. In some embodiments, the test condition component of the test resource may change the one or more conditions of the memory subsystem 110. In such embodiments, the test component 113 generates a second set of test results based on data collected during performance of the one or more operations performed under the second condition. After the test component 113 generates the first set of test results and/or the second test results, the test component 113 transmits each set of test results to the processing device that tests the resource.

FIG. 2 illustrates a test platform 200 for performing testing of memory devices according to some embodiments of the present disclosure. The test platform 200 may include one or

more test racks

210A, 210B, and 210N. Each of the

test racks

210A, 210B, and 210N (referred to as test racks 210) may include a plurality of test boards 212, where each test board 212 includes one or more test resources 214 (i.e., test sockets). Test platform 200 may include any number of racks 210, test boards 212, or test resources 214. As shown, the test board 212 may include one or more test resources 214. Although three test resources 214 are shown, test board 212 may include any number of test resources 214. Each test resource 214 may include a memory subsystem that has been coupled to the respective test resource 214.

One or more tests may be performed on memory devices of a memory subsystem that are already coupled to test resources 214. Each test resource 214 may include a separate processing device dedicated to facilitating memory device testing. For example, each test resource 214 may have a separate processing device, rather than each rack 210 and even each test board 212 sharing a processing device. The processing device may receive instructions to be executed when performing the test. The instructions may include one or more operations to be performed at a memory device of the memory subsystem. The instructions may also include one or more conditions to be applied to the memory subsystem during testing.

In some embodiments, the test resources 214 may be removed from the test board 212, and testing of the memory devices may be performed at the removed test resources 214 separate from the test rack 210. Test board 212 and test resources 214 may include a locking mechanism configured to secure test resources 214 to test board 212. The first component of the locking mechanism may be disposed on an external portion of the test resource 214. A second component of the locking mechanism may be included at the test plate 212. The test resource 214 may be secured to the test board 212 in response to the first component and the second component of the locking mechanism engaging. Similarly, the test resources 214 may be removed from the test board 212 in response to the first component of the locking mechanism separating from the second component.

Because the test resources 214 include dedicated processing devices for facilitating memory device testing, testing of the memory devices of the memory subsystem may be performed even when the test resources 214 are removed from the test board 212 and test rack 210. For example, the test resources 214, once removed from the test board 212, may be connected to a power supply and a network connection that is separate from the test board 212 and the test rack 210 (e.g., a separate computing device). In response to the test resource 214 being connected to a power supply and network connection, the processing device of the test resource 214 may facilitate testing of the memory devices coupled to the memory subsystem from which the test resource 214 was removed.

The resource allocator component 222 may receive (e.g., from a user) instructions that include a series of one or more operations and/or conditions of a test to be performed for a memory device of a memory subsystem. The resource allocator component 222 may determine the particular test resources 214 on the different test racks 210 that are available to perform the tests. For example, the resource allocator component 222 may query each processing device of each test resource 214 of each test rack 210 to determine the particular test resource 214 on the different test racks 210 that are available to perform the test. In some embodiments, the resource allocator component 222 may be provided by a server 220 connected to each processing device of the test resource 214. In some embodiments, server 220 is a computing device or system coupled to each processing device of each test resource 214 over a network.

In response to the memory subsystem being coupled to a particular test resource 214, resource allocator component 222 may transmit the received instructions to the processing device of the particular test resource 214. In some embodiments, resource allocator component 222 may transmit the received instructions to the processing device prior to the memory subsystem being coupled to test resource 214. After the test of the memory devices of the memory subsystem is performed, the processing device of the test resources 214 can transmit data associated with the test results to the resource allocator component 222 for transmission and/or presentation to the requesting user. The data associated with the test results may include data associated with performance of an operation at a memory device of the memory subsystem. In some embodiments, the data associated with the test results may further include data associated with one or more conditions of the test resources 214 during test execution.

In some examples, the processing device of the test resource 212 cannot be used to facilitate testing at the test resource 214. In some embodiments, the processing device of another test resource 214 may be used to facilitate testing. For example, the processing device of the first test resource 214 cannot be used to facilitate testing of the memory device. A second test resource 214 may be identified, where the second test resource 214 includes a processing device that may be used to facilitate testing of the memory device. The memory devices of the memory subsystem may be tested at the second test resource 214 until the processing devices of the first test resource 214 are available to facilitate the testing.

FIG. 3 is a memory device test resource 310 of a memory device test rack according to some embodiments of the present disclosure. For example, the memory device test resources 310 may be one implementation of any of the memory device test resources 214 shown in FIG. 2. The test resources 310 may include a dedicated processing device 312 for facilitating testing at the test resources 310, one or more test condition components 314, one or more test resource monitoring components 316, and a memory subsystem interface port 318 (referred to herein as port 318).

As previously described, the processing device 312 may facilitate testing of the memory devices 324 of the memory subsystem 320 coupled to the test resources 310. The processing device 312 may receive one or more test instructions to be executed when performing testing of the memory device 324. The one or more test instructions may include one or more operations to be performed at the memory device 324. In some embodiments, the one or more test instructions may further include one or more conditions to be applied to the memory subsystem 320 during test execution.

Memory subsystem 320 may be coupled to test resources 310 by interfacing with port 318. The port 318 may include a first set of one or more serial input/output (IO) pins configured to couple to corresponding serial IO sockets of the memory subsystem 320. The port 318 may further include a second set of one or more IO pins configured to couple to corresponding IO sockets of the memory subsystem 320. Additional details regarding port 318 are further described with respect to fig. 4.

In response to detecting that memory subsystem 320 has been coupled to port 318, processing device 312 may provide a power supply signal to memory subsystem 320 via port 318 under a first voltage condition. In some embodiments, the power signal may include power. The processing device 312 may further transmit one or more test instructions, including one or more operations to be performed at the memory device 324, to the memory subsystem 320 via the port 318.

In some embodiments, processing device 312 may cause memory subsystem 320 to initiate a reboot process before performing the test at memory device 324. In such embodiments, the processing device may transmit a signal to the memory subsystem controller 322 via the port 318 instructing the memory subsystem controller 322 to initiate a reboot process. In response to receiving the signal, memory subsystem controller 322 may initiate a reboot process. Memory subsystem controller 322 may initiate the test after initiating the reboot process. In other or similar embodiments, processing device 312 does not transmit a signal to memory subsystem controller 322 to initiate the reboot process, but may transmit a signal to memory subsystem controller 322 via port 318 instructing memory subsystem controller 322 to initiate a test at memory device 324. The memory subsystem controller 322 may initiate a test at the memory device 324 in response to receiving the signal from the processing device 312 via the port 318.

Prior to initiating testing at the memory device 324, the processing device 312 may apply one or more conditions of the test resources 310 to the memory subsystem 320. In some embodiments, the processing device 312 may apply the one or more test conditions to the memory subsystem 320 according to the one or more test instructions received from a resource allocator (e.g., resource allocator component 222 of fig. 2). The test condition component 314 may generate the one or more test conditions. In some other embodiments, the test conditions component 314 may include at least one of a temperature controller or a voltage controller. In some embodiments, the temperature controller may include one or more fans configured to cool ambient air surrounding the memory subsystem embedded within the test resources. In other or similar embodiments, the temperature controller may be a dual Peltier device (e.g., two Peltier devices) that utilizes the Peltier effect to exert a heating or cooling effect on a surface of the dual Peltier device coupled to the memory subsystem. In another example, a voltage condition may be applied to memory subsystem 320 by a voltage controller. In some embodiments, the voltage controller may include one or more power supplies configured to provide different voltages to the memory subsystem 320 via the port 318.

In some embodiments, the one or more test instructions may include a first condition to be applied to the memory subsystem during test execution. The first condition may be generated by the test condition component 314 before or during execution of a test at the memory device 324A. In some embodiments, the one or more test instructions may include at least a second condition to be applied to memory subsystem 320 during test execution at memory device 324. The test condition component 314 can change the first condition to a second condition during testing of the memory device 324.

The test resource monitoring component 316 may monitor one or more conditions within the test resources 310. In some embodiments, the test resource monitoring component 316 may monitor the conditions generated by the test conditions component 314. For example, the temperature monitoring component may measure a temperature of the test resource 310, where the temperature is generated by a temperature controller of the test resource 310. The test resource monitoring component 316 may include at least one of: a temperature monitoring component configured to monitor a temperature of the test resource 310, a voltage monitoring component configured to monitor a voltage of a power supply signal provided to the memory subsystem 320 via the port 318, a current monitoring component configured to monitor a current of a power supply signal provided to the memory subsystem 320 via the port 318, or a humidity monitoring component configured to monitor a humidity of the test resource 310.

As previously described, memory subsystem controller 322 may receive one or more test instructions from processing device 312 that include one or more operations to be performed at memory device 324. In response to receiving an instruction from processing device 312 to initiate a test at memory device 324, memory subsystem controller 322 may cause one or more operations of the received test instruction to be performed at memory device 324. Memory subsystem controller 322 may generate one or more sets of test results associated with the performance of the one or more operations at memory device 324. According to the previously described embodiments, memory subsystem controller 322 may generate a first set of test results.

In some embodiments, memory subsystem controller 322 may generate at least a second set of test results. While performing the one or more operations at the memory device 324, the memory subsystem controller 322 may detect a change from a first condition to a second condition, where the test condition component 314 changes the first condition to the second condition according to the previously described embodiments. In some embodiments, memory subsystem controller 322 may detect the change in response to receiving a signal from processing device 312. In other or similar embodiments, memory subsystem controller 322 may detect the change in response to receiving a signal from a sensor of memory subsystem 320 that the condition of memory subsystem 320 has changed from the first condition to the second condition. In response to detecting that the first condition becomes the second condition, memory subsystem controller 322 may generate a second set of test results. The second set of test results may correspond to execution of one or more operations of the test instruction under the second condition.

In response to completing the test at memory device 324, memory subsystem controller 322 may transmit one or more sets of test results to processing device 312. In response to receiving the one or more sets of test results, processing device 312 may transmit each set of test results to another computing device, such as server 220 of FIG. 2, for transmission and/or presentation to a user requesting a memory device 324 test.

In some embodiments, the processing device 312 may include a memory component (not shown) configured to store data associated with one or more conditions of the test resources 310 during execution of the test at the memory device 324. In such embodiments, the processing device 312 may transmit data associated with the one or more conditions of the test resource 310 during execution of the test at the memory device 324 along with each set of test results.

In some embodiments, the test resources 310 may be removed from the test rack 210. The test resource 310 may include one or more components of a fastening mechanism disposed outside of the subject test resource, such as fastening component 330. The fastening component 330 may be a first component of a fastening mechanism configured to engage with a second component of the fastening mechanism. In some embodiments, the second component of the fastening mechanism may be contained in the test plate of the test rack 210. When the fastening component 330 engages with the second component of the fastening mechanism, the test resource 310 may be secured to a test plate of the test rack 210. Similarly, when the fastening component 330 is separated from the second component of the fastening mechanism, the test resource 310 may be removed from the test plate of the test rack 210. The test resources 310 may be connected to a power supply and a network connection that is separate from the test rack 210. For example, an operator of the test rack 210 may separate the fastening component 330 of the test resource 310 from the second component of the fastening mechanism of the test board and connect the test resource 310 to a power source and a network connection (e.g., a separate computing device) separate from the test rack 210. In accordance with previously disclosed embodiments, the processing device 312 may facilitate testing of the memory device 324 in response to the test resources 310 being connected to a power supply and a network connection separate from the test rack 210.

FIG. 4 is an example connection of memory device test resources 310 to a memory subsystem 320, according to some embodiments of the present disclosure. The port 318 may be configured to transmit a power signal to the memory subsystem 320. The port 318 may be further configured to transmit instructions and data to the memory subsystem 320 and/or receive instructions and data from the memory subsystem 320.

The port 318 may include a first set of pins 412 configured to couple to a first set of sockets 416 of the memory subsystem 320. Each of the first set of pins 412 may be configured to transmit a power supply signal (e.g., power) to the memory subsystem 320. The first set of sockets 416 may be configured to receive power signals transmitted via the port 318 from the test resource 310. In some embodiments, each of the first set of pins 412 may be a non-serial input/output (IO) pin. In other or similar embodiments, each of the first set of pins 412 may be a pin of a high speed serial interface. For example, each of the first set of pins 412 may be configured to facilitate a peripheral component interconnect express (PCIe) protocol and/or a serial AT attachment (SATA) protocol.

In some embodiments, memory subsystem 320 may be enclosed in a protective enclosure 420. The boot 420 may have an opening 422 for exposing the first set of sockets 416 to the first set of pins 412 of the test resource 310. The first set of pins 412 may be configured to connect to the first set of sockets 416 via openings 422 of the boot 420.

The port 318 may further include a second set of pins 414. Each of the second set of pins 414 may be configured to transfer instructions and data between the processing device 312 and the memory subsystem 320. In some embodiments, each of the second set of pins 414 may be a serial IO pin. In other or similar embodiments, each of the second set of pins 414 may be pins of a low speed serial interface. For example, each of the second set of pins 414 may be configured to facilitate a universal asynchronous receiver/transmitter (UART) protocol, a System Management Bus (SMB) protocol, or a serial line debug (SWD protocol). Some of memory subsystems 320 may include a second set of sockets 418. In some embodiments, each of second set of sockets 418 may be a serial IO socket. The second set of sockets 418 may be configured to receive data from the processing device 312 and/or transmit data to the processing device 312. In some embodiments, openings 422 of boot 420 may expose second set of sockets 418 to second set of pins 414 of port 318. Second set of pins 414 may be configured to couple to second set of sockets 418 via openings 422 of protective cover 420.

Fig. 5 is a flow diagram of an example method 500 of a smart memory device test rack, according to some embodiments of the present disclosure. Method 500 may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, method 500 is performed by a processing device testing a resource (e.g., processing device 312 of FIG. 3). Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Thus, the illustrated embodiments are to be understood as examples only, and the processes shown may be performed in a different order, and some processes may be performed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Thus, not all processes are required in every embodiment. Other process flows are possible.

At operation 510, the processing device 312 detects that the memory subsystem has engaged the memory device test resources. For example, the memory subsystem may be memory subsystem 320 of FIG. 3. The memory subsystem 320 may interface with the test resources 310 via a memory subsystem interface port (e.g., port 318). The port 318 may include one or more non-serial input/output (IO) pins, such as the first set of pins 412 of fig. 4, configured to couple to a corresponding socket of the memory subsystem 320, such as the first set of sockets 416. Each of the first set of pins 412 may be configured to transfer power from the test resource 310 to the memory subsystem 320 interfaced with the test resource 310. The port 318 may further include one or more serial IO pins, such as the second set of pins 414, configured to couple to corresponding serial IO sockets of the memory subsystem 320, such as the second set of sockets 418. The one or more serial IO pins in the second set of pins 414 may be configured to transmit data and instructions between the processing device 312 and the memory subsystem 320 interfaced with the test resource 310.

In some embodiments, memory subsystem 320 may be enclosed within a protective enclosure, such as memory subsystem protective enclosure 420. The protective cover 420 may include openings 422 configured to expose the first set of sockets 416 and the second set of sockets 418 of the memory subsystem 320 to the first set of pins 412 and the second set of pins 414 of the port 318. First set of pins 412 and second set of pins 414 may be configured to couple to first set of sockets 416 and second set of sockets 418 via openings 422 of protective cover 420.

At operation 520, the processing device 312 identifies a test to be performed for a memory device (e.g., memory device 324) of the memory subsystem 320, where the test includes one or more test instructions to be executed when performing the test. Memory subsystem 320 may include a memory subsystem controller, such as memory subsystem controller 322. Memory subsystem controller 322 may be responsible for performing testing of memory device 324. In some embodiments, the one or more test instructions include one or more operations to be performed at the memory device 324, such as a read operation, a write operation, and/or an erase operation. The test instructions may further include conditions under which the test is performed, referred to as test conditions. For example, the test instructions may include one or more temperature conditions and/or one or more voltage conditions to be applied to memory subsystem 320 during test execution. Each test condition may be generated by a test condition component 314 of the test resource 310. For example, memory subsystem 320 may be subjected to temperature conditions generated by a temperature controller. The test conditions may be monitored by one or more test resource monitoring components of the test resources 310, such as the test resource monitoring component 316. For example, the temperature monitoring component may monitor the temperature of the memory subsystem 320 during testing. In another example, the voltage monitoring component may monitor the voltage provided to the memory subsystem 320 via the port 318. The test resource monitoring component 316 may also include a current monitoring component configured to monitor current provided to the memory subsystem 320 via the port 318. In other or similar embodiments, test resource monitoring component 316 may include a humidity monitoring component configured to monitor the humidity of the ambient air surrounding memory subsystem 320 during testing.

At operation 530, the processing device 312 transmits the one or more test instructions to the memory subsystem 320 via the port 318, wherein the testing is performed by executing the one or more test instructions at the memory subsystem 320. Memory subsystem controller 322 of memory subsystem 320 may receive the one or more test instructions and cause one or more operations of the test to be performed at memory device 324. In some embodiments, processing device 312 causes operations to be performed at memory device 324 by transmitting a signal to memory subsystem controller 322 via port 318 that initiates performance of operations at memory device 324. In other or similar embodiments, processing device 312 causes operations to be performed at memory device 324 by transmitting a signal to cause memory subsystem controller 322 to initiate a reboot process. The one or more operations may be performed in response to the memory subsystem 320 initiating a reboot process.

Processing device 312 may receive, via port 318, one or more sets of test results associated with performance of the one or more operations at memory device 324. Each set of test results may include at least one of a performance characteristic or behavior of memory device 324 when performing the test process. Performance characteristics and/or behavior of memory device 324 may be observed by memory subsystem controller 322 while the one or more operations are being performed. In response to receiving the one or more sets of test results, processing device 312 may transmit the test results to a server associated with the client requesting the memory device test, such as server 220 of FIG. 2. In some embodiments, the processing device 312 may transmit data associated with one or more conditions monitored by the test resource monitoring component 316 of the first test resource 310A, as well as the test results. For example, processing device 312 may transmit data associated with at least one of: the temperature of the test resource 310, the humidity of the test resource 310, the voltage of the power supply signal provided to the memory subsystem 320, or the current of the power supply signal provided to the memory subsystem 320 during testing of the memory device 324.

FIG. 6 is a flow diagram of an example method 600 of a memory subsystem interfacing with memory device test resources of a smart memory device test rack in accordance with some embodiments of the present disclosure. The method 600 may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by the testing component 113 of FIG. 1. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Thus, the illustrated embodiments are to be understood as examples only, and the processes shown may be performed in a different order, and some processes may be performed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Thus, not all processes are required in every embodiment. Other process flows are possible.

At operation 610, the testing component 113 detects that a memory subsystem (e.g., memory subsystem 320 of FIG. 3) has engaged with a memory device testing resource (e.g., testing resource 310). According to previously described embodiments, the memory subsystem 320 may interface with the test resources 310 via a memory subsystem interface port (e.g., port 318).

At operation 620, the testing component 113 receives, via the port 318, one or more test instructions for a test to be performed on a memory device (e.g., memory device 324) of the memory subsystem 320 from a processing device (e.g., processing device 312) of the test resource 310. In accordance with previously disclosed embodiments, the one or more test instructions may include an operation to be performed at memory device 324. Memory subsystem 320 may cause each operation of the one or more test instructions to be performed at memory device 324. In some embodiments, memory subsystem 320 may cause each operation to be performed under various test conditions, temperature conditions, or voltage conditions. According to the previously described embodiments, the temperature conditions and/or voltage conditions may be applied to the memory subsystem 320 by a test condition component (e.g., test condition component 314) of the test resources 310.

At operation 630, the testing component 113 performs testing of the memory device 324 by executing the one or more received test instructions. As previously described, a memory subsystem controller (e.g., memory subsystem controller 322) may perform testing by causing the one or more operations of the received test instructions to be performed. In some embodiments, memory subsystem controller 322 may perform a test at memory device 324 in response to receiving a signal from processing device 312 via port 318 that initiates a test of memory device 324. In other or similar embodiments, memory subsystem controller 322 may perform the test in response to initiating a reboot process. According to previously described embodiments, memory subsystem controller 322 may initiate a reboot process in response to receiving a signal from processing device 312.

At operation 640, the testing component 113 generates a first set of test results during test execution. As previously described, the one or more test instructions of the test may include the conditions under which the memory subsystem 320 performed the test of the memory device. In some embodiments, the conditions may include at least a first test condition, such as a first temperature condition and/or a first voltage condition. The first set of test results may correspond to performance of a test under a first test condition. Memory subsystem controller 322 may generate a second set of test results corresponding to the execution of one or more operations of the test instructions under a second condition.

At operation 650, the testing component 113 transmits the first set of test results to the processing device 312 via the port 318. In some embodiments, processing device 312 further transmits a second set of test results generated based on the performance of the one or more operations under the second condition, in accordance with the previously described embodiments. In accordance with the previously described embodiments, in response to receiving the first set of test results and/or the second set of test results, processing device 312 may transmit the received test results to a server, such as server 220 of fig. 2.

FIG. 7 is a flow diagram of an example method 700 of a resource allocator for each processing device operatively coupled to a test plate of a test rack, according to some embodiments of the present disclosure. Method 700 may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, method 700 is performed by resource allocator component 222 of fig. 2. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Thus, the illustrated embodiments are to be understood as examples only, and the processes shown may be performed in a different order, and some processes may be performed in parallel. Additionally, in various embodiments, one or more processes may be omitted. Thus, not all processes are required in every embodiment. Other process flows are possible.

At operation 710, processing logic receives a first request to perform a test for a memory device of a memory subsystem at a memory device test rack. In some embodiments, the memory subsystem may be memory subsystem 320 of FIG. 3 and the memory device may be memory device 324. In some embodiments, the memory device test rack may be any of the test racks 210A, B or C of fig. 2. The test rack 210 may include two or more memory device test resources, such as the test resources 312 of FIG. 3. Each test resource 310 may include a dedicated processing device, such as processing device 312, where processing device 312 is dedicated to facilitating memory device testing at test resource 310. Each test resource 310 may further include a test condition component, such as test condition component 314. In some embodiments, the first request may include one or more operations corresponding to test conditions to be applied to the memory subsystem 320 during testing.

At operation 720, the processing logic transmits a second request to each individual processing device 312 of each test resource 310 to determine the test resources 310 available to perform the test. At operation 730, processing logic receives a response from each individual processing device 312 that includes an indication of whether the test resource 310 is available to perform the test. In some embodiments, the response may include an indication of the test condition component 314 included in the test resource 310. For example, the processing logic may receive a first response from the first processing device 312 of the first test resource 310 indicating that the first test resource 310 is available and that the first test resource 310 includes a temperature controller and a voltage controller. The processing logic may also receive a second response from the second processing device 312 of the second test resource 310 indicating that the second test resource 310 is available and that the second test resource 310 includes a temperature controller.

At operation 740, based on the responses received from each individual processing device, processing logic determines available test resources 310 of the test rack 212 to perform the test. In some embodiments, the available test resources 310 may be further determined based on an indication of whether the available test resources 310 include a test condition component 314 configured to generate the test condition included in the first request. According to a previous example, the first request may include one or more operations corresponding to the voltage of the power supply signal provided by the available test resources 310 to the memory subsystem 320. Processing logic may select an available test resource 310 to test based on an indication that the first test resource 310 includes a first response of the voltage controller.

At operation 750, processing logic transmits an indication of available test resources 310. In response to receiving an indication of available test resources 310, the memory subsystem may be coupled to the available test resources 310 for testing. For example, processing logic may transmit an indication of available test resources 310 to an operator of the test rack 210. In response to receiving the indication, the operator may couple the memory subsystem 320 to the available test resources 310 for testing.

In some embodiments, processing logic may receive one or more operations to be performed during testing of a memory device. The operation may include test conditions generated by the test conditions component 314 of the available test resources 310. In some embodiments, the test conditions may include the temperature of the ambient air surrounding memory subsystem 320 or the voltage of the power supply signal provided to memory subsystem 320. The operations may further include one or more of a read operation, a write operation, or an erase operation performed at the memory device 324 during testing. In response to receiving the one or more operations, processing logic may transmit one or more test instructions including the one or more operations to the processing device 312 allocated to the available test resources 310. In some embodiments, the one or more test instructions may be generated by processing logic. In some embodiments, the one or more test instructions are transmitted to the processing device 312 in response to receiving an indication that the memory subsystem 320 has been coupled to the available test resources 310 by a memory subsystem interface port (e.g., port 318) of the available test resources 310.

Fig. 8 illustrates an example machine of a computer system 800 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 800 may correspond to a host system (e.g., the host system 120 of fig. 1) that includes, is coupled to, or utilizes a memory subsystem (e.g., the memory subsystem 110 of fig. 1), or may be used to perform the operations of a controller (e.g., to execute an operating system to perform operations corresponding to the test component 113 of fig. 1). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The machine may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Additionally, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

Example computer system 800 includes a processing device 802, a main memory 804 (e.g., Read Only Memory (ROM), flash memory, Dynamic Random Access Memory (DRAM), such as synchronous DRAM (sdram) or Rambus DRAM (RDRAM), etc.), a static memory 806 (e.g., flash memory, Static Random Access Memory (SRAM), etc.), and a data storage system 818, which communicate with each other via a bus 830.

The processing device 802 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, Reduced Instruction Set Computing (RISC) microprocessor, Very Long Instruction Word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device 802 may also be one or more special-purpose processing devices such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), network processor, or the like. The processing device 802 is configured to execute instructions 826 for performing the operations and steps discussed herein. The computer system 800 may further include a network interface device 708 that communicates over a network 820.

The data storage system 818 may include a machine-readable storage medium 824 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 826, or software embodying any one or more of the methodologies or functions described herein. The instructions 826 may also reside, completely or at least partially, within the main memory 804 and/or within the processing device 802 during execution thereof by the computer system 800, the main memory 804, and the processing device 802, which also constitute machine-readable storage media. The machine-readable storage media 824, data storage system 818, and/or main memory 804 may correspond to memory subsystem 110 of fig. 1.

In one embodiment, instructions 826 include instructions to implement functionality corresponding to a test component (e.g., test component 113 of FIG. 1). While the machine-readable storage medium 824 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the most effective means used by those skilled in the data processing arts to convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

The present disclosure also relates to apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), Random Access Memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear from the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.

The present disclosure may be provided as a computer program product or software which may include a machine-readable medium having stored thereon instructions which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) -readable storage medium, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, and so forth.

In the foregoing specification, embodiments of the disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A memory device test resource, comprising:

a dedicated processing device of the memory device test resources, the dedicated processing device configured to facilitate testing of memory devices of a memory subsystem coupled to the memory device test resources;

a memory subsystem interface port coupled to the special purpose processing device and configured to couple the memory device test resources to the memory subsystem;

a test condition component coupled to the special purpose processing device and configured to generate a test condition at the memory device test resource;

a test resource monitoring component coupled to the dedicated processing device and configured to monitor one or more conditions at the memory device test resources.

2. The memory device test resource of claim 1, wherein the special purpose processing device is configured to perform operations comprising:

detecting that the memory subsystem has been coupled to the memory device test resource;

identifying a test to be performed with respect to the memory device of the memory subsystem, wherein the test comprises one or more test instructions to be executed when performing the test; and

causing the one or more test instructions to be transmitted to the memory subsystem, wherein the test is performed by executing the one or more test instructions at the memory subsystem.

3. The memory device test resource of claim 2, wherein the special purpose processing device is configured to perform operations further comprising:

a first set of test results of the test performed for the memory device is received from the memory subsystem.

4. The memory device test resource of claim 1, wherein the memory subsystem interface port comprises: a first set of serial input/output (IO) pins configured to be coupled to corresponding serial IO sockets of the memory subsystem; and a second set of IO pins configured to be coupled to corresponding IO sockets of the memory subsystem, and wherein one or more test instructions of a test to be performed at the memory device are transmitted to the memory subsystem via the first set of serial IO pins of the memory subsystem interface port.

5. The memory device test resource of claim 1, wherein the special purpose processing device is configured to perform operations comprising:

cause the test condition component to generate a first test condition to be applied to the memory subsystem based on one or more test instructions of a test to be performed for the memory device; and

receiving, from the test resource monitoring component, data associated with one or more conditions within the memory device test resources, wherein the one or more conditions comprise the first test condition generated by the test condition component.

6. The memory device test resource of claim 5, wherein the special purpose processing device is configured to perform operations comprising:

causing the test condition component to generate a second test condition that is applied to the memory subsystem when the test is performed at the memory device; and

a first set of test results of the test performed for the memory device under the first test condition and a second set of test results of the test performed for the memory device under the second test condition are received from the memory subsystem.

7. The memory device test resource of claim 1, wherein the test condition component comprises at least one of a temperature controller or a voltage controller, and the test resource monitoring component comprises at least one of a temperature monitoring component, a voltage monitoring component, a current monitoring component, or a humidity monitoring component.

8. A system, comprising:

a memory device; and

a processing device operatively coupled to the memory device, the processing device performing operations comprising:

receiving, from a requestor, a first request to perform a test for a memory device of a memory subsystem at a memory device test rack, wherein the memory device test rack comprises a plurality of memory device test resources, each memory device test resource comprising a separate processing device;

transmitting a second request to each separate processing device to determine which memory device test resources of the plurality of memory device test resources are available to perform the test of the memory devices of the memory subsystem;

receiving a response from each individual processing device, the response including an indication of whether each of the plurality of memory device test resources is available to perform the test;

determining available memory device test resources of the memory device test rack to perform the test based on the responses received from each individual processing device; and

transmitting an indication of the available memory device test resources to the requestor.

9. The system of claim 8, wherein the processing device is to perform operations further comprising:

receiving, from the requestor, one or more operations to be performed during the testing of the memory devices of the memory subsystem;

transmitting one or more test instructions comprising the one or more operations to the separate processing device allocated to the available memory device test resource.

10. The system of claim 9, wherein the one or more test instructions are transmitted to the separate processing device in response to receiving an indication that the memory subsystem has been coupled to the available memory device test resources by a memory subsystem interface port of the available memory device test resources.

11. The system of claim 9, wherein the one or more operations correspond to at least one of test conditions generated by a test conditions component of the available memory device test resources during the test or one or more of a read operation, a write operation, or an erase operation performed at the memory device during the test.

12. The system of claim 11, wherein the test condition comprises at least one of a temperature of ambient air surrounding the memory subsystem or a voltage of a power supply signal provided to the memory subsystem by the available memory device test resources.

13. The system of claim 8, wherein the first request to perform the test for the memory device comprises one or more operations corresponding to test conditions to be applied to the memory subsystem during the test, and wherein the available memory device test resources are further determined based on an indication of whether the available memory device test resources comprise a test condition component configured to generate the test conditions during the test.

14. A test rack, comprising:

a first memory device test resource comprising a first processing device, wherein the first processing device is configured to facilitate performance of a test of a memory device of a memory subsystem coupled to the first memory device test resource; and

a second memory device test resource comprising a second processing device, wherein the second processing device is configured to facilitate execution of the test at the memory device of the memory subsystem coupled to the second memory device test resource in response to the first processing device of the first memory device test resource being unavailable to facilitate execution of the test.

15. The test rack of claim 14, wherein the first processing device is to perform operations comprising:

detecting that the memory subsystem has engaged the first memory device test resource;

identifying the test to be performed for the memory device of the memory subsystem, wherein the test comprises one or more test instructions to be executed when performing the test; and

16. The test rack of claim 15, wherein the first processing device is to perform operations comprising:

17. The test rack of claim 15, wherein the first processing device is to perform operations further comprising:

causing a test condition component of the first memory device test resource to generate a first test condition to be applied to the memory subsystem based on the one or more test instructions of the test to be performed for the memory device; and

receiving, from a test resource monitoring component of the first memory device test resource, data associated with one or more conditions within the first memory device test resource, wherein the one or more conditions comprise the first test condition generated by the test condition component.

18. The test rack of claim 17, wherein the test condition component comprises at least one of a temperature controller or a voltage controller, and the test resource monitoring component comprises at least one of a temperature monitoring component, a voltage monitoring component, a current monitoring component, or a humidity monitoring component.

19. The test rack of claim 14, wherein the first processing device is to perform operations comprising:

transmitting a notification to a memory device test resource allocator that the first processing device is unavailable to facilitate performance of the test at the first memory device test resource.

20. The test rack of claim 19, wherein the second processing device is to perform operations comprising:

receiving a request to facilitate performance of the test at the second memory device test resource;

detecting that the memory subsystem has engaged the second memory device test resource;