CN112989440A - Chip, processor driving method and electronic equipment - Google Patents
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Abstract
The application discloses a chip, a processor driving method and electronic equipment, and belongs to the technical field of integrated circuits. The chip comprises a memory, a control module and a processor, wherein the control module is electrically connected with the memory and the processor respectively; the memory is used for storing target data; the control module is used for generating a control signal aiming at the memory after the chip is powered on and reset; reading target data from a memory according to the control signal; generating a first signal according to the target data; transmitting a first signal to a processor; the processor is used for determining whether to start working according to the first signal. The chip, the processor driving method and the electronic device can improve the safety of the chip.
Description
Technical Field
The application belongs to the technical field of integrated circuits, and particularly relates to a chip, a processor driving method and electronic equipment.
Background
A chip is an Integrated Circuit (IC) that is made up of a large number of transistors. An integrated circuit is a miniature electronic device or component, which is a circuit with specific functions and is formed by integrating a certain number of electronic elements, such as resistors, capacitors, transistors, etc., and connecting lines among the elements through a semiconductor process.
In the related art, once the chip is powered on and reset, the internal processor starts to work. After the chip is acquired by an attacker, the chip starts to work as soon as the chip is powered on and resets the internal processor, the processor architecture, the instruction set, the programming model and the like are all public, the attacker can easily analyze the information, then the chip is simulated in a simulation mode, the vulnerability of the chip is further discovered, and the chip is attacked through the vulnerability, for example, configuration information of the chip is tampered, a user code is read and the like, so that the chip is poor in safety.
Disclosure of Invention
An object of the embodiments of the present application is to provide a chip, a processor driving method, and an electronic device, which can solve the problem of poor chip security.
In a first aspect, an embodiment of the present application provides a chip, including: a memory, a control module, and a processor, wherein,
the control module is electrically connected with the memory and the processor respectively;
the memory is used for storing target data;
the control module is used for generating a control signal aiming at the memory after the chip is powered on and reset; reading target data from a memory according to the control signal; generating a first signal according to the target data; transmitting a first signal to a processor;
the processor is used for determining whether to start working according to the first signal.
In some possible implementations of the first aspect of the embodiment of the present application, the control module is specifically configured to:
generating a driving signal for driving the memory to operate, a read enable signal for controlling a read enable of the memory, and a data read signal for reading target data from the memory;
transmitting a driving signal to the memory so that the memory operates under the driving of the driving signal;
transmitting a read enable signal to the memory so that the target data stored by the memory can be read under the control of the read enable signal;
and sending a data reading signal to the memory, and reading the target data from the memory according to the data reading signal.
In some possible implementations of the first aspect of the embodiments of the present application, the target data is stored in a storage area corresponding to a preset address in the memory; the control module is specifically configured to:
generating a preset address;
transmitting a data read signal including a preset address to a memory;
and reading the target data from the storage area according to the preset address.
In some possible implementations of the first aspect of the embodiment of the present application, the control module is specifically configured to:
and carrying out target transformation on the target data to obtain a first signal.
In some possible implementations of the first aspect of the embodiments of the present application, the processor is specifically configured to:
detecting whether the first signal is matched with a preset signal value;
and determining that the processor starts to work under the condition that the first signal is detected to be matched with the preset signal value.
In some possible implementations of the first aspect of embodiments of the present application, the target data includes:
all or part of the configuration information of the chip.
In some possible implementations of the first aspect of the embodiments of the present application, the control module includes: a register; the control module is further configured to:
the configuration information is loaded into the registers.
In some possible implementations of the first aspect of the embodiments of the present application, the control module is further configured to:
detecting whether the register loads the configuration information correctly;
under the condition that the register is detected to be loaded with the configuration information correctly, reading the configuration information from the register;
according to the configuration information, a first signal is generated.
In a second aspect, an embodiment of the present application provides a processor driving method, which is applied to a chip provided in the first aspect of the embodiment of the present application or any possible implementation of the first aspect of the embodiment of the present application, and the processor driving method includes:
after the chip is powered on and reset, generating a control signal aiming at the memory;
reading target data from a memory according to the control signal;
generating a first signal according to the target data;
a first signal is transmitted to the processor to cause the processor to determine whether to begin operation based on the first signal.
In a third aspect, an embodiment of the present application provides an electronic device, including the chip provided in the first aspect of the embodiment of the present application or any possible implementation of the first aspect of the embodiment of the present application.
In an embodiment of the present application, a chip provided in an embodiment of the present application includes a memory, a control module, and a processor. The control module generates a control signal aiming at the memory after the chip is powered on and reset; reading target data from a memory according to the control signal; generating a first signal according to the target data; the first signal is transmitted to a processor. The processor determines whether it is to start operating according to the first signal. Thus, the processor starts to work only after the processor receives the first signal and determines to start to work according to the first signal, and the processor does not start to work after the chip is powered on and reset. And because the first signal is generated by the control module according to the target data in the memory, an attacker needs to acquire the target data of the memory and analyze the hardware circuit at the same time to possibly simulate the first signal, but because the target data is pre-stored in the memory of the chip, the attacker is difficult to directly acquire the target data in the memory and analyze the hardware circuit, so that even if the attacker acquires the chip, the attacker is difficult to simulate the first signal, the chip is difficult to simulate in a simulation mode, the vulnerability of the chip is difficult to find, and the security of the chip can be improved.
Drawings
Fig. 1 is a schematic structural diagram of a chip provided in an embodiment of the present application;
fig. 2 is a schematic diagram of a process for generating a first signal according to an embodiment of the present application;
FIG. 3 is a schematic diagram of another structure of a chip provided in an embodiment of the present application;
fig. 4 is a schematic diagram of another process for generating a first signal according to an embodiment of the present application;
fig. 5 is a flowchart illustrating a processor driving method according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments that can be derived by one of ordinary skill in the art from the embodiments given herein are intended to be within the scope of the present disclosure.
The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that embodiments of the application may be practiced in sequences other than those illustrated or described herein, and that the terms "first," "second," and the like are generally used herein in a generic sense and do not limit the number of terms, e.g., the first term can be one or more than one. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.
The chip, the processor driving method, and the electronic device provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings through specific embodiments and application scenarios thereof.
Fig. 1 is a schematic structural diagram of a chip provided in an embodiment of the present application. The chip 100 may include: a control module 101, a processor 102, and a memory 103, wherein,
the control module 101 is electrically connected with the memory 103 and the processor 102 respectively;
the memory 103 is used for storing target data;
the control module 101 is configured to generate a control signal for the memory 103 after power-on reset of the chip; reading target data from the memory 103 according to the control signal; generating a first signal according to the target data; transmitting a first signal to the processor 102;
the processor 102 is configured to determine whether to start operating according to the first signal.
In an embodiment of the present application, a chip provided in an embodiment of the present application includes a memory, a control module, and a processor. The control module generates a control signal aiming at the memory after the chip is powered on and reset; reading target data from a memory according to the control signal; generating a first signal according to the target data; the first signal is transmitted to a processor. The processor determines whether it is to start operating according to the first signal. Thus, the processor starts to work only after the processor receives the first signal and determines to start to work according to the first signal, and the processor does not start to work after the chip is powered on and reset. And because the first signal is generated by the control module according to the target data in the memory, an attacker needs to acquire the target data of the memory and analyze the hardware circuit at the same time to possibly simulate the first signal, but because the target data is pre-stored in the memory of the chip, the attacker is difficult to acquire the target data in the memory and analyze the hardware circuit, so that even if the attacker acquires the chip, the attacker is difficult to simulate the first signal, the chip is difficult to simulate in a simulation mode, the vulnerability of the chip is difficult to find, and the safety of the chip can be improved.
In some possible implementations of the embodiments of the present application, the memory storing the target data in the embodiments of the present application may be a nonvolatile memory or a volatile memory. Examples of the nonvolatile memory include a charge Erasable Programmable read only memory (EEPROM), a Flash memory (Flash memory), and the like. Examples of volatile Memory include Random Access Memory (RAM).
Preferably, the memory in the embodiment of the present application is a nonvolatile memory. Because data in the EEPROM and the Flash of the nonvolatile memory are difficult to obtain, even if an attacker obtains the chip, the attacker can not obtain the data in the nonvolatile memory and further cannot obtain target data, the first signal is difficult to simulate, the chip is difficult to simulate in a simulation mode, the loopholes of the chip are difficult to find, and the safety of the chip can be improved.
In some possible implementations of the embodiment of the present application, the control module 101 in the embodiment of the present application may be specifically configured to:
generating a driving signal for driving the memory 103 to operate, a read enable signal for controlling a read enable of the memory 103, and a data read signal for reading target data from the memory 103;
transmitting a driving signal to the memory 103 to make the memory 103 operate under the driving of the driving signal;
transmitting a read enable signal to the memory 103 so that the target data stored in the memory 103 can be read under the control of the read enable signal by the memory 103;
sends a data read signal to the memory 103, and reads target data from the memory 103 in accordance with the data read signal.
Specifically, after the power-on reset of the chip, the control module 101 generates a driving signal for driving the memory 103 to operate, a read enable signal for controlling the read enable of the memory 103, and a data read signal for reading target data from the memory 103. The control module 101 transmits the driving signal, the read enable signal, and the data read signal to the memory 103. The memory 103 starts to operate after receiving the driving signal, and then starts a data reading function according to the read enable signal, so that the control module 101 can read data from the memory 103, and then the control module 101 reads target data from the memory 103 according to the data reading signal.
In some possible implementations of the embodiments of the present application, the target data may be stored in a storage area corresponding to the preset address in the memory. Accordingly, the control module 101 may be specifically configured to: generating a preset address; transmitting a data read signal including a preset address to a memory; and reading the target data from the storage area according to the preset address.
In some possible implementations of the embodiments of the present application, the preset address may be a plurality of addresses. Furthermore, the target data may be acquired from a plurality of addresses, that is, the target data in the embodiment of the present application is a combination of data stored in storage areas corresponding to the plurality of addresses.
In the embodiment of the present application, since the target data is formed by combining data stored in the storage areas corresponding to the plurality of addresses, even if an attacker acquires the chip, the attacker may not know which data the target data is formed by combining, and thus may hardly acquire the target data, and may not generate the first signal by simulation, and thus may not simulate the chip in a simulation manner, and may not find a bug of the chip, so that the security of the chip may be improved.
In some possible implementations of the embodiments of the present application, the control module 101 may be specifically configured to:
and carrying out target transformation on the target data to obtain a first signal.
Specifically, the control module may include: one or more of the logic and gate circuit, the logic or gate circuit, the logic not gate circuit, the accumulation circuit and the like performs target transformation on target data through the logic and gate circuit, the logic or gate circuit, the logic not gate circuit, the accumulation circuit and the like to obtain a first signal.
In this embodiment, the processor 102 may specifically be configured to:
detecting whether the first signal is matched with a preset signal value;
in the case where it is detected that the first signal matches a preset signal value, it is determined that it is starting to operate.
Illustratively, assuming the preset signal is 10101001, the processor will only begin operation if and only if the first signal generated is also 10101001. When the first signal is not 10101001 or the processor does not receive the first signal, the processor is inactive.
In some possible implementations of embodiments of the present application, the control module 101 may include two parts: SCTRL1 and SCTRL 2. After the chip is reset, the SCTRL1 generates a control signal for the memory 103 and a preset address, the control signal including a driving signal for driving the memory 103 to operate, a read enable signal for controlling a read enable of the memory 103, and a data read signal including the preset address for reading target data from the memory 103. After the driving signal, the read enable signal and the data read signal enter the memory 103, the memory 103 is started to work, the read enable of the memory 103 is controlled, a hardware code (code) of a preset address is read, and the read code is transmitted to the SCTRL 2. SCTRL2 performs a target transformation on the code to generate a set of activation signals that control whether processor 102 is operating.
Exemplarily, as shown in fig. 2. Fig. 2 is a schematic diagram of a first process for generating a first signal according to an embodiment of the present disclosure. After the power-on reset of the chip, the SCTRL1 generates a driving signal (drive, d) for driving the memory 103 to operate, a read enable signal (read enable, re) for controlling a read enable of the memory 103, and a data read signal (read data, rd) including a preset address for reading target data from the memory 103. Wherein, the preset address included in rd is Add [3 ]. After the driving signal d and the read enable signal re enter the memory 103, the memory 103 is started to work and the read enable of the memory 103 is controlled, and the SCTRL1 reads data from a storage area corresponding to the Add [3] in the memory 103 according to the preset address Add [3] included in the data read signal rd. SCTRL1 reads code 11000001 and transfers 11000001 to SCTRL 2. 11000001 performs a target conversion in SCTRL2 to a first signal "00100001". SCTRL2 transmits 00100001 to processor 102 and processor 102 will begin operation upon receiving 00100001. When 00100001 is not received or 00100001 is not received, processor 102 is not active.
It is understood that the code in the embodiment of the present application is the above target data. codes are preset and each address has a corresponding code, and the corresponding codes are read and output by giving the preset addresses through the SCTRL 1.
In some possible implementations of the embodiments of the present application, the target data in the embodiments of the present application may include: all or part of the configuration information of the chip.
In the embodiment of the application, the first signal can be generated through all or part of configuration information of the chip, and then the processor is driven to work. Because the target data includes all or part of configuration information of the chip, the configuration information of the chip is not needed or only a small amount of configuration information of the chip is needed in the bootstrap program, even if the bootstrap program of the chip is acquired by an attacker, the attacker cannot acquire all or part of the configuration information of the chip, and further the chip is difficult to be simulated in a simulation mode, so that the vulnerability of the chip is difficult to discover, and the safety of the chip can be improved.
After the processor is started, the processor executes functions such as chip configuration, power-on/reset booting, user code execution and the like, and the functions are collectively called a boot program. Boot procedures include, but are not limited to: configuring clock frequency, configuring voltage trimming parameters, configuring system control registers, configuring a debugging module, configuring a peripheral module, configuring Input/Output (IO), and the like.
In some possible implementations of embodiments of the present application, the control module 101 may include a register, as shown in fig. 3. Fig. 3 is a schematic structural diagram of another chip provided in the embodiment of the present application. The chip 100 may include: a control module 101, a processor 102 and a memory 103. Wherein,
the control module 101 is electrically connected with the memory 103 and the processor 102 respectively;
a memory 103 for storing target data;
the control module 101 is used for generating a control signal for the memory 102 after the chip is powered on and reset; reading target data from the memory 102 according to the control signal; loading target data into a register; generating a first signal according to the target data; transmitting a first signal to the processor 102; the target data comprises all configuration information or part of configuration information of the chip.
And a processor 102 for determining whether to start working according to the first signal.
The control module 101 includes a register 104, and the register 104 is used for temporarily storing all or part of the target data, or data during or after transformation of the target data.
The register 104 may store target data read from the memory 103 for reading, not only by the control module 101, but also by other modules. Without a register, the target data read from the memory 103 can only be used for the control module 101 operations and cannot be used for other purposes.
In the embodiment of the application, because the target data includes all configuration information or part of configuration information of the chip, before the processor starts to work, all or part of configuration information of the chip is stored in the register, and after the processor starts to work, only a small amount of configuration information of the chip needs to be loaded or configuration information of the chip does not need to be loaded, so that the working efficiency of the processor can be improved.
In some possible implementations of embodiments of the present application, the control module 101 may be further configured to: detecting whether the register loads the configuration information correctly; under the condition that the register is detected to be loaded with the configuration information correctly, reading the configuration information from the register; according to the configuration information, a first signal is generated.
The embodiment of the present application does not limit the manner used for detecting whether the register is correctly loaded into all or part of the configuration information of the chip, and any available manner may be applied to the embodiment of the present application. For example, a consistency check is performed to check whether the register is correctly loaded with all or part of the configuration information of the chip.
In some possible implementations of embodiments of the present application, the control module 101 may include two parts: SCTRL3 and SCTRL 4. After the chip is reset, the SCTRL3 generates a control signal for the memory 103 and a preset address, the control signal including a driving signal for driving the memory 103 to operate, a read enable signal for controlling a read enable of the memory 103, and a data read signal including the preset address for reading target data from the memory 103. After the driving signal, the read enable signal and the data read signal enter the memory 103, the memory 103 is started to work and the read enable of the memory 103 is controlled, so that a hardware code (code) of a preset address is read, the code is all or part of configuration information of the chip, the read code is loaded into the register 104, and the data in the register 104 can be used as data for generating a starting signal of the processor 102 and can also be used as a chip configuration code in a bootstrap program of the processor 102. The SCTRL4 detects whether the configuration information is correctly loaded into the register 104, and when it is detected that the configuration information is correctly loaded into the register 104, reads the configuration information from the register 104, and generates a first signal according to the configuration information.
Exemplarily, as shown in fig. 4. Fig. 4 is a schematic diagram of another process for generating a first signal according to an embodiment of the present disclosure. After the power-on reset of the chip, the SCTRL3 generates a driving signal d for driving the memory 103 to operate, a read enable signal re for controlling the read enable of the memory 103, and a data read signal rd including a preset address for reading target data from the memory 103. Wherein, the preset address included in rd is Add [3 ]. After the driving signal d and the read enable signal re enter the memory 103, the memory 103 is started to work and the read enable of the memory 103 is controlled, and the SCTRL3 reads data from a storage area corresponding to the Add [3] in the memory 103 according to the preset address Add [3] included in the data read signal rd. SCTRL3 reads code 11000001, loads 11000001 into register 104, and when 11000001 is correctly loaded into register 104, SCTRL4 reads 11000001 from register 104, and then performs a target translation on 11000001 to convert to the first signal "00100001". SCTRL4 transmits 00100001 to processor 102 and processor 102 will begin operation upon receiving 00100001. When 00100001 is not received or 00100001 is not received, processor 102 is not active.
Fig. 5 is a flowchart illustrating a processor driving method according to an embodiment of the present application. The processor driving method provided by the embodiment of the application can be applied to the chip provided by the embodiment of the application. The processor driving method comprises the following steps:
step 501: after the chip is powered on and reset, generating a control signal aiming at the memory;
step 502: reading target data from a memory according to the control signal;
step 503: generating a first signal according to the target data;
step 504: a first signal is transmitted to the processor to cause the processor to determine whether to begin operation based on the first signal.
Specifically, after the chip is powered on and reset, the control module generates a control signal for the memory, reads target data from the memory according to the control signal, generates a first signal according to the target data, and transmits the first signal to the processor. The processor determines whether to start working after receiving the first signal, and starts working when determining that the processor starts working according to the first signal.
In an embodiment of the present application, a chip provided in an embodiment of the present application includes a memory, a control module, and a processor. The control module generates a control signal aiming at the memory after the chip is powered on and reset; reading target data from a memory according to the control signal; generating a first signal according to the target data; the first signal is transmitted to a processor. The processor determines whether it is to start operating according to the first signal. Thus, the processor starts to work only after the processor receives the first signal and determines to start to work according to the first signal, and the processor does not start to work after the chip is powered on and reset. And because the first signal is generated by the control module according to the target data in the memory, an attacker needs to acquire the target data of the memory and analyze the hardware circuit at the same time to possibly simulate the first signal, but because the target data is pre-stored in the memory of the chip, the attacker is difficult to acquire the target data in the memory and analyze the hardware circuit, so that even if the attacker acquires the chip, the attacker is difficult to simulate the first signal, the chip is difficult to simulate in a simulation mode, the vulnerability of the chip is difficult to find, and the safety of the chip can be improved.
In some possible implementations of the embodiments of the application, the processor may match the first signal with a preset signal value after receiving the first signal, and start to operate when the first signal matches with the preset signal value.
In some possible implementations of the embodiments of the present application, the control module may generate a driving signal for driving the memory to operate, a read enable signal for controlling a read enable of the memory, and a data read signal for reading target data from the memory, and transmit the driving signal, the read enable signal, and the data read signal to the memory. The memory starts to work after receiving the driving signal, and then the data reading function is started according to the reading enabling signal, so that the control module can read data from the memory, and then the control module reads target data from the memory according to the data reading signal.
In some possible implementations of the embodiments of the present application, the target data may be stored in a storage area corresponding to the preset address in the memory. The control module may further: generating a preset address; transmitting a data read signal including a preset address to a memory; and reading the target data from the storage area according to the preset address.
In some possible implementations of the embodiments of the present application, the preset address may be a plurality of addresses. Furthermore, the target data may be acquired from a plurality of addresses, that is, the target data in the embodiment of the present application is a combination of data stored in storage areas corresponding to the plurality of addresses.
In the embodiment of the application, since the target data is formed by combining the data stored in the storage areas corresponding to the plurality of addresses, even if an attacker acquires the chip, the attacker does not know which data the target data is formed by combining, and further hardly acquires the target data, so that the first signal cannot be simulated, and further the chip is difficult to simulate in a simulation mode, so that a bug of the chip is difficult to find, and the security of the chip can be improved.
In some possible implementations of the embodiments of the present application, the target data in the embodiments of the present application may include: all or part of the configuration information of the chip.
In the embodiment of the application, the first signal can be generated through all or part of configuration information of the chip, and then the processor is driven to work. Because the target data includes all or part of configuration information of the chip, the configuration information of the chip is not needed or only a small amount of configuration information of the chip is needed in the bootstrap program, even if the bootstrap program of the chip is acquired by an attacker, the attacker cannot acquire all or part of the configuration information of the chip, and further the chip is difficult to be simulated in a simulation mode, so that the vulnerability of the chip is difficult to discover, and the safety of the chip can be improved.
In some possible implementations of the embodiment of the present application, after step 502 and before step 503, the method for driving a processor provided in the embodiment of the present application may further include: target data including all or part of configuration information of the chip is loaded into the register.
In the embodiment of the application, because the target data includes all configuration information or part of configuration information of the chip, before the processor starts to work, all or part of configuration information of the chip is stored in the register, and after the processor starts to work, only a small amount of configuration information of the chip needs to be loaded or configuration information of the chip does not need to be loaded, so that the working efficiency of the processor can be improved.
In some possible implementations of the embodiment of the present application, after loading target data including all configuration information or part of configuration information of a chip into a register, the method for driving a processor provided in the embodiment of the present application may further include: whether the register is correctly loaded with all or part of configuration information of the chip is detected. When it is detected that the register is correctly loaded with all or part of the configuration information of the chip, step 503 is executed.
The embodiment of the present application does not limit the manner used for detecting whether the register is correctly loaded into all or part of the configuration information of the chip, and any available manner may be applied to the embodiment of the present application. For example, a consistency check is performed to check whether the register is correctly loaded with all or part of the configuration information of the chip.
The embodiment of the application also provides electronic equipment comprising the chip provided by the embodiment of the application.
It should be understood that the chips mentioned in the embodiments of the present application may also be referred to as system-on-chip, system-on-chip or system-on-chip, etc.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Further, it should be noted that the scope of the methods and apparatus of the embodiments of the present application is not limited to performing the functions in the order illustrated or discussed, but may include performing the functions in a substantially simultaneous manner or in a reverse order based on the functions involved, e.g., the methods described may be performed in an order different than that described, and various steps may be added, omitted, or combined. In addition, features described with reference to certain examples may be combined in other examples.
Through the above description of the embodiments, those skilled in the art can clearly understand that the method of the above embodiments is implemented by hardware.
While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A chip, wherein the chip comprises: a memory, a control module, and a processor, wherein,
the control module is electrically connected with the memory and the processor respectively;
the memory is used for storing target data;
the control module is used for generating a control signal aiming at the memory; reading the target data from the memory according to the control signal; generating a first signal according to the target data; transmitting the first signal to the processor;
the processor is used for determining whether to start working according to the first signal.
2. The chip of claim 1, wherein the control module is specifically configured to:
generating a driving signal for driving the memory to work, a read enable signal for controlling the read enable of the memory, and a data read signal for reading target data from the memory;
transmitting the driving signal to the memory so as to enable the memory to work under the driving of the driving signal;
transmitting the read enable signal to the memory so that the target data stored by the memory can be read under the control of the read enable signal;
and sending the data reading signal to the memory, and reading the target data from the memory according to the data reading signal.
3. The chip of claim 2, wherein the target data is stored in a storage area corresponding to a preset address in the memory; the control module is specifically configured to:
generating the preset address;
transmitting the data read signal including the preset address to the memory;
and reading the target data from the storage area according to the preset address.
4. The chip according to any one of claims 1 to 3, wherein the control module is specifically configured to:
and carrying out target transformation on the target data to obtain the first signal.
5. The chip according to any of claims 1 to 3, wherein the processor is specifically configured to:
detecting whether the first signal is matched with a preset signal value;
and determining that the processor starts to work under the condition that the first signal is detected to be matched with the preset signal value.
6. The chip of any of claims 1 to 3, wherein the target data comprises:
all or part of the configuration information of the chip.
7. The chip of claim 6, wherein the control module comprises: a register; the control module is further configured to:
loading the configuration information into the register.
8. The chip of claim 7, wherein the control module is further configured to:
detecting whether the register is loaded with the configuration information correctly;
reading the configuration information from the register in the case that the register is detected to be loaded with the configuration information correctly;
and generating the first signal according to the configuration information.
9. A processor driving method, wherein the method is applied to the chip of any one of claims 1 to 8; the method comprises the following steps:
generating a control signal for a memory;
reading target data from the memory according to the control signal;
generating a first signal according to the target data;
and transmitting the first signal to the processor to enable the processor to determine whether to start working according to the first signal.
10. An electronic device, characterized in that it comprises a chip according to any one of claims 1 to 8.
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