CN112989268B - Memory operation-oriented fully-unfolded non-orthogonal wiring memory array design method - Google Patents
Memory operation-oriented fully-unfolded non-orthogonal wiring memory array design method Download PDFInfo
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Abstract
The invention discloses a memory operation-oriented memory array design method for fully-unfolded non-orthogonal wiring, and belongs to the fields of memory operation integration and brain-like calculation. The memory array design method of the fully-expanded non-orthogonal wiring for memory operation comprises a memory array, wherein a memory unit is arranged In the array, the memory array inputs Data through a Data-In port as an operand, and the operand is a vector D converted from a matrix D ’ And simultaneously taking the data preprogrammed in the memory calculation unit as another operand matrix W. Vector D is caused by the combined action of Data input by data_in and Bias voltage added by bias_voltage port ’ And completing matrix multiplication operation with the matrix W so as to complete two-dimensional convolution on the matrix D. The invention utilizes the characteristics of two-dimensional convolution to redesign the connection relation between the array design and the storage and calculation units aiming at the fully-unfolded two-dimensional convolution, greatly reduces the redundancy and sparseness of the whole storage and calculation array, and can effectively reduce the whole array area under the condition of unchanged calculation force.
Description
Technical Field
The invention discloses a memory operation-oriented memory array design method for fully-unfolded non-orthogonal wiring, and belongs to the fields of memory operation integration and brain-like calculation.
Background
Most of the traditional computer architectures are von-neumann, i.e. memory-computing separation architectures, which not only cause a great deal of energy consumption in data transmission, but also cause the asynchronization of the storage rate and the operation rate, thereby affecting the overall operation speed. The in-memory calculation realizes the integration of memory calculation, and breaks through the speed wall and the power consumption wall of memory calculation. Meanwhile, by utilizing the characteristics of the devices, a single device can finish one-time multiplication and addition operation, has the characteristics of high speed, high parallelism and good energy efficiency ratio for the whole device array, and is suitable for neural network operation needing a large amount of multiplication and addition operation.
In the design of in-memory computation, the memory computation array mainly completes convolution operation, and the memory computation array in a fully-expanded form can complete convolution operation on all data at one time and output a convolution matrix, but the cost is larger area redundancy. The sparsity of devices participating in operation in the whole memory array is very high, the invention optimizes the sparsity, and provides the memory array with fully-unfolded non-orthogonal wiring, so that the sparsity of the devices participating in operation and the area of the whole memory array are greatly reduced.
Disclosure of Invention
(one) solving the technical problems
Aiming at the defects of the prior art, the invention provides a memory array design method of fully-unfolded non-orthogonal wiring for memory operation.
(II) technical scheme
In order to achieve the above purpose, the present invention provides the following technical solutions: the memory array design method for the fully-unfolded non-orthogonal wiring for the memory operation comprises an array, wherein a memory unit is arranged In the array, the memory unit inputs Data through a Data-In port as an operand d, and simultaneously, the Data preprogrammed In the memory unit is used as another operand w. Under the combined action of the Data input by the Data-In and the Bias voltage added by the Bias voltage port, the operand d and the operand w complete multiplication operation.
Further, each of the memory cells in the memory array are connected in a non-orthogonal manner.
Further, the storage array inputs the input matrix of the array through m×n data_in ports, where m represents the number of rows of the input matrix and n represents the number of columns of the input matrix.
Further, the storage array may be adapted for convolution operations of convolution kernels of various sizes.
Further, the data of the input matrix is m×n, and is developed into a vector of 1× (mxn) by the method of formula (1), where formula (1) is:
further, the 1× (mxn) vector is input by mxn data_in ports.
Further, the array outputs Data through the data_out port.
Further, the array performs a two-dimensional convolution operation on the input matrix in a manner of formula (2), where formula (2) is:
(III) beneficial effects
Compared with the prior art, the method for designing the memory array of the fully-unfolded non-orthogonal wiring for memory operation has the following beneficial effects:
the memory operation-oriented fully-unfolded non-orthogonal wiring memory array design method is suitable for convolution layer operation in memory calculation and can adapt to convolution kernels of various sizes. The invention utilizes the characteristics of two-dimensional convolution to redesign the connection relation between the array design and the storage and calculation units aiming at the fully-unfolded two-dimensional convolution, greatly reduces the redundancy and sparseness of the whole storage and calculation array, and can effectively reduce the whole array area under the condition of unchanged calculation force.
Drawings
Fig. 1 is a block diagram showing the overall structure of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
Referring to fig. 1, a memory array design method of fully-expanded non-orthogonal wiring for memory operation includes an array, in which a memory unit is disposed, and the memory unit inputs Data as an operand d through a data_in port, and simultaneously uses Data preprogrammed In the memory unit as another operand w. Under the combined action of the Data input by the Data-In and the Bias voltage added by the Bias voltage port, the operand d and the operand w complete multiplication operation.
The data inputs of each of the memory cells in the array are routed non-orthogonally.
The invention will be further described with reference to the following specific drawings and examples.
FIG. 1 shows an example of a memory array according to the present invention, in which the input data is an mxn matrix, the convolution kernel uses two sizes, 3×3 and 2×2, and the corresponding convolved output matrix sizes are (m-2) x (n-2) and (m-1) x (n-1).
The block labeled CIM in the figure is the memory unit. The memory cell inputs Data as one operand d through the Data In port, while taking Data preprogrammed In the memory cell as another operand w. Under the combined action of the Data input by the Data-In and the Bias voltage added by the Bias voltage port, the operand d and the operand w complete multiplication operation.
The array has 2n+3 columns and m×n rows, wherein at most, the memory cells of the 1 st, 2 nd, 3 rd, n+1 st, n+2 nd, n+3 rd, 2n+1 st, 2n+2 nd and 2n+3 rd columns are pre-programmed with an operation amount w, and other operation units are only occupied and are called redundant units. The purpose of placing redundant units is firstly to facilitate wiring of later-stage layout, and secondly to ensure consistency of each operation unit. Meanwhile, only the 1 st to (m-1) x (n-1) th rows are provided with memory units, and only the (m-1) x (n-1) +1 th to m x n th rows are provided with wiring without memory units, so that the first design is to meet the requirement that the sizes of an input matrix and an output convolution matrix are not matched; secondly, the wiring of the later layout is convenient.
The connections between each memory cell in the array are non-orthogonal wiring, such as: the data input ports of the memory devices of the first row and the first column are singly connected out; the data input ends of the first row and the second column are connected with and connected with the data input end of the first column storage unit of the second row in parallel; the data input ends of the first row, the third column, the second row and the first column of the third row are connected in detail and output the devices which are similarly pushed to the (m-1) x (n-1), and since the data input port of the device of the last row can exceed the (m-1) x (n-1) row after oblique wiring, the invention is provided with a wiring area of m+n-2 rows, namely the (m-1) x (n-1) +1 row to the m x n row in the array, as shown in detail in figure 1.
In this example, the computational array can adapt to convolution kernels of two sizes, 3×3 and 2×2, so as to meet the operation requirements of most convolution neural networks. When the convolution kernel size is 3×3, the 1 st, 2 nd, 3 rd, n+1 st, n+2 nd, n+3 th, 2n+1 st, 2n+2 nd, 2n+3 rd columns of memory cells are enabled, and the operation amount w is preprogrammed, and then the convolution matrix with edges is output. When the convolution kernel size is 2×2, the memory cells of columns 1, 2, n+1, n+2 are enabled and preprogrammed with an operand w, at which time the output is a convolution matrix without edges.
The input matrix is expanded into a 1× (mxn) vector by the way of equation (1) and input from the data_in port of mxn rows. At the same time, each row of memory cells is preprogrammed with the same another operand w.
The analog output from each operation unit in a row of the array is collected and output from data_out, and finally the array can complete two-dimensional convolution operation on the input matrix in the mode of the formula (2).
In summary, the memory array design of the fully-expanded non-orthogonal wiring for memory operationsThe method greatly compresses the redundancy of the array when in use, the area of the array designed by the invention is (2n+3) multiplied by m multiplied by n, and the area of the array required by the traditional scheme is m 2 ×n 2 The theoretical area compression ratio isTaking m=n=48 as an example, the area compression ratio of the present invention is 24 times.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (5)
1. The memory array design method for the fully-unfolded non-orthogonal wiring for the memory operation is characterized by comprising a memory array, wherein a memory unit is arranged In the memory array, the memory unit inputs Data through a Data-In port as an operand d, simultaneously takes the Data preprogrammed In the memory unit as another operand w, and completes multiplication operation of the operand d and the operand w under the combined action of Data input by Data-In and Bias voltage added by a Bias-voltage port;
the storage array inputs an input matrix of the array through m multiplied by n Data-In ports, wherein m represents the number of rows of the input matrix, and n represents the number of columns of the input matrix;
the size of the input matrix is m×n, and the input matrix is developed into a vector of 1× (m×n) by a method of formula (1), wherein the formula (1) is:
the array completes two-dimensional convolution operation on an input matrix in a mode of a formula (2), wherein the formula (2) is as follows:
2. the memory array design method for the fully-expanded non-orthogonal wiring for memory operations according to claim 1, wherein the method comprises the following steps: each of the memory cells in the memory array are connected in a non-orthogonal manner.
3. The memory array design method for the fully-expanded non-orthogonal wiring for memory operations according to claim 2, wherein the method comprises the following steps: the storage array may accommodate convolution operations of convolution kernels of various sizes.
4. The memory array design method for fully-expanded non-orthogonal wiring for memory operations according to claim 3, wherein: the 1× (mxn) vector is input by the mxn Data-In ports of the array.
5. The memory array design method for the fully-expanded non-orthogonal wiring for memory operations according to claim 4, wherein the method comprises the following steps: the array outputs Data through the data_out port.
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