CN112988652A

CN112988652A - Computer system

Info

Publication number: CN112988652A
Application number: CN201911212750.4A
Authority: CN
Inventors: 严勤; 王太诚; 王荣; 兰荣
Original assignee: Hongfujin Precision Industry Wuhan Co Ltd; Hon Hai Precision Industry Co Ltd
Current assignee: Hongfujin Precision Industry Wuhan Co Ltd; Hon Hai Precision Industry Co Ltd
Priority date: 2019-12-02
Filing date: 2019-12-02
Publication date: 2021-06-18

Abstract

A computer system comprises a processor, a first chip, a second chip and a memory; the memory is used for storing a first program and a second program; the processor is electrically connected to the first chip and is used for outputting a first instruction and a second instruction to the first chip; the first chip is electrically connected to the memory and the second chip, and is used for acquiring a first program of the memory when receiving the first instruction so as to complete power-on self-test; the first chip is also used for sending a third instruction to the second chip when receiving the second instruction; and the second chip is used for acquiring a second program of the memory according to the third instruction so as to control peripheral equipment to execute corresponding operation. The computer system provided by the invention reduces the arrangement of the memory, can save the cost and can effectively monitor the hardware connected with the system.

Description

Computer system

Technical Field

The present invention relates to a computer system.

Background

In order to better monitor computer hardware, a separate Embedded Controller (EC) is often used on a computer motherboard to electrically connect with a Super Peripheral Interface (SIO), and a read-only memory (ROM) is added to detect hardware information of the SIO, so as to ensure the working performance of the SIO.

However, the peripheral circuits of the EC ROM need to be added to the hardware circuit to ensure that the EC is normally operated, thereby increasing the cost.

Disclosure of Invention

In view of the foregoing, there is a need for a computer system that is less costly and that can assist the super i/o chip in monitoring hardware behavior.

A computer system comprises a processor, a first chip, a second chip and a memory;

the memory is used for storing a first program and a second program;

the processor is electrically connected to the first chip and is used for outputting a first instruction and a second instruction to the first chip;

the first chip is electrically connected to the memory and the second chip, and is used for acquiring a first program of the memory when receiving the first instruction so as to complete power-on self-test; the first chip is also used for sending a third instruction to the second chip when receiving the second instruction; and

the second chip is used for acquiring a second program of the memory according to the third instruction so as to control peripheral equipment to execute corresponding operation.

Further, the peripheral device includes a fan, and the second chip is configured to control an operating state of the fan by the second program.

Further, the peripheral device further includes an interaction device, and the second chip is used for the second program to perform interaction management of input and output on the interaction device.

Further, the interactive device comprises a keyboard, a mouse, a touch screen and other devices for input and output.

Further, the peripheral device further includes a power supply in the computer system for supplying a power supply voltage to the components, and the second chip is used for controlling the power supply by the second program.

Furthermore, the first chip calls a first program and data in the memory through a first bus, and the first chip stores the data in the memory through the first bus.

Furthermore, the second chip calls a second program and data in the memory shaft through the first bus and stores the data into the memory through the first bus.

In some embodiments, the first bus comprises a Serial Peripheral Interface (SPI bus).

In some embodiments, the first chip and the second chip are electrically connected through a second Bus, where the second Bus is a Low pin count Bus (LPC Bus) or an Enhanced Serial Peripheral Interface (eSPI Bus).

In some embodiments, the first Chip includes a Platform management Controller Hub (PCH) Chip, and the second Chip includes a Super Input and Output Chip (SIO).

According to the computer system provided by the embodiment of the application, the memory is electrically connected with the first chip and the second chip, so that the first chip and the second chip can share and access the memory, the setting of the memory in the computer system is reduced, the cost can be saved, and the hardware connected with the system can be effectively monitored.

Drawings

FIG. 1 is a functional block diagram of a computer system in accordance with a preferred embodiment of the present invention.

Description of the main elements

Computer system 100

Processor 10

First chip 20

Second chip 30

Memory 40

First bus 41

Second bus 42

The following detailed description will further illustrate the invention in conjunction with the above-described figures.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It will be understood that when an element is referred to as being "electrically connected" to another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "electrically connected" to another element, it can be connected by contact, e.g., by wires, or by contactless connection, e.g., by contactless coupling.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

Referring to fig. 1, the present invention provides a computer system 100. The computer system 100 operates in an electronic device (not shown). The electronic device may be, but is not limited to, a desktop computer, a notebook computer, a tablet computer, a Personal Digital Assistant (PDA), a smart phone, a game, a server computer, and the like.

In this embodiment, the computer system 100 may operate in a server.

The computer system 100 includes a processor 10, a first chip 20, a second chip 30, and a memory 40. In the present embodiment, the processor 10, the first chip 20, the second chip 30 and the memory 40 are disposed on a main board (not shown) of the electronic device. The electronic device (such as a server) is also connected with other peripheral equipment, such as a keyboard, a mouse and the like.

In this embodiment, the processor 10 is electrically connected to the first chip 20, the first chip 20 is electrically connected to the second chip 30, and the memory 40 is electrically connected to the first chip 20 and the second chip 30.

In this embodiment, the first chip 20 is electrically connected to the second chip 30 through a first bus 41, and the memory 40 is electrically connected to the first bus 41, so that the memory 40 is electrically connected to the first chip 20 and the second chip 30. The first bus 41 may be a Serial Peripheral Interface (SPI) bus.

In this embodiment, the first chip 20 and the second chip 30 are electrically connected through a second bus 42. The second Bus 42 may be a Low pin count Bus (LPC) Bus or an Enhanced Serial Peripheral Interface (eSPI) Bus.

In one embodiment, the processor 10 may be a Central Processing Unit (CPU), the first Chip 20 may be a Platform Controller Hub (PCH) Chip, the second Chip 30 may be a Super Input and Output Chip (SIO), and the memory 40 may be a Basic Input/Output System ROM (BIOS ROM).

In this embodiment, the processor 10 is configured to control the first chip 20 to complete power-on self-test and execute a corresponding instruction.

Specifically, the first chip 20 is configured to receive a first instruction issued by the processor 10, and further execute a corresponding operation or/and send a second instruction to the second chip 30.

The second chip 30 is used to electrically connect to a peripheral low-speed device (not shown), which may be a keyboard, a mouse, a serial port, a parallel port, a fan, or the like. The second chip 30 is further configured to receive a second instruction sent by the first chip 20, so as to control the peripheral device to perform a corresponding operation.

The memory 40 stores a first program and a second program. Wherein the first program is a part of the BIOS code and is executed first when the computer system 100 is started. The first program provides the lowest layer and most direct hardware setting and control for the computer, such as system initialization, hardware component inspection, reading disk information and file output to a printer. The second program provides additional hardware control for the electronic device, and the task executed by the second program comprises one or more of the following tasks: power control of the computer system 100, that is, controlling a power supply in the computer system 100 to supply a power supply voltage to each component; fan control, i.e. controlling the operation of fans in the computer system 100; thermal monitoring, i.e., intelligently managing the temperature of various components in the computer system 100; interactive device management, that is, interactive management of input and output of devices such as keyboard scanning, mouse, and touch screen in the computer system 100.

Specifically, when an electronic device (e.g., a server) is powered on and a power key is pressed, the main board (not shown) is powered on, and the power of the main board generates a low level signal, and the low level signal outputs a RESET signal to the processor 10 through a clock generator (not shown) on the main board, so as to initialize the processor 10. When the power supply is stable and the initialization of the processor 10 is completed, the processor 10 executes a predetermined instruction from a predetermined address, thereby sending a first instruction to the first chip 20. After receiving the first instruction, the first chip 20 calls the first program from the memory 40 and executes the first program, thereby starting a power-on self-test procedure to check whether the hardware device connected to the computer system 100 is normal. After the power-on self-test is completed, the first program continues to guide the computer system 100 to initialize, thereby completing the boot process of the electronic device.

After the computer is turned on, the processor 10 sends a second instruction to the first chip 20, and the first chip 20 receives the second instruction, and calls data from the memory 40 through the first bus 41 to execute a corresponding operation. The first chip 20 also issues a third command to the second chip 30 via the second bus 42. After receiving the third instruction, the second chip 30 calls the second program of the memory 40 through the first bus 41 to control peripheral devices (such as a keyboard, a mouse, etc.) to perform corresponding operations, and stores data generated by the peripheral devices into the memory 40 through the first bus 41.

It is understood that the first chip 20 may also store data in the memory 40 through the first bus 41.

According to the computer system provided by the embodiment of the invention, the memory 40 is electrically connected with the first chip 20 and the second chip 30, so that the shared access of the first chip 20 and the second chip 30 to the memory 40 is realized, the setting of a private memory in the computer system is reduced, the production cost is saved, and the hardware connected with the system can be effectively monitored.

Although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the invention. Those skilled in the art can also make other changes and the like in the design of the present invention within the spirit of the present invention as long as they do not depart from the technical effects of the present invention. Such variations are intended to be included within the scope of the invention as claimed.

Claims

1. A computer system, the computer system comprising a processor, a first chip, a second chip, and a memory, wherein:

the memory is used for storing a first program and a second program;

2. The computer system of claim 1, wherein: the peripheral equipment comprises a fan, and the second chip is used for controlling the running state of the fan according to the second program.

3. The computer system of claim 1, wherein: the peripheral equipment further comprises interactive equipment, and the second chip is used for performing input and output interactive management on the interactive equipment according to the second program.

4. The computer system of claim 3, wherein: the interactive device comprises a keyboard, a mouse and a touch screen.

5. The computer system of claim 1, wherein: the peripheral device further comprises a power supply, and the second chip is used for controlling the power supply according to a second program.

6. The computer system of claim 1, wherein: the first chip calls a first program and data in the memory through a first bus, and the first chip stores the data in the memory through the first bus.

7. The computer system of claim 6, wherein: the second chip calls a second program and data in the memory shaft through the first bus and stores the data in the memory through the first bus.

8. The computer system of claim 7, wherein: the first bus is a serial peripheral interface bus.

9. The computer system of claim 1, wherein: the first chip and the second chip are electrically connected through a second bus, and the second bus is a low-pin-count bus or an enhanced serial peripheral interface bus.

10. The computer system of claim 1, wherein: the first chip comprises a platform management control chip, and the second chip comprises a super input-output chip.