CN112988602B - Verification platform generation method and device, computer equipment and storage medium - Google Patents
Verification platform generation method and device, computer equipment and storage medium Download PDFInfo
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- CN112988602B CN112988602B CN202110477666.6A CN202110477666A CN112988602B CN 112988602 B CN112988602 B CN 112988602B CN 202110477666 A CN202110477666 A CN 202110477666A CN 112988602 B CN112988602 B CN 112988602B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
- G06F11/3672—Test management
- G06F11/3688—Test management for test execution, e.g. scheduling of test suites
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
- G06F11/3696—Methods or tools to render software testable
Abstract
The application relates to a generation method and device of a verification platform, computer equipment and a storage medium. The method comprises the following steps: obtaining a verification model applicable to a first operating environment; adding a calling interface at the initial calling position of the verification model to obtain a target verification model; instantiating the calling interface in the target verification platform; the target verification platform is a verification platform suitable for the second operation environment; and calling the target verification model through the calling interface, and integrating the target verification model into the target verification platform. Therefore, the obtained target verification model can be called by the verification platform of the second operation environment by adding the calling interface to the verification model corresponding to the first operation environment, so that the verification model corresponding to the first operation environment is integrated into the verification platform corresponding to the second operation environment in a whole package, and the building efficiency of the verification platform is improved.
Description
Technical Field
The present application relates to the field of chip testing technologies, and in particular, to a verification platform generation method, an apparatus, a computer device, and a storage medium.
Background
With the development of chip manufacturing technology, a technology for performing system-level verification on chip performance appears, and the performance and logic of a chip can be verified through a test case. In the test and Verification of a chip, a conventional technology is generally based on a Universal Verification Methodology (UVM), a Verification model (Verification IP, VIP) for testing is written, then a certain amount of VIP is integrated into a Verification platform in a UVM environment, and the chip is verified through the UVM Verification platform.
However, when the verification platform of the chip is not in the UVM environment, the original VIP needs to be disassembled, reassembled, and the like to form a new verification platform suitable for a new operating environment, which results in low building efficiency of the verification platform.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method and an apparatus for generating a verification platform, a computer device, and a storage medium, which can improve efficiency of building the verification platform.
A method of generating a verification platform, the method comprising:
obtaining a verification model applicable to a first operating environment;
adding a calling interface at the initial calling position of the verification model to obtain a target verification model;
instantiating the call interface in a target verification platform; the target verification platform is a verification platform suitable for a second operation environment;
and calling the target verification model through the calling interface, and integrating the target verification model into the target verification platform.
In one embodiment, before adding a calling interface at a starting calling position of the verification model to obtain a target verification model, the method further includes:
deleting the program code corresponding to the error reporting mechanism from the basic package corresponding to the verification model; the basic package represents a general library corresponding to the first operating environment, and the error reporting mechanism is used for reporting an error when the called time of the verification model is greater than 0.
In one embodiment, the deleting the error reporting mechanism from the basic package corresponding to the verification model includes:
determining a root operation stage function from the basic packet;
based on a preset identification, searching a program code corresponding to the error reporting mechanism in the root operation stage function;
and deleting the program code corresponding to the error reporting mechanism.
In one embodiment, after adding a calling interface at a starting calling position of the verification model to obtain a target verification model, the method further includes:
in the calling interface, modifying an end identifier in a basic packet corresponding to the target verification model; and the end identifier is used for indicating the end of the test case after generating the test sequence corresponding to the target verification model.
In one embodiment, the modifying, in the call interface, the end identifier corresponding to the basic package includes:
setting parameters corresponding to the ending marks as preset values; wherein the preset value indicates that the end flag is invalid. In one embodiment, after the calling the target verification model through the calling interface and integrating the target verification model into the target verification platform, the method further includes:
acquiring a target test case;
determining a target verification model to be used from the target verification platform according to the target test case;
determining a target test sequence according to the target test case and the target verification model to be used;
and verifying the chip corresponding to the target verification model according to the target test sequence.
In one embodiment, the determining a target test sequence according to the target test case and the target verification model to be used includes:
calling a calling interface corresponding to each target verification model to be used to obtain a test sequence identification set corresponding to the target verification model to be used;
and determining a target test sequence matched with the target test case from the test sequence identification set.
An apparatus for generating a verification platform, the apparatus comprising:
the data acquisition module is used for acquiring a verification model suitable for the first operating environment;
the interface adding module is used for adding a calling interface at the initial calling position of the verification model to obtain a target verification model;
the model instantiation module is used for instantiating the calling interface in a target verification platform; the target verification platform is a verification platform suitable for a second operation environment;
and the platform generation module is used for calling the target verification model through the calling interface and integrating the target verification model into the target verification platform.
A computer device comprising a memory storing a computer program and a processor implementing the method of any of the above embodiments when the processor executes the computer program.
A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method of any of the above embodiments.
The generation method and device of the verification platform, the computer equipment and the storage medium obtain a verification model suitable for the first operating environment; adding a calling interface at the initial calling position of the verification model to obtain a target verification model; instantiating the calling interface in the target verification platform; the target verification platform is a verification platform suitable for the second operation environment; and calling the target verification model through the calling interface, and integrating the target verification model into the target verification platform. Based on the scheme, the obtained target verification model can be called by the verification platform of the second operation environment by adding the calling interface to the verification model corresponding to the first operation environment, so that the verification model corresponding to the first operation environment is integrated into the verification platform corresponding to the second operation environment in a whole package mode, and the building efficiency of the verification platform is improved.
Drawings
FIG. 1 is a flow diagram that illustrates a method for generating a verification platform, according to one embodiment;
FIG. 2 is a flow diagram illustrating an example of a delete error reporting mechanism;
FIG. 3 is a flow diagram that illustrates a method for performing a test based on a target verification platform, according to one embodiment;
FIG. 4 is a flowchart illustrating an example implementation of step S530;
FIG. 5 is a block diagram showing the structure of a generation apparatus of a verification platform according to an embodiment;
FIG. 6 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are capable of operation in sequences other than those illustrated or otherwise described herein. The implementations described in the exemplary embodiments below are not intended to represent all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.
In an embodiment, as shown in fig. 1, a method for generating a verification platform is provided, and this embodiment is illustrated by applying the method to a terminal, it is to be understood that the method may also be applied to a server, and may also be applied to a system including a terminal and a server, and is implemented by interaction between the terminal and the server. In this embodiment, the method includes the steps of:
step S100, a verification model suitable for the first operating environment is obtained.
And step S200, adding a calling interface at the initial calling position of the verification model to obtain the target verification model.
Step S300, instantiating the calling interface in a target verification platform; and the target verification platform is a verification platform suitable for the second operating environment.
And step S400, calling the target verification model through the calling interface, and integrating the target verification model into the target verification platform.
The verification model refers to a test model for performing test verification on the chip, such as a VIP model. The first operating environment refers to an operating environment for generating and operating the verification model, and the second operating environment is an operating environment of the target verification platform. The second operating environment may be the same as or different from the first operating environment. For example, the first operating environment may be a UVM environment and the second operating environment may be a non-UVM environment. The initial calling position refers to a starting position point of the verification model for starting to execute the test verification, and when the verification model is a VIP model suitable for the first operating environment, the initial calling position is the top layer of the VIP.
Specifically, an original verification model VIP suitable for the first execution environment is obtained, a calling interface is added at a starting calling position (for example, the top layer of the VIP) of the verification model VIP, so that the verification model is called and used, and the verification model with the added calling interface is determined as a target verification model. The target verification model is then instantiated in a target verification platform adapted to the second operating environment, optionally on top of the target verification platform. After the calling interface is instantiated in the target verification platform, the target verification model is called through the calling interface, the target verification model is integrated into the target verification platform, the target verification platform suitable for the second operation environment is obtained, the target verification platform integrates the target verification model suitable for the first operation environment, secondary construction of a verification model VIP is not needed, and the construction efficiency of the target verification platform is improved.
The generation method of the verification platform obtains a verification model applicable to a first operating environment; adding a calling interface at the initial calling position of the verification model to obtain a target verification model; instantiating the calling interface in the target verification platform; the target verification platform is a verification platform suitable for the second operation environment; and calling the target verification model through the calling interface, and integrating the target verification model into the target verification platform. Therefore, the obtained target verification model can be called by the verification platform of the second operation environment by adding the calling interface to the verification model corresponding to the first operation environment, so that the verification model corresponding to the first operation environment is integrated into the verification platform corresponding to the second operation environment in a whole package, and the building efficiency of the verification platform is improved.
In one embodiment, the method before step S200 includes:
deleting the program code corresponding to the error reporting mechanism from the basic package corresponding to the verification model; the basic package represents a general library corresponding to the first operating environment, and the error reporting mechanism is used for reporting an error when the called time of the verification model is greater than 0.
Specifically, the error reporting mechanism refers to a mechanism for reporting an error when the time when the verification model is invoked is greater than 0. Specifically, the first operating environment may be determined by determining whether the start time of the verification model VIP in the basic packet is 0, and by means of preset character matching, a mechanism that is based on the first operating environment and performs 0-point start restriction on the verification model VIP, that is, an error reporting mechanism, is searched in the basic packet. After the error reporting mechanism is found, the program code corresponding to the error reporting mechanism is further searched, and the program code is deleted. After the program code is deleted, the restriction of the first operating environment on the verification model can be removed, so that the verification model VIP can be started at any time, and a basis is provided for the subsequent whole package integration of the verification model suitable for the first operating environment into the second environment.
Optionally, as shown in fig. 2, for a schematic flowchart of deleting an error reporting mechanism, the process of deleting a program code corresponding to the error reporting mechanism from the basic package corresponding to the verification model specifically includes the following steps:
step S211, determining a root run phase function from the basic packet.
Step S212, based on the preset identifier, searching for a program code corresponding to the error reporting mechanism in the root operation stage function.
Step S213, deleting the program code corresponding to the error reporting mechanism.
And the preset identification represents an identification for reporting errors when the called time of the verification model is greater than 0, and the identification is a section of code in the basic packet.
Specifically, a root run phase function (i.e., a run _ phase function in the uvm _ root class) is determined from the basic package, and a program code corresponding to a preset identifier is searched in the run _ phase function, where the program code is used to implement the error reporting mechanism, and an error is reported when the called time of the verification model VIP is greater than 0. And after finding the program code corresponding to the error reporting mechanism, deleting the program code corresponding to the error reporting mechanism so as to remove the limitation that the VIP (verification module) must be started at the simulation time 0. The restriction of the verification model VIP by the first execution environment may thus be removed, so that the verification model VIP may be started at any time, providing a basis for subsequent integration of the verification model VIP applicable to the first execution environment into the second environment.
For example, the limitation in the UVM methodology that the UVM verification model VIP must be started at simulation time 0 is removed, including: and modifying a run _ phase function (root run function) in UVM _ root class in the UVM package, and canceling the mechanism for judging whether the root run function run _ phase is mistakenly reported when the calling time is greater than 0, so that the purpose of starting the UVM at any time is achieved. By modifying the UVM base library, the limitation that the start point of the UVM verification model VIP must start from the simulation time 0 is broken, and the UVM verification platform can be started at any time point specified in verilog, that is, the UVM verification model VIP can be started at any time point, so that a plurality of UVM verification models VIP can be integrally integrated into a non-UVM SOC verification platform (chip system level verification platform).
In the above embodiment, the program code corresponding to the error reporting mechanism is deleted from the basic package corresponding to the verification model, so that the limitation of the first operating environment on the verification model can be removed, the verification model can be started at any time, and a basis is provided for subsequently integrating the whole verification model suitable for the first operating environment into the second environment.
In one embodiment, which is an implementable manner after step S200, the method includes:
and in the calling interface, modifying an ending identifier in the basic packet corresponding to the target verification model, wherein the ending identifier is used for indicating to end the test case after generating a test sequence corresponding to the target verification model.
Specifically, an end identifier is usually set in a basic packet corresponding to the target verification model, and when the terminal detects the end identifier in the basic packet, the test case is ended. In order to prevent the test case from being ended after the operation of one target verification model is ended, the basic packet can be modified, specifically, after the ending identifier is found in the basic packet, the ending identifier is modified, so that the test case is not ended after the operation of the target verification model is ended, and a foundation is provided for continuing the operation of the next verification model VIP.
Optionally, in the call interface, modifying the end identifier corresponding to the basic packet specifically includes: and setting the parameter corresponding to the ending identifier as a preset value.
The ending mark represents an identifier of the ending test case, and the preset value represents that the ending mark is invalid, for example, "0" in the computer language is adopted to represent the removal of the limitation of ending the test case.
Specifically, an end identifier (finish _ on _ completion) that is based on the first execution environment and ends the execution of the verification model VIP is found in the basic package. And after the ending identifier in the target verification model is obtained, modifying the ending identifier, and setting the parameter corresponding to the ending identifier as a preset value to remove the limitation of ending the test case after the operation of the target verification model is ended, so that the test case is not ended after the operation of the target verification model is ended, and a basis is provided for continuing the operation of the next verification model VIP.
Illustratively, the limitation of ending the simulation by the UVM VIP after the test sequence end is generated is removed inside the UVM VIP call interface established in step S200. Since in the default UVM methodology, once a test sequence is generated, the UVM will send an end signal, ending the entire test case. However, when the SOC test case is written, modules other than the UVM VIP are still running after the test sequence is ended, so that the whole SOC test case cannot be ended according to whether the UVM VIP is ended. The method for canceling uvm vip to end the SOC test case is that an end signal finish _ on _ complete of an uvm _ top object is set to be a preset value 0. Therefore, the test case is not finished after the target verification model is operated, and a foundation is provided for continuing the operation of the next verification model VIP.
Optionally, the purpose of starting the UVM at any time can be achieved by canceling the error reporting mechanism when the called time of run _ phase is greater than 0, and the purpose of not ending the test case after the operation of the target verification model is ended can be achieved by setting the end signal finish _ on _ completion of UVM _ top object to be the preset value 0. Therefore, the UVM verification model VIP can be started at any time, the operation of another UVM verification model VIP is waited after the operation technology of one UVM verification model VIP, and the aims of integrating a plurality of UVM verification models VIPs into one target verification platform and testing and verifying chips are fulfilled.
In the above embodiment, in the calling interface, the end identifier in the basic packet corresponding to the target verification model is modified, so that the test case is not ended after the target verification model is finished running, and a basis is provided for continuing running of the next verification model VIP.
In one embodiment, one possible implementation of step S300 includes:
and adding a calling interface at the initial calling position of the verification model to obtain the target verification model, wherein the calling interface of the verification model VIP can be instantiated on the top layer of the SOC verification platform. Optionally, different UVM verification models VIP may be specified through the non-UVM verification platform to perform dynamic creation, different factors are created, different UVM tree structures are constructed, and then corresponding test cases are executed according to requirements. Therefore, the time for integrating a plurality of UVM verification models VIP into the SOC verification platform can be shortened, and meanwhile, the requirements on the technical level of verification personnel can be lowered.
In an embodiment, as shown in fig. 3, there is further provided a method for performing a test based on a target verification platform, including the following steps:
step S510, a target test case is obtained.
And S520, determining a target verification model to be used from the target verification platform according to the target test case.
Step S530, a target test sequence is determined according to the target test case and the target verification model to be used.
And S540, verifying the chip corresponding to the target verification model according to the target test sequence.
Specifically, in steps S100 to S400, a call interface is added to at least one verification model originally applicable to the first operating environment, the restriction of starting the verification model VIP and the restriction of ending the verification model VIP are removed from the call interface, and the obtained target verification model is integrated into a target verification platform applicable to the second operating environment. And after a target verification platform suitable for the second operating environment is obtained, a target test case for testing and verifying the chip is obtained, and a target verification model required by the target test case, namely the target verification model to be used, is determined from the target verification platform according to the target test case. And determining a target test sequence according to the test verification requirements of the target verification model to be used by the target test case, and verifying the chip corresponding to the target verification model according to the target test sequence.
In the embodiment, the target test case is used for testing and verifying the chip based on the target verification platform which is set up efficiently, so that the test verification efficiency of the chip is improved.
In an embodiment, as shown in fig. 4, the flowchart of step S530 is a flow chart that can be implemented, and specifically includes the following steps:
step S531, for each target verification model to be used, calling an interface corresponding to the target verification model to be used to obtain a test sequence identifier set corresponding to the target verification model to be used.
And step S532, determining a target test sequence matched with the target test case from the test sequence identification set.
The test sequence identification set is an identification representing a test sequence, and a specific test sequence can be generated through the test sequence identification set.
Specifically, for each target verification model to be used, in the process of calling the target verification model to be used, a calling interface corresponding to the target verification model to be used is called, and a test sequence identification set corresponding to the target verification model to be used is obtained through the calling interface. The target test sequence corresponding to the target test case can be determined through the test sequence identification set, and a basis is provided for the test and verification of subsequent chips.
Illustratively, when a verification model VIP calling interface is added on top of the UVM verification model VIP, the calling interface corresponds to a test sequence identification set, including a run _ test function of the VM verification model VIP. The test case based on the SOC verification platform can transfer the test sequence name through a corresponding VIP top layer call verification model VIP call interface of the UVM verification model VIP, generate a corresponding VIP test sequence of the UVM verification model VIP, and test a module to be tested on the SOC. Since the limitation that the UVM verification model VIP must be started at the simulation time 0 is removed in step S203, any UVM verification model VIP may be started at any simulation time within the test case based on the SOC verification platform to generate the required simulation stimulus. Specifically, when the SOC-level test case is written, only the UVM verification model VIP call interface corresponding to the specific UVM verification model VIP needs to be called at the time when the SOC-level test case needs to generate the test stimulus, and the test sequence name is transferred to the UVM verification model VIP call interface, so that the UVM verification model VIP generates the specific test sequence at the specific time of the simulation.
In the embodiment, the calling interface corresponding to the target verification model to be used is called for each target verification model to be used, the test sequence identification set corresponding to the target verification model to be used is obtained by adding the calling interface to the verification model, the target test sequence matched with the target test case is determined from the test sequence identification set, a basis is provided for the target verification platform which is built based on high efficiency for the target test case to test and verify the chip, and the test verification efficiency of the chip can be improved.
It should be understood that although the various steps in the flow charts of fig. 1-4 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 1-4 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed in turn or alternately with other steps or at least some of the other steps.
In one embodiment, as shown in fig. 5, there is provided a generation apparatus of a verification platform, including: a data acquisition module 501, an interface adding module 502, a model instantiating module 503 and a platform generating module 504, wherein:
a data obtaining module 501, configured to obtain a verification model applicable to a first operating environment;
an interface adding module 502, configured to add a calling interface at an initial calling position of the verification model to obtain a target verification model;
a model instantiating module 503, configured to instantiate the call interface in the target verification platform; the target verification platform is a verification platform suitable for the second operation environment;
and the platform generation module 504 is configured to invoke the target verification model through the invocation interface, and integrate the target verification model into the target verification platform.
In one embodiment, the generation apparatus of the verification platform further includes a first restriction removal module configured to: deleting the program code corresponding to the error reporting mechanism from the basic package corresponding to the verification model; the basic package represents a general library corresponding to the first operating environment, and the error reporting mechanism is used for reporting an error when the called time of the verification model is greater than 0.
In one embodiment, the first restriction removal module is further configured to: determining a root operation stage function from the basic packet; based on a preset identification, searching a program code corresponding to an error reporting mechanism in a root operation stage function; and deleting the program code corresponding to the error reporting mechanism.
In one embodiment, the generation apparatus of the verification platform further includes a second restriction removal module configured to: in the calling interface, modifying an end identifier in a basic packet corresponding to the target verification model; and the end identifier is used for indicating the end of the test case after generating the test sequence corresponding to the target verification model.
In one embodiment, the second restriction removal module is further configured to: setting parameters corresponding to the ending marks as preset values; wherein the preset value indicates that the end mark is invalid.
In one embodiment, the generation apparatus of the verification platform further includes a test verification module, configured to: acquiring a target test case; determining a target verification model to be used from a target verification platform according to the target test case; determining a target test sequence according to the target test case and a target verification model to be used; and verifying the chip corresponding to the target verification model according to the target test sequence.
In one embodiment, the test validation module is further configured to: calling a calling interface corresponding to each target verification model to be used to obtain a test sequence identification set corresponding to the target verification model to be used; and determining a target test sequence matched with the target test case from the test sequence identification set.
For specific limitations of the generation apparatus of the verification platform, reference may be made to the above limitations of the generation method of the verification platform, which are not described herein again. The modules in the generation device of the verification platform can be wholly or partially implemented by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as shown in fig. 6. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless communication can be realized through WIFI, an operator network, NFC (near field communication) or other technologies. The computer program is executed by a processor to implement a method of generating a verification platform. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.
Those skilled in the art will appreciate that the architecture shown in fig. 6 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory and a processor, the memory having a computer program stored therein, the processor implementing the following steps when executing the computer program:
obtaining a verification model applicable to a first operating environment;
adding a calling interface at the initial calling position of the verification model to obtain a target verification model;
instantiating the calling interface in the target verification platform; the target verification platform is a verification platform suitable for the second operation environment;
and calling the target verification model through the calling interface, and integrating the target verification model into the target verification platform.
In one embodiment, the processor, when executing the computer program, further performs the steps of: deleting the program code corresponding to the error reporting mechanism from the basic package corresponding to the verification model; the basic package represents a general library corresponding to the first operating environment, and the error reporting mechanism is used for reporting an error when the called time of the verification model is greater than 0.
In one embodiment, the processor, when executing the computer program, further performs the steps of: determining a root operation stage function from the basic packet; based on a preset identification, searching a program code corresponding to an error reporting mechanism in a root operation stage function; and deleting the program code corresponding to the error reporting mechanism.
In one embodiment, the processor, when executing the computer program, further performs the steps of: in the calling interface, modifying an end identifier in a basic packet corresponding to the target verification model; and the end identifier is used for indicating the end of the test case after generating the test sequence corresponding to the target verification model.
In one embodiment, the processor, when executing the computer program, further performs the steps of: setting parameters corresponding to the ending marks as preset values; wherein the preset value indicates that the end mark is invalid.
In one embodiment, the processor, when executing the computer program, further performs the steps of: acquiring a target test case; determining a target verification model to be used from a target verification platform according to the target test case; determining a target test sequence according to the target test case and a target verification model to be used; and verifying the chip corresponding to the target verification model according to the target test sequence.
In one embodiment, the processor, when executing the computer program, further performs the steps of: calling a calling interface corresponding to each target verification model to be used to obtain a test sequence identification set corresponding to the target verification model to be used; and determining a target test sequence matched with the target test case from the test sequence identification set.
In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of:
obtaining a verification model applicable to a first operating environment;
adding a calling interface at the initial calling position of the verification model to obtain a target verification model;
instantiating the calling interface in the target verification platform; the target verification platform is a verification platform suitable for the second operation environment;
and calling the target verification model through the calling interface, and integrating the target verification model into the target verification platform.
In one embodiment, the computer program when executed by the processor further performs the steps of: deleting the program code corresponding to the error reporting mechanism from the basic package corresponding to the verification model; the basic package represents a general library corresponding to the first operating environment, and the error reporting mechanism is used for reporting an error when the called time of the verification model is greater than 0.
In one embodiment, the computer program when executed by the processor further performs the steps of: determining a root operation stage function from the basic packet; based on a preset identification, searching a program code corresponding to an error reporting mechanism in a root operation stage function; and deleting the program code corresponding to the error reporting mechanism.
In one embodiment, the computer program when executed by the processor further performs the steps of: in the calling interface, modifying an end identifier in a basic packet corresponding to the target verification model; and the end identifier is used for indicating the end of the test case after generating the test sequence corresponding to the target verification model.
In one embodiment, the computer program when executed by the processor further performs the steps of: setting parameters corresponding to the ending marks as preset values; wherein the preset value indicates that the end mark is invalid.
In one embodiment, the computer program when executed by the processor further performs the steps of: acquiring a target test case; determining a target verification model to be used from the target verification platform according to the target test case; determining a target test sequence according to the target test case and the target verification model to be used; and verifying the chip corresponding to the target verification model according to the target test sequence.
In one embodiment, the computer program when executed by the processor further performs the steps of: calling a calling interface corresponding to each target verification model to be used to obtain a test sequence identification set corresponding to the target verification model to be used; and determining a target test sequence matched with the target test case from the test sequence identification set.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in the embodiments provided herein can include at least one of non-volatile and volatile memory. Non-volatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical storage, or the like. Volatile Memory can include Random Access Memory (RAM) or external cache Memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for generating a verification platform, the method comprising:
obtaining a verification model applicable to a first operating environment; the first operating environment is a UVM environment;
deleting the program code corresponding to the error reporting mechanism from the basic package corresponding to the verification model; the basic package represents a general library corresponding to the first operating environment, and the error reporting mechanism is used for reporting an error when the called time of the verification model is greater than the simulation time 0;
adding a calling interface at the initial calling position of the verification model to obtain a target verification model; the initial calling position is the top layer of the verification model;
instantiating the call interface in a target verification platform; the target verification platform is a verification platform suitable for a second operation environment; the verification platform of the second operating environment is an SOC chip system level verification platform;
and calling the target verification model through the calling interface, and integrating the target verification model into the target verification platform.
2. The method of claim 1, wherein deleting the error reporting mechanism from the base package corresponding to the verification model comprises:
determining a root operation stage function from the basic packet;
based on a preset identification, searching a program code corresponding to the error reporting mechanism in the root operation stage function;
and deleting the program code corresponding to the error reporting mechanism.
3. The method of claim 1, wherein after adding a calling interface at a starting calling position of the verification model to obtain a target verification model, the method further comprises:
in the calling interface, modifying an end identifier in a basic packet corresponding to the target verification model; and the end identifier is used for indicating the end of the test case after generating the test sequence corresponding to the target verification model.
4. The method according to claim 3, wherein modifying the corresponding end identifier of the basic packet in the call interface comprises:
setting parameters corresponding to the ending marks as preset values; wherein the preset value indicates that the end flag is invalid.
5. The method of claim 1, wherein instantiating the call interface in a target verification platform comprises:
instantiating the call interface on the top layer of the SOC chip system level verification platform.
6. The method of claim 1, wherein after the invoking the target verification model and integrating the target verification model into the target verification platform via the invocation interface, further comprising:
acquiring a target test case;
determining a target verification model to be used from the target verification platform according to the target test case;
determining a target test sequence according to the target test case and the target verification model to be used;
and verifying the chip corresponding to the target verification model according to the target test sequence.
7. The method according to claim 6, wherein the determining a target test sequence according to the target test case and the target verification model to be used comprises:
calling a calling interface corresponding to each target verification model to be used to obtain a test sequence identification set corresponding to the target verification model to be used;
and determining a target test sequence matched with the target test case from the test sequence identification set.
8. An apparatus for generating a verification platform, the apparatus comprising:
the data acquisition module is used for acquiring a verification model suitable for the first operating environment; the first operating environment is a UVM environment;
the deleting module is used for deleting the program code corresponding to the error reporting mechanism from the basic package corresponding to the verification model; the basic package represents a general library corresponding to the first operating environment, and the error reporting mechanism is used for reporting an error when the called time of the verification model is greater than the simulation time 0;
the interface adding module is used for adding a calling interface at the initial calling position of the verification model to obtain a target verification model; the initial calling position is the top layer of the verification model;
the model instantiation module is used for instantiating the calling interface in a target verification platform; the target verification platform is a verification platform suitable for a second operation environment; the verification platform of the second operating environment is an SOC chip system level verification platform;
and the platform generation module is used for calling the target verification model through the calling interface and integrating the target verification model into the target verification platform.
9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the method of any of claims 1 to 7.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 7.
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