CN112987516A - Method for semiconductor photoetching process - Google Patents
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- CN112987516A CN112987516A CN201911213591.XA CN201911213591A CN112987516A CN 112987516 A CN112987516 A CN 112987516A CN 201911213591 A CN201911213591 A CN 201911213591A CN 112987516 A CN112987516 A CN 112987516A
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7088—Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/708—Construction of apparatus, e.g. environment aspects, hygiene aspects or materials
- G03F7/7085—Detection arrangement, e.g. detectors of apparatus alignment possibly mounted on wafers, exposure dose, photo-cleaning flux, stray light, thermal load
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/24—Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change
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Abstract
A method of semiconductor photoetching technology comprises the steps of judging whether overlay error values of each wafer in a batch of wafers are in a reasonable range or not after the overlay error values are obtained; if the alignment error values are all within the reasonable range, uploading the average value of the alignment error values to a production control system, and using the average value for the compensation value of the alignment error of the next batch of wafers by the production control system; if the overlay error value is not in the reasonable range, the specific wafer corresponding to the overlay error value which is not in the reasonable range needs to be reworked, the overlay error value of the specific wafer is uploaded to a production control system, and the production control system uses the overlay error value of the specific wafer for a compensation value of the overlay error in the process of reworking the specific wafer. The method can avoid averaging the compensation values of the reworked wafer, so that the reworked wafer is optimally compensated, the alignment precision meets the requirement, and the method is simple to operate.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a method of a semiconductor photoetching process.
Background
Photolithography, which is a process of transferring a pattern on a mask plate to a substrate by exposure, is a very important process in a semiconductor manufacturing process and is considered as a core step in the manufacture of large-scale integrated circuits. A series of complex and time-consuming photolithography processes in semiconductor manufacturing are mainly performed by corresponding exposure machines.
In semiconductor fabrication, the exposure process mainly includes three major steps: replacing the substrate on the chuck (stage); aligning the substrate on the chuck; and transferring the pattern on the mask plate to the substrate. The three steps are sequentially and repeatedly carried out on the same chuck.
In recent years, in order to further improve the throughput of exposure apparatuses, various exposure apparatuses having a dual chuck have been developed, and a wafer replacement operation, an alignment operation, and an exposure operation are simultaneously performed by the dual chuck.
There is an exposure machine having a double chuck (twin-stage), comprising: a first chuck and a second chuck for placing a substrate; an alignment detection unit for detecting an alignment mark on the substrate; an optical projection unit for exposing a substrate; the exposure apparatus further comprises two measuring units for measuring the two-dimensional positions of the first chuck and the second chuck, respectively.
When the exposure machine is used for exposing the wafer, the Overlay error (Overlay) is an index for measuring the alignment accuracy of the current layer and the previous layer, when the exposure of the layer is completed, an engineer can measure the Overlay error by using a measuring machine, when the Overlay error exceeds the specification line (Spec) of a product, the rework (rework) is needed to be performed on the current layer of the wafer, namely, the photoresist exposed on the current layer is removed, then new photoresist is spin-coated on the current layer, and then the current layer is exposed again for one time. When the overlay error of the current layer measured by the engineer satisfies the specification line, the batch of wafers can be sent to the next process from the chuck of the exposure machine. Meanwhile, the overlay error value of the current layer is calculated by a certain rule and then stored in a production control system for an optimized compensation value (Optimize) of the overlay error of the wafer of the next batch.
The existing method for reworking wafers still has the condition that the reworked wafers still exceed the specification line.
Disclosure of Invention
The invention aims to solve the technical problem of improving the condition that the existing reworked wafer still exceeds the specification line.
The invention provides a method of a semiconductor photoetching process, which comprises the following steps:
acquiring an overlay error value of each wafer in a batch of wafers;
judging whether the overlay error values are all in a reasonable range;
if the alignment error values are all within the reasonable range, uploading the average value of the alignment error values to a production control system, and using the average value for the compensation value of the alignment error of the next batch of wafers by the production control system; if the overlay error value is not in the reasonable range, the specific wafer corresponding to the overlay error value which is not in the reasonable range needs to be reworked, the overlay error value of the specific wafer is uploaded to a production control system, and the production control system uses the overlay error value of the specific wafer for a compensation value of the overlay error in the process of reworking the specific wafer.
Optionally, the batch of wafers has M wafers, and M is greater than or equal to 10 and less than or equal to 50.
Optionally, each wafer has N overlay error values, where N is greater than or equal to 20 and less than or equal to 200.
Optionally, the N overlay error values of each wafer are weighted and averaged to obtain an on-chip overlay error mean value, and the M on-chip overlay error mean values are weighted and averaged to obtain an average value of the overlay error values.
Optionally, the uploading to the production control system includes: only the average of 1 of the overlay error values is uploaded.
Optionally, the using the average value for the compensation value of the overlay error of the next batch of wafers includes:
when the alignment error of the next batch of wafers is a batch positive error, subtracting the average value from the batch positive error in the correcting process;
and when the alignment error of the next batch of wafers is the batch negative error, adding the average value to the batch negative error during correction.
Optionally, the reasonable range is X% of the critical dimension of the manufactured semiconductor device, and the absolute value of X is greater than or equal to 0 and less than or equal to 10.
Optionally, the overlay error values all include within the reasonable range:
and the absolute values of the overlay error values are less than or equal to X%.
Optionally, the misalignment error value includes, if not within the reasonable range:
at least one overlay error value has an absolute value greater than the X%.
Optionally, the wafer corresponding to the overlay error value larger than X% is the specific wafer, the number of the specific wafers is Q, and Q is greater than or equal to 1 and less than or equal to M.
Optionally, the uploading the overlay error value of the specific wafer to a production control system includes: and uploading the Q in-chip overlay error mean values, wherein the Q in-chip overlay error mean values correspond to the Q specific wafers one by one.
Optionally, the using the overlay error value of the specific wafer for the compensation value of the overlay error in the specific wafer rework process includes:
determining the sequence of Q pieces of specific wafers, and recording as a Z-th piece of specific wafer, wherein Z is more than or equal to 1 and less than or equal to Q;
when the alignment error of the reworked Z-th specific wafer is the Z-th positive error, subtracting the average value of the alignment errors in the Z-th wafer from the Z-th positive error in the correction process;
and when the alignment error of the reworked Z-th specific wafer is the Z-th negative error, adding the Z-th positive error to the Z-th intra-wafer alignment error mean value during correction.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the method of the semiconductor photoetching process comprises the steps of obtaining an alignment error value of each wafer in a batch of wafers, and judging whether the alignment error values are all in a reasonable range; if the alignment error values are all within the reasonable range, uploading the average value of the alignment error values to a production control system, and using the average value for the compensation value of the alignment error of the next batch of wafers by the production control system; if the overlay error value is not in the reasonable range, the specific wafer corresponding to the overlay error value which is not in the reasonable range needs to be reworked, the overlay error value of the specific wafer is uploaded to a production control system, and the production control system uses the overlay error value of the specific wafer for a compensation value of the overlay error in the process of reworking the specific wafer. The method can avoid averaging the compensation value of the reworked wafer, so that the reworked wafer is optimally compensated, the alignment precision meets the requirement, and the method is simple to operate and avoids the problems of misoperation, data transmission failure and the like caused by manual operation.
Drawings
FIG. 1 is a schematic flow chart of a method of semiconductor photolithography according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an overlay mark according to an embodiment of the present invention.
Detailed Description
As mentioned in the background, the existing rework method for wafers still exceeds the specification line.
Research finds that overlay errors of wafers exposed on the same chuck are large due to changes of a previous process or deformation of individual wafers, compensation values of the wafers on the same chuck are averaged when the wafers are directly reworked due to inconsistent behaviors of the wafers exposed on the same chuck, and accordingly the wafers needing to be reworked are not optimally compensated; the reworked wafer may continue to exceed the gauge line. In one embodiment, to solve the above problem, the metrology values of the rework wafers need to be individually distinguished and re-sent (resend) to the overlay compensation system, so that the rework wafers are optimally compensated, which is time-consuming and complex, and the manual operation is prone to manual errors, resulting in a failure of re-sending.
Therefore, the invention provides a semiconductor photoetching process method, which comprises the steps of judging whether alignment error values of each wafer in a batch of wafers are in a reasonable range or not after the alignment error values are obtained; if the alignment error values are all within the reasonable range, uploading the average value of the alignment error values to a production control system, and using the average value for the compensation value of the alignment error of the next batch of wafers by the production control system; if the overlay error value is not in the reasonable range, the specific wafer corresponding to the overlay error value which is not in the reasonable range needs to be reworked, the overlay error value of the specific wafer is uploaded to a production control system, and the production control system uses the overlay error value of the specific wafer for a compensation value of the overlay error in the process of reworking the specific wafer. The method can avoid averaging the compensation value of the reworked wafer, so that the reworked wafer is optimally compensated, the alignment precision meets the requirement, and the method is simple to operate and avoids the problems of misoperation, data transmission failure and the like caused by manual operation.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In describing the embodiments of the present invention in detail, the drawings are not to be considered as being enlarged partially in accordance with the general scale, and the drawings are only examples, which should not be construed as limiting the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
FIG. 1 is a flow chart illustrating a method of semiconductor photolithography according to an embodiment of the present invention.
Referring to fig. 1, a method of semiconductor lithography process according to an embodiment of the present invention includes the steps of:
step S101, obtaining an overlay error value of each wafer in a batch of wafers;
step S102, judging whether the overlay error values are all in a reasonable range;
step S103, if the alignment error values are all in the reasonable range, uploading the average value of the alignment error values to a production control system, and using the average value in the compensation value of the alignment error of the next batch of wafers by the production control system; if the overlay error value is not in the reasonable range, the specific wafer corresponding to the overlay error value which is not in the reasonable range needs to be reworked, the overlay error value of the specific wafer is uploaded to a production control system, and the production control system uses the overlay error value of the specific wafer for a compensation value of the overlay error in the process of reworking the specific wafer.
The foregoing process is described in detail below.
Step S101 is performed to obtain an overlay error value of each wafer in a batch of wafers.
The batch of wafers are coated with a photoresist layer, and the photoresist layer is exposed and developed. The batch of wafers is provided with M wafers, and M is more than or equal to 10 and less than or equal to 50.
After the wafer is exposed and developed, an overlay measurement is required to obtain an overlay accuracy or an overlay error value of the wafer. Overlay error is the deviation of alignment between a layer and a previous layer, each layer having an alignment mark (mark), and a current layer alignment mark (mark) formed after exposure of the layer is measured by measuring the deviation between the current layer alignment mark (mark) and the previous layer alignment mark (mark). If the deviation value is too large, the current layer is washed away, the exposure is carried out again (rework), and the deviation value of the generated current layer alignment mark (mark) and the previous layer alignment mark (mark) is measured again until the deviation value meets the requirement. Generally, the overlay measurement is performed on an overlay measurement machine. In a specific embodiment, referring to fig. 2, fig. 2 shows an overlay mark according to an embodiment of the present invention, where the overlay mark includes a front layer alignment mark 201 and a current layer alignment mark 202, the current layer alignment mark 202 is a block pattern, the front layer alignment mark 201 is four straight line patterns, and is located around the block pattern, and when overlay measurement is performed, overlay error values can be obtained by measuring distances between the current layer alignment mark 202 and the front layer alignment mark 201 (such as X1, X2, Y1, and Y2 in fig. 2), where the specific overlay error values include an X-direction overlay error value and a Y-direction overlay error value, the X-direction overlay error value is generally (X1-X2)/2, and the Y-direction overlay error value is generally (Y1-Y2)/2.
In a specific embodiment, each wafer may have N front layer alignment marks 201 and corresponding current layer alignment marks 202, after performing overlay measurement, each wafer correspondingly has N overlay error values, where N is greater than or equal to 20 and less than or equal to 200, specifically, N may be 20, 40, 50, 100, 150, or 200, and the N overlay error values are (weighted) averaged to obtain an overlay error value of each wafer (or an average value of the in-wafer overlay error values of each wafer). Specifically, referring to fig. 2, the front layer of one wafer has 45 front layer alignment marks (marks) 201, and the current layer also forms 45 current layer alignment marks (marks) 202, and through overlay measurement, a wafer can correspondingly obtain 45 overlay error values, and the 45 overlay error values are averaged (weighted) to obtain an overlay error value of each wafer (or an average value of the overlay error values in the wafer sheet of each wafer), for example, [ (X01-X02) + (X03-X04) + … + (X89-X90) ]/90 is an overlay error value in the X direction of a wafer (average value of the overlay error in the X direction), and [ (Y01-Y02) + (Y03-Y04) + … + (Y89-Y90) ]/90 is an overlay error value in the Y direction of a wafer (average value of the overlay error in the Y direction).
In other embodiments, several wafers in a batch of wafers may be selected for overlay measurement during overlay measurement, so as to obtain an overlay error value for each wafer. In one embodiment, when a lot of wafers has 25 wafers, 1, 2, 5, 10 or 20 wafers may be selected for overlay measurement, and overlay error values corresponding to the wafers are obtained.
And S102, judging whether the overlay error values are all in a reasonable range.
The reasonable range is X% of the critical dimension of the manufactured semiconductor device, the absolute value of X is greater than or equal to 0 and less than or equal to 10, and the absolute value of X can be 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10. In a specific embodiment, if the critical dimension of the device is 50nm and the absolute value of X is 8, then the reasonable range is 4 nm.
In one embodiment, the overlay error values each include within the reasonable range: the absolute values of the overlay error values are all less than or equal to X% (where X% refers to X% of the critical dimension of the manufactured semiconductor device).
The overlay error values being outside the reasonable range include: at least one overlay error value has an absolute value greater than the X%. The wafer corresponding to the alignment error value larger than X% is the specific wafer, the number of the specific wafers is Q, and Q is larger than or equal to 1 and smaller than or equal to M. In a specific embodiment, after overlay measurement is performed on all 25 wafers in a batch of wafers, if the absolute value of the overlay error of 5 wafers is greater than X%, the number Q of the specific wafer is 5.
For example, if a reasonable range is defined as 4nm, M is 25, N is 45, and if the overlay error values [ (X01-X02) + (X03-X04) + … + (X89-X90) ]/90 and [ (Y01-Y02) + (Y03-Y04) + … + (Y89-Y90) ]/90 of each of 25 wafers are less than or equal to 4nm, the overlay error values are determined to be within the reasonable range; if the overlay error value [ (X01-X02) + (X03-X04) + … + (X89-X90) ]/90 or [ (Y01-Y02) + (Y03-Y04) + … + (Y89-Y90) ]/90 of one of the 25 wafers is more than 8%, judging that the overlay error value is out of the reasonable range.
The determination of whether the overlay error values are all within a reasonable range can be performed on existing overlay analysis systems.
Step S103 is carried out, if the alignment error values are all in the reasonable range, the average value of the alignment error values is uploaded to a production control system, and the production control system uses the average value as a compensation value of the alignment error of the next batch of wafers; if the overlay error value is not in the reasonable range, the specific wafer corresponding to the overlay error value which is not in the reasonable range needs to be reworked, the overlay error value of the specific wafer is uploaded to a production control system, and the production control system uses the overlay error value of the specific wafer for a compensation value of the overlay error in the process of reworking the specific wafer.
In an embodiment, the N overlay error values of each wafer are weighted and averaged to obtain an on-chip overlay error mean, and the M on-chip overlay error mean values are weighted and averaged to obtain an average of the overlay error values.
Specifically, a batch of wafers, for example, 25 wafers, are tested by extracting 5 wafers, and then the average value of the overlay error values of the batch of wafers is obtained by averaging 45 × 5 — 225 overlay error values, or the overlay error value of each wafer of the 5 wafers (or the average value of the overlay error values in each wafer) is obtained first, and then the average value of the overlay error values is obtained by weighted averaging the average values of the overlay error values in the 5 wafers. In other embodiments, the average value of the overlay error values may be calculated by other algorithms, such as different weights of alignment marks (marks) in different regions of each wafer, so that the average value of the overlay error values is the average value of the weighted overlay error values.
In one embodiment, the uploading to a production control system comprises: only the average of 1 of the overlay error values is uploaded. The using the average value for the compensation value of the overlay error of the next batch of wafers comprises: when the alignment error of the next batch of wafers is a batch positive error, subtracting the average value from the batch positive error in the correcting process; and when the alignment error of the next batch of wafers is the batch negative error, adding the average value to the batch negative error during correction.
In one embodiment, the uploading the overlay error value of the specific wafer to a production control system includes: and uploading the Q in-chip overlay error mean values, wherein the Q in-chip overlay error mean values correspond to the Q specific wafers one by one. Specifically, when the number of the specific wafers Q is 5, 5 in-chip overlay error mean values are uploaded, where the 5 in-chip overlay error mean values correspond to the 5 specific wafers one to one, and include a 1 st in-chip error mean value, a 2 nd in-chip error mean value, a 3 rd in-chip error mean value, a 4 th in-chip error mean value, and a 5 th in-chip error mean value.
For example, defining a reasonable range of 4nm, where M is 25, N is 45, assuming that 5 of 25 wafers are extracted to test an overlay error value, if the overlay error values [ (X01-X02) + (X03-X04) + … + (X89-X90) ]/90 and [ (Y01-Y02) + (Y03-Y04) + … + (Y89-Y90) ]/90 of each of the 5 wafers tested are less than or equal to 4nm, determining that the overlay error values of the 25 wafers in the batch are all in the reasonable range, and meanwhile, averaging the overlay error values of the 5 wafers tested (denoted as X _ AVG and Y _ AVG), uploading X _ AVG and Y _ AVG to a production control system, and using X _ AVG and avy _ AVG as overlay error compensation values of the next batch of wafers; if the tested 5 wafers have an overlay error value [ (X01-X02) + (X03-X04) + … + (X89-X90) ]/90 or [ (Y01-Y02) + (Y03-Y04) + … + (Y89-Y90) ]/90 of more than 8%, it is determined that the batch of 25 wafers is out of a reasonable range, and then the overlay error values are retested for each of the 25 wafers, respectively denoted as X _ 01-X _25 and Y _ 01-Y25, and then when X _ xx or Y _ xx is greater than 4nm, rework time is required for the corresponding wafer numbered xx, for example xx is 02, and the 2 nd wafer needs rework, and X _02 and Y _02 are uploaded to the production control system, and X _02 and Y _02 are used as the overlay error compensation values for the 2 nd wafer.
The using the overlay error value of the specific wafer for the compensation value of the overlay error in the specific wafer rework process includes:
determining the sequence of Q specific wafers, and marking as a Z specific wafer, wherein Z is more than or equal to 1 and less than or equal to Q, specifically, when 5 specific wafers exist, marking the 5 specific wafers as a 1 st specific wafer, a 2 nd specific wafer, a 3 rd specific wafer, a 4 th specific wafer and a 5 th specific wafer in sequence;
and when the alignment error of the reworked Z-th specific wafer is the Z-th positive error, subtracting the average value of the alignment errors in the Z-th wafer from the Z-th positive error in the correction process. Specifically, when the overlay error of the 1 st specific wafer is the 1 st positive error, subtracting the 1 st positive error from the 1 st intra-wafer overlay error mean value during correction; when the alignment error of the 2 nd specific wafer is the 2 nd positive error, subtracting the average value of the alignment errors in the 2 nd wafer from the 2 nd positive error in the correction process; …, respectively; when the overlay error of the 5 th specific wafer is the 5 th positive error, subtracting the 5 th positive error from the 5 th intra-wafer overlay error mean value in the correction process.
And when the alignment error of the reworked Z-th specific wafer is the Z-th negative error, adding the Z-th positive error to the Z-th intra-wafer alignment error mean value during correction. Specifically, when the alignment error of the 1 st specific wafer is the 1 st negative error, the 1 st negative error is added to the 1 st average alignment error value during correction; when the alignment error of the 2 nd specific wafer is the 2 nd negative error, adding the 2 nd negative error to the average value of the alignment errors in the 2 nd wafer during correction; …, respectively; and when the alignment error of the 5 th specific wafer is the 5 th negative error, adding the 5 th negative error to the average value of the alignment errors in the 5 th wafer during correction.
As shown in FIG. 2, when (X1-X2)/2 and (Y1-Y2)/2 are greater than 0, positive errors are recorded, and vice versa, negative errors are recorded.
Still taking the 2 nd wafer as an example, when X _02 corresponding to the 2 nd wafer is larger than 0, during rework (note rework as second exposure, and before rework is first exposure), the production control system will control the movement of the alignment part of the exposure machine, where the corresponding compensation value is X _02, that is, the difference between the movement value of the exposure machine during the second exposure and the movement value during the first exposure is X _02, that is, the movement value of the alignment part during the second exposure is the sum or subtraction of the movement value of the first exposure and X _ 02.
The method can avoid averaging the compensation value of the reworked wafer, so that the reworked wafer is optimally compensated, the alignment precision meets the requirement, and the method is simple to operate and avoids the problems of misoperation, data transmission failure and the like caused by manual operation.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.
Claims (12)
1. A method of semiconductor lithography processing, comprising:
acquiring an overlay error value of each wafer in a batch of wafers;
judging whether the overlay error values are all in a reasonable range;
if the alignment error values are all within the reasonable range, uploading the average value of the alignment error values to a production control system, and using the average value for the compensation value of the alignment error of the next batch of wafers by the production control system; if the overlay error value is not in the reasonable range, the specific wafer corresponding to the overlay error value which is not in the reasonable range needs to be reworked, the overlay error value of the specific wafer is uploaded to a production control system, and the production control system uses the overlay error value of the specific wafer for a compensation value of the overlay error in the process of reworking the specific wafer.
2. The method of claim 1, wherein the batch of wafers has M wafers, wherein M is greater than or equal to 10 and less than or equal to 50.
3. The method of claim 2, wherein each wafer has N overlay error values, wherein N is greater than or equal to 20 and less than or equal to 200.
4. The method as claimed in claim 3, wherein the weighted average of the N overlay error values for each wafer is a mean value of the overlay error values in a wafer, and the weighted average of the mean values of the overlay error values in M wafers is a mean value of the overlay error values.
5. The method of claim 4, wherein the uploading to a production control system comprises: only the average of 1 of the overlay error values is uploaded.
6. The method of claim 5, wherein using the average value for a compensation value for overlay error for a next wafer lot comprises:
when the alignment error of the next batch of wafers is a batch positive error, subtracting the average value from the batch positive error in the correcting process;
and when the alignment error of the next batch of wafers is the batch negative error, adding the average value to the batch negative error during correction.
7. The method of claim 6, wherein the reasonable range is X% of the critical dimension of the manufactured semiconductor device, and the absolute value of X is greater than or equal to 0 and less than or equal to 10.
8. The method of claim 7, wherein the overlay error values are each within the reasonable range comprises:
and the absolute values of the overlay error values are less than or equal to X%.
9. The method of claim 8, wherein the absence of the overlay error value from the reasonable range comprises:
at least one overlay error value has an absolute value greater than the X%.
10. The method as claimed in claim 9, wherein the wafer corresponding to the overlay error value having an absolute value greater than X% is the specific wafer, the number of the specific wafer is Q, and Q is greater than or equal to 1 and less than or equal to M.
11. The method as claimed in claim 10, wherein uploading the overlay error value for the specific wafer to a production control system comprises: and uploading the Q in-chip overlay error mean values, wherein the Q in-chip overlay error mean values correspond to the Q specific wafers one by one.
12. The method as claimed in claim 11, wherein the using the overlay error value of the specific wafer for the compensation value of the overlay error during the specific wafer rework comprises:
determining the sequence of Q pieces of specific wafers, and recording as a Z-th piece of specific wafer, wherein Z is more than or equal to 1 and less than or equal to Q;
when the alignment error of the reworked Z-th specific wafer is the Z-th positive error, subtracting the average value of the alignment errors in the Z-th wafer from the Z-th positive error in the correction process;
and when the alignment error of the reworked Z-th specific wafer is the Z-th negative error, adding the Z-th positive error to the Z-th intra-wafer alignment error mean value during correction.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN112987516B (en) | 2023-01-24 |
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