CN112968818A - Train Ethernet abnormal data detection system, equipment and method - Google Patents
Train Ethernet abnormal data detection system, equipment and method Download PDFInfo
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Abstract
The invention discloses a train Ethernet abnormal data detection system, equipment and a method, wherein the train Ethernet abnormal data detection system comprises: the system comprises a main processor, a switch, terminal equipment and a server processing unit, wherein the main processor is integrated by an ARM processing unit and an FPGA processing unit, the FPGA processing unit is in communication connection with the switch and the terminal equipment through an Ethernet communication unit and is also in communication connection with the ARM processing unit, the ARM processing unit is in communication connection with the switch through the Ethernet communication unit, and the switch is in communication connection with the server processing unit. The invention reduces the complexity of hardware circuit, improves the reliability of the system, reduces the extra expense of CPU, ensures the real-time and accuracy of data processing and reduces the misjudgment rate.
Description
Technical Field
The invention relates to the technical field of train communication, in particular to a train Ethernet abnormal data detection system, equipment and method.
Background
In order to meet the requirement of large data volume transmission, Ethernet communication is often adopted between the train server and the terminal equipment, and by adopting the Ethernet communication, although the data transmission rate and the data transmission quantity are improved, the network security problem of the train Ethernet is more prominent.
At present, in order to ensure the network security of the train ethernet, abnormal data in the network data is often detected in the network data transmission process, and the abnormal data is usually detected and filtered by means of rule setting, black and white list filtering, expert manual detection and the like.
However, in the prior art, the conventional abnormal data detection and filtering method not only has the problems of misjudgment and long time consumption for judgment, but also has high cost of a CPU (central processing unit) and influences the interactive performance of a computer.
Disclosure of Invention
The embodiment of the application provides a train Ethernet abnormal data detection system, equipment and a method, which are used for at least solving the technical problems that misjudgment exists in abnormal data detection, time consumption is long in judgment, and computer interaction performance is influenced in the prior art.
In a first aspect, an embodiment of the present application provides a train ethernet abnormal data detection system, including: a main processor, a switch, a terminal device and a server processing unit, wherein,
the main processor is integrated by an ARM processing unit and an FPGA processing unit;
the FPGA processing unit is in communication connection with the switch and the terminal equipment through the Ethernet communication unit, and is also in communication connection with the ARM processing unit, and the FPGA processing unit is used for detecting and filtering abnormal network data in the network data of the switch and the terminal equipment according to the judgment vector and sending the network data and the abnormal network data to the ARM processing unit;
the ARM processing unit is in communication connection with the switch through the Ethernet communication unit, and the switch is in communication connection with the server processing unit and used for sending the network data and the abnormal data to the server processing unit and sending the judgment vector to the FPGA processing unit;
the server processing unit is used for training network data, generating an abnormal data detection model and a judgment vector, updating the judgment vector based on the abnormal data detection model and the abnormal data, and sending the updated judgment vector to the ARM processing unit.
In some embodiments, the ARM processing unit is further configured to configure the FPGA processing unit according to the updated decision vector.
In some of these embodiments, the FPGA processing unit comprises: a multipath selection module and an anomaly data detection module, wherein,
the multi-path selection module is in communication connection with the switch through the Ethernet communication unit, and is also in communication connection with the abnormal data detection module and used for sending the network data to the abnormal data detection module when the data of the switch is received as the network data; when the data of the receiving switch is configuration data, namely updated judgment vectors, the configuration data is sent to the ARM processing unit;
the abnormal data detection module is in communication connection with the terminal equipment through the Ethernet communication unit and is used for sending the network data of the switch and the terminal equipment to the ARM processing unit, detecting and filtering abnormal network data in the network data according to the judgment vector, and sending the abnormal network data to the ARM processing unit.
In some of these embodiments, the FPGA processing unit further comprises: a data storage module, wherein,
the data storage module is in communication connection with the abnormal data detection module and is used for storing network data and abnormal network data of the switch and the terminal equipment.
In some embodiments, the method for detecting abnormal data in the FPGA processing unit specifically includes:
analyzing network data of the switch and the terminal equipment into matrix vector data;
multiplying the matrix vector data by the judgment vector, and if the multiplication result is 1, sending abnormal network data in the network data to an ARM processing unit; and if the multiplication result is 0, sending the normal network data in the network data to the terminal equipment or the switch through the Ethernet communication unit.
In some of these embodiments, further comprising:
the wireless communication unit, the FPGA processing unit and the ARM processing unit are in communication connection with the data center system through the wireless communication unit and are used for sending the network data and the abnormal data to the data center system.
In some of these embodiments, further comprising:
and the monitoring unit is in communication connection with the FPGA processing unit and the ARM processing unit and is used for monitoring the running states of the FPGA processing unit and the ARM processing unit in real time, generating and sending abnormal signals to the FPGA processing unit and the ARM processing unit when the running states are abnormal, and resetting the FPGA processing unit and the ARM processing unit.
In a second aspect, an embodiment of the present application provides a train ethernet abnormal data detection device, including the train ethernet abnormal data detection system described above.
In a third aspect, an embodiment of the present application provides a train ethernet abnormal data detection method, which is applied to the train ethernet abnormal data detection system as claimed in the claims, and includes:
s1: the FPGA processing unit sends the network data of the terminal equipment and the switch to the server processing unit through the ARM processing unit and the switch in sequence;
s2: the server processing unit trains network data to generate an abnormal data detection model and a judgment vector, and sends the judgment vector to the FPGA processing unit through the switch and the ARM processing unit in sequence;
s3: the FPGA processing unit detects and filters abnormal network data in the network data according to the judgment vector, sends normal network data in the network data to terminal equipment or a switch, and sends the abnormal network data to the server processing unit through the ARM processing unit and the switch in sequence;
s4: the server processing unit updates the judgment vector generated at step S2 based on the abnormal data detection model and the abnormal network data, and repeatedly executes steps S2 to S4.
In some embodiments, between the step S2 and the step S3, the method further includes:
when the data received by the FPGA processing unit from the switch is network data, executing the step S3;
when the data received by the FPGA processing unit from the switch is the configuration data, i.e., the updated judgment vector, the FPGA processing unit is configured, and step S3 is executed.
The invention has the technical effects or advantages that:
the invention provides a train Ethernet abnormal data detection system, which adopts a main processor integrating an ARM processing unit and an FPGA processing unit, wherein an Ethernet communication module is directly hung on the FPGA processing unit, so that the problems that the interaction performance of a computer is influenced due to the high cost of a CPU (Central processing Unit) during abnormal data detection are solved, the complexity of a hardware circuit is reduced, the reliability of the system is improved, and the extra cost of the CPU is reduced based on the characteristic that the FPGA processing unit processes data in parallel, so that the real-time performance and the accuracy of data processing are ensured; and abnormal network data are detected through the FPGA processing unit and the judgment vector, the network data are sent to the server processing unit through the ARM processing unit, the judgment vector is updated, the reliability of the system is guaranteed, and the misjudgment rate is reduced.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.
Fig. 1 is a block diagram of a train ethernet abnormal data detection system according to an embodiment of the present invention;
fig. 2 is a data flow diagram of a train ethernet abnormal data detection system according to an embodiment of the present invention;
fig. 3 is a hardware configuration diagram of a train ethernet abnormal data detection system according to an embodiment of the present invention;
FIG. 4 is a flowchart of a method for detecting abnormal Ethernet data of a train according to an embodiment of the present invention;
in the above figures:
1. a main processor; 11. an ARM processing unit; 12. an FPGA processing unit; 121. a multipath selection unit; 122. an abnormal data detection module; 123. a data storage module; 2. a switch; 3. a terminal device; 4. a server processing unit; 5. a monitoring unit; 6. an Ethernet communication unit; 7. a wireless communication unit.
Detailed Description
In order to make the technical solutions of the present invention better understood by those skilled in the art, the present invention will be further described in detail with reference to the accompanying drawings and the detailed description. Although embodiments of the invention are disclosed in the accompanying drawings, it should be understood that the invention can be embodied in any form and should not be construed as limited to the embodiments set forth herein.
In the description of the present invention, it is to be understood that the terms "inside", "outside", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. The terms "first," "second," "third," and the like, herein are used to describe various elements, components, regions, layers and/or sections, but only to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Terms such as "first," "second," "third," and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the term "connected" is to be interpreted broadly, e.g. as a fixed connection, a detachable connection, or an integral connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The invention provides a train Ethernet abnormal data detection method, aiming at solving the technical problems of misjudgment, long time consumption judgment and influence on the interaction performance of a computer in the prior art of detecting abnormal data, wherein an ARM processing unit and an FPGA processing unit are integrated to form a main processor, and an Ethernet communication module is directly hung on the FPGA processing unit, so that the problems that the interaction performance of the computer is influenced due to the high cost of a CPU in the abnormal data detection process are solved, the complexity of a hardware circuit is reduced, the reliability of a system is improved, and the extra cost of the CPU is reduced based on the characteristic that the FPGA processing unit processes data in parallel, and the real-time performance and the accuracy of data processing are ensured; and abnormal network data are detected through the FPGA processing unit and the judgment vector, the network data are sent to the server processing unit through the ARM processing unit, the judgment vector is updated, the reliability of the system is guaranteed, and the misjudgment rate is reduced.
The technical solution of the present invention will be described in detail below with reference to the specific embodiments and the accompanying drawings.
The embodiment relates to a train Ethernet abnormal data detection system, which comprises a main processor 1, an exchanger 2, a terminal device 3 and a server processing unit 4, wherein,
the main processor 1 is integrated by an ARM processing unit 11 and an FPGA processing unit 12;
the FPGA processing unit 12 is in communication connection with the switch 2 and the terminal device 3 through the Ethernet communication unit 6, and is also in communication connection with the ARM processing unit 11, and is used for detecting and filtering abnormal network data in the network data of the switch 2 and the terminal device 3 according to the judgment vector, and sending the network data and the abnormal network data to the ARM processing unit 11;
the ARM processing unit 11 is in communication connection with the switch 2 through the Ethernet communication unit 6, and the switch 2 is in communication connection with the server processing unit 4 and used for sending the network data and the abnormal data to the server processing unit 4 and sending the judgment vector to the FPGA processing unit 12;
the server processing unit 4 is configured to train network data, generate an abnormal data detection model and a judgment vector, update the judgment vector based on the abnormal data detection model and the abnormal data, and send the updated judgment vector to the ARM processing unit 11.
According to the train Ethernet abnormal data detection system provided by the embodiment, the ARM processing unit and the FPGA processing unit are integrated to form the main processor, and the Ethernet communication module is directly hung on the FPGA processing unit, so that the problems that the interaction performance of a computer is influenced due to the high cost of a CPU (central processing unit) during abnormal data detection are solved, the complexity of a hardware circuit is reduced, the reliability of the system is improved, the extra cost of the CPU is reduced based on the characteristic that the FPGA processing unit processes data in parallel, and the real-time performance and the accuracy of data processing are guaranteed; and abnormal network data are detected through the FPGA processing unit and the judgment vector, the network data are sent to the server processing unit through the ARM processing unit, the judgment vector is updated, the reliability of the system is guaranteed, and the misjudgment rate is reduced.
Referring to fig. 1 and fig. 3, the train ethernet abnormal data detection system provided in this embodiment includes: the system comprises a main processor 1, an exchanger 2, a terminal device 3, a server processing unit 4, a monitoring unit 5, an Ethernet communication unit 6 and a wireless communication unit 7, wherein the main processor 1 is respectively in communication connection with the exchanger 2 and the terminal device 3 through the Ethernet communication unit 6, the exchanger 2 is in communication connection with the server processing unit 4, the main processor 1 is in communication connection with a data center system through the wireless communication unit 7, and the monitoring unit 5 is in communication connection with the main processor 1. Referring to fig. 2, the data flow of the ethernet anomaly data detection system based on the train includes 4 data flows, specifically as follows:
(1) data stream 1
Data flow 1 is a bidirectional data flow: from the switch 2 to the terminal device 3, and from the terminal device 3 to the switch 2, in the FPGA processing unit 12, abnormal network data detection is performed on the data stream 1, and if there is an abnormal network number, counting and filtering are performed, and the FPGA processing unit 12 includes a data analysis engine that analyzes the network data according to a dynamically defined mode to determine whether there is abnormal network data in the network data.
(2) Data stream 2
In the FPGA processing unit 12, the abnormal network data is preprocessed and then reported to the ARM processing unit 11.
(3) Data stream 3
The ARM processing unit 11 configures the FPGA processing unit 12.
(4) Data stream 4
The data stream 4 is a bidirectional data stream, the ARM processing unit 11 processes and packages the network data uploaded by the FPGA processing unit 12 and sends the network data to the server processing unit 4, the server processing unit 4 performs unified processing on the acquired network data or abnormal network data to generate an abnormal data detection model and a judgment vector, the judgment vector is updated according to the abnormal network data and the abnormal data detection model, the updated judgment vector is sent to the ARM processing unit 11, and finally the judgment vector in the FPGA processing unit 12 is updated.
Specifically, with reference to fig. 1 and fig. 3, the main processor 1 is connected to the switch 2 and the terminal device 3 through the ethernet communication unit 6, in this embodiment, the number of the ethernet communication units 6 is two, the ethernet communication unit 6 may be an ethernet PHY, each ethernet communication unit 6 is provided with a data receiving ethernet interface and a data transmitting ethernet interface, which are used for receiving and transmitting data, and the two ethernet interfaces, one in and one out, are arranged to be connected to the ethernet network, so that the original network topology structure is not changed, the use is convenient and flexible, and the effect of a "hardware firewall" is achieved.
Specifically, referring to fig. 1 to 3, the main processor 1 is integrated by an ARM processing unit 11 and an FPGA processing unit 12, in this embodiment, the main processor 1 employs an SOC chip, wherein, the ARM processing unit 11 is connected with the switch 2 through the Ethernet communication unit 6 in a communication way, the switch 2 is connected with the server processing unit 4 through the Ethernet communication unit 6 in a communication way, more specifically, the ARM processing unit 11 is connected with the switch 2 through the data transmission interface of the Ethernet communication unit 6 in a communication way, the FPGA processing unit 12 is respectively connected with the switch 2 and the terminal device 3 through the Ethernet communication unit 6 in a communication way, the FPGA processing unit 12 is also connected with the ARM processing unit in a communication way, in the embodiment, the FPGA processing unit 12 is communicatively connected to the ARM processing unit 11 through an AXI bus, by adopting the AXI bus, a larger communication bandwidth between the FPGA processing unit 12 and the ARM processing unit 11 is ensured. The FPGA processing unit 12 is used for detecting and filtering abnormal network data in the network data of the switch 2 and the terminal device 3 according to the judgment vector, and sending the network data and the abnormal network data to the ARM processing unit 11; the ARM processing unit 11 is configured to send the network data and the abnormal data to the server processing unit 4, and send the determination vector to the FPGA processing unit 12.
More specifically, referring to fig. 3, the FPGA processing unit 12 includes a multipath selection module 121, an abnormal data detection module 122 and a data storage unit 123, wherein the multipath selection module 121 is communicatively connected to the ARM processing unit 11 and is also communicatively connected to the switch 2 through the ethernet communication unit 6, more specifically, the multipath selection module 121 is communicatively connected to the switch 2 through a data receiving interface of the ethernet communication unit 6, the abnormal data detection module 122 is communicatively connected to the multipath selection module 131 and the ARM processing unit 11 and is also communicatively connected to the terminal device 3 through the ethernet communication unit 6, specifically, the abnormal data detection module 122 is communicatively connected to the terminal device 3 through a data transmitting interface and a data receiving interface of the ethernet communication unit 6, the data storage module 123 is communicatively connected to the abnormal data detection module 122, and the multipath selection module 121 is configured to, when data of the receiving switch 2 is network data, sending the network data to the abnormal data detection module 122; when the data of the receiving switch 2 is the configuration data, i.e. the updated judgment vector, the configuration data is sent to the ARM processing unit 11; the abnormal data detection module 122 is configured to send the network data of the switch 2 and the terminal device 3 to the ARM processing unit 11, detect and filter abnormal network data in the network data according to the judgment vector, and send the abnormal network data to the ARM processing unit 11; the data storage module 123 is configured to store the network data and the abnormal network data of the switch 2 and the terminal device 3, and specifically, the main processor 1 is externally connected with a DDR4, and is communicatively connected to the FPGA processing unit 12, and configured to store the network data and the abnormal network data of the switch 2 and the terminal device 3. In this embodiment, the main processor 1 is further externally connected with another DDR4, which is in communication connection with the ARM processing unit 12 and is used for system operation and algorithm operation. The main processor 1 is also provided with an eMMC interface storage chip which is used for storing data and has the size of 32GB, and the main processor 1 is also provided with a NorFlash which has the space size of 32MB and is used for storing a mirror image and a file system of an operating system.
In this embodiment, the method for detecting abnormal data in the FPGA processing unit 12 specifically includes:
analyzing the network data of the switch 2 and the terminal equipment 3 into matrix vector data;
multiplying the matrix vector data by the judgment vector, and if the multiplication result is 1, sending abnormal network data in the network data to the ARM processing unit 11; if the multiplication result is 0, normal network data in the network data is sent to the terminal device 3 or the switch 2 through the ethernet communication unit 6. In the present embodiment, when abnormal data is detected, the abnormal data is stored to the data storage module 123. In this embodiment, the parallel processing mechanism based on the FPGA processing unit 12 can accelerate the algorithm, increase the determination speed, and simultaneously, do not bring extra overhead to the CPU and do not affect the interactive performance of the computer.
In this embodiment, the AXI bus is used as a data interaction channel of the ARM processing unit 11 and the FPGA processing unit 12, and the channel is logically divided into three parts, which are specifically as follows:
(a) configuring a channel: the ARM processing unit 11 configures the abnormal data detection module 122 in the FPGA processing unit 12;
(b) abnormal data uplink channel: the abnormal data detection module 122 in the FPGA processing unit 12 detects the abnormal data, simply preprocesses the abnormal data, reports the abnormal data to the ARM processing unit 11, and uploads the abnormal data to the server processing unit 4 after being processed by the ARM processing unit 11.
(c) The ARM processing unit 11 uplink/downlink channel: for transmitting uplink and downlink IP data between the ARM processing unit 11 and the ethernet communication unit 6.
Specifically, referring to fig. 2 and 3, the server processing unit 4 is configured to train network data, generate an abnormal data detection model and a judgment vector, update the judgment vector based on the abnormal data detection model and the abnormal data, and send the updated judgment vector to the ARM processing unit. In this embodiment, more specifically, the ARM processing unit 11 is further configured to configure the abnormal data detection module 122 in the FPGA processing unit 12 according to the updated judgment vector.
Specifically, referring to fig. 1 to 3, the FPGA processing unit 12 and the ARM processing unit 11 are communicatively connected to the data center system through the wireless communication unit 7, and are configured to send the network data and the abnormal data to the data center system. In this embodiment, the wireless communication unit 7 may be a 4G wireless communication unit.
Specifically, with reference to fig. 1 to fig. 3, the monitoring unit 5 is communicatively connected to the FPGA processing unit 12 and the ARM processing unit 11, and is configured to monitor the operation states of the FPGA processing unit 12 and the ARM processing unit 11 in real time, generate and send an abnormal signal to the FPGA processing unit 12 and the ARM processing unit 11 when the operation state is an abnormal state, and perform reset processing on the FPGA processing unit 12 and the ARM processing unit 11.
More specifically, the main processor 1 is also provided with a USB communication interface and an RS232 communication interface, serving as a debug interface. The main processor 1 is also provided with a power supply system for supplying power to the whole train Ethernet abnormal data detection system, and the main processor 1 is also provided with an RTC for providing clock information for the main processor 1.
According to the train Ethernet abnormal data detection system provided by the embodiment, the ARM processing unit and the FPGA processing unit are integrated to form the main processor, the Ethernet communication module is directly hung on the FPGA processing unit, the problems that the interaction performance of a computer is affected due to the high cost of a CPU during abnormal data detection are solved, the complexity of a hardware circuit is reduced, the reliability of the system is improved, the extra cost of the CPU is reduced based on the characteristic that the FPGA processing unit processes data in parallel, and the real-time performance and the accuracy of data processing are guaranteed; and abnormal network data are detected through the FPGA processing unit and the judgment vector, the network data are sent to the server processing unit through the ARM processing unit, the judgment vector is updated, the reliability of the system is guaranteed, and the misjudgment rate is reduced.
The embodiment also provides train ethernet abnormal data detection equipment, which comprises the train ethernet abnormal data detection system.
Referring to fig. 4, the present embodiment provides a train ethernet abnormal data detection method, which is applied to the train ethernet abnormal data detection system described above, and includes:
s1: the FPGA processing unit 12 sends the network data of the terminal equipment 3 and the switch 2 to the server processing unit 4 through the ARM processing unit 11 and the switch 3 in sequence;
s2: the server processing unit 4 trains network data to generate an abnormal data detection model and a judgment vector, and sends the judgment vector to the FPGA processing unit 12 through the switch 2 and the ARM processing unit 11 in sequence;
s3: the FPGA processing unit 12 detects and filters abnormal network data in the network data according to the judgment vector, sends normal network data in the network data to the terminal equipment 3 or the switch 2, and sends the abnormal network data to the server processing unit 4 through the ARM processing unit 11 and the switch 2 in sequence;
s4: the server processing unit 4 updates the judgment vector generated at step S2 based on the abnormal data detection model and the abnormal network data, and repeatedly executes steps S2 to S4.
The method for detecting train ethernet abnormal data provided by this embodiment further includes, between step S2 and step S3:
when the data received by the FPGA processing unit 12 from the switch 2 is network data, step S3 is executed;
when the FPGA processing unit 12 receives the data of the switch 2 as the configuration data, that is, the updated judgment vector, the FPGA processing unit 12 is configured, and the step S3 is executed. In this embodiment, when the FPGA processing unit 12 receives the updated judgment vector that is the configuration data, the FPGA processing unit 12 configures the judgment vector of the abnormal data detecting module 122 in the FPGA processing unit 12 based on the updated judgment vector.
According to the train Ethernet abnormal data detection method provided by the embodiment, based on a train Ethernet abnormal data detection system, the ARM processing unit and the FPGA processing unit are integrated to form the main processor, and the Ethernet communication module is directly hung on the FPGA processing unit, so that the problems that the interaction performance of a computer is influenced due to the high cost of a CPU in abnormal data detection are solved, the complexity of a hardware circuit is reduced, the reliability of the system is improved, and based on the characteristic that the FPGA processing unit processes data in parallel, the extra cost of the CPU is reduced, and the real-time performance and the accuracy of data processing are ensured; and abnormal network data are detected through the FPGA processing unit and the judgment vector, the network data are sent to the server processing unit through the ARM processing unit, the judgment vector is updated, the reliability of the system is guaranteed, and the misjudgment rate is reduced.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. An Ethernet abnormal data detection system for a train is characterized by comprising: a main processor, a switch, a terminal device and a server processing unit, wherein,
the main processor is integrated by an ARM processing unit and an FPGA processing unit;
the FPGA processing unit is in communication connection with the switch and the terminal equipment through an Ethernet communication unit, is also in communication connection with the ARM processing unit, is used for detecting and filtering abnormal network data in the network data of the switch and the terminal equipment according to a judgment vector, and is used for sending the network data and the abnormal network data to the ARM processing unit;
the ARM processing unit is in communication connection with the switch through the Ethernet communication unit, the switch is in communication connection with the server processing unit, and the ARM processing unit is used for sending the network data and the abnormal data to the server processing unit and sending the judgment vector to the FPGA processing unit;
the server processing unit is used for training the network data, generating the abnormal data detection model and the judgment vector, updating the judgment vector based on the abnormal data detection model and the abnormal data, and sending the updated judgment vector to the ARM processing unit.
2. The train ethernet anomaly data detection system according to claim 1, wherein said ARM processing unit is further configured to configure said FPGA processing unit according to said updated decision vector.
3. The train ethernet anomaly data detection system according to claim 1, wherein said FPGA processing unit comprises: a multipath selection module and an anomaly data detection module, wherein,
the multipath selection module is in communication connection with an ARM processing unit and an abnormal data detection module, is also in communication connection with the switch through the Ethernet communication unit, and is used for sending the network data to the abnormal data detection module when the data received by the switch is the network data; when the received data of the switch is configuration data, namely the updated judgment vector, the configuration data is sent to the ARM processing unit;
the abnormal data detection module is in communication connection with the terminal equipment through the Ethernet communication unit, is also in communication connection with an ARM processing unit, and is used for sending the network data of the switch and the terminal equipment to the ARM processing unit, detecting and filtering the abnormal network data in the network data according to the judgment vector, and sending the abnormal network data to the ARM processing unit.
4. The train Ethernet abnormal data detection system according to claim 3, wherein the FPGA processing unit further comprises: a data storage module, wherein,
the data storage module is in communication connection with the abnormal data detection module and is used for storing the network data and the abnormal network data of the switch and the terminal equipment.
5. The train Ethernet abnormal data detection system according to any one of claims 1 to 4, wherein the abnormal data detection method in the FPGA processing unit specifically comprises:
analyzing the network data of the switch and the terminal equipment into matrix vector data;
multiplying the matrix vector data by the judgment vector, and if the multiplication result is 1, sending the abnormal network data in the network data to the ARM processing unit; and if the multiplication result is 0, sending the normal network data in the network data to the terminal equipment or the switch through the Ethernet communication unit.
6. The train ethernet anomaly data detection system according to claim 1, further comprising:
the FPGA processing unit and the ARM processing unit are in communication connection with a data center system through the wireless communication unit and are used for sending the network data and the abnormal data to the data center system.
7. The train ethernet anomaly data detection system according to claim 1, further comprising:
and the monitoring unit is in communication connection with the FPGA processing unit and the ARM processing unit and is used for monitoring the running states of the FPGA processing unit and the ARM processing unit in real time, generating and sending abnormal signals to the FPGA processing unit and the ARM processing unit when the running state is an abnormal state, and resetting the FPGA processing unit and the ARM processing unit.
8. An ethernet over train anomaly data detection device comprising the ethernet over train anomaly data detection system according to any one of claims 1 to 7.
9. A train ethernet abnormal data detection method applied to the train ethernet abnormal data detection system according to any one of claims 1 to 7, comprising:
s1: the FPGA processing unit sends network data of the terminal equipment and the switch to the server processing unit through the ARM processing unit and the switch in sequence;
s2: the server processing unit trains the network data to generate an abnormal data detection model and a judgment vector, and sends the judgment vector to the FPGA processing unit through the switch and the ARM processing unit in sequence;
s3: the FPGA processing unit detects and filters abnormal network data in the network data according to the judgment vector, sends normal network data in the network data to the terminal equipment or the switch, and sends the abnormal network data to the server processing unit through the ARM processing unit and the switch in sequence;
s4: the server processing unit updates the judgment vector generated in the step S2 based on the abnormal data detection model and the abnormal network data, and repeatedly performs the steps S2 to S4.
10. The method for detecting ethernet over train anomaly data according to claim 9, wherein between the step of S2 and the step of S3, the method further comprises:
when the data of the switch received by the FPGA processing unit is the network data, executing the step S3;
and when the data received by the FPGA processing unit from the switch is configuration data, i.e., the updated judgment vector, configuring the FPGA processing unit, and executing the step S3.
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| CN202110399041.2A CN112968818B (en) | 2021-04-14 | 2021-04-14 | Train Ethernet abnormal data detection system, equipment and method |
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| CN114116567A (en) * | 2021-11-29 | 2022-03-01 | 辽宁神州北斗科技有限公司 | Big data calculation analysis system and method |
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