CN112968598B - PFC control system and PFC control method - Google Patents

PFC control system and PFC control method Download PDF

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CN112968598B
CN112968598B CN202110537098.4A CN202110537098A CN112968598B CN 112968598 B CN112968598 B CN 112968598B CN 202110537098 A CN202110537098 A CN 202110537098A CN 112968598 B CN112968598 B CN 112968598B
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resistor
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CN112968598A (en
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陈铭钦
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Foshan Xinchen Electronic Co ltd
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Foshan Xinchen Electronic Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/01—Arrangements for reducing harmonics or ripples
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/40—Arrangements for reducing harmonics

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The application relates to a PFC control system and a PFC control method, wherein the PFC control system comprises a current sampling circuit, a PFC control circuit and a working circuit, wherein the input end of the working circuit is electrically connected with a mains supply VIN, and the output end of the working circuit is used for being electrically connected with a LOAD LOAD; the input end of the current sampling circuit is electrically connected with the working circuit, the output end of the current sampling circuit is grounded, and the current sampling circuit is electrically connected with the PFC control circuit; the PFC control circuit is coupled with the working circuit and used for driving the full range of the mains supply input voltage to meet the standard THDI. The PFC control method comprises the following steps: acquiring circuit information of a PFC control system; obtaining an equation about the mains voltage and the adjustable parameter according to the circuit information; based on an equation, the adjustable parameters are adjusted according to the magnitude of the mains supply voltage, and the adjustable parameters are used for driving the mains supply input voltage to meet the THDI of the standard in a full range. The PFC processing method and the PFC processing device have the effect of facilitating PFC.

Description

PFC control system and PFC control method
Technical Field
The present disclosure relates to the field of UPS power factor correction technologies, and in particular, to a PFC control system and a PFC control method.
Background
PFC means "power factor correction" and the power factor refers to the relationship between the effective power and the total power consumption (apparent power), that is, the ratio of the effective power divided by the total power consumption (apparent power). Basically, the power factor can measure the effective utilization degree of the power, and when the power factor value is larger, the power utilization rate is higher. The power factor is a parameter for measuring the power efficiency of the electric equipment, and the low power factor represents the low power efficiency. A technique for increasing the power factor of a powered device is known as power factor correction.
In the related art, a micro UPS performs PFC under the mains supply, and a power factor correction circuit is built. When implementing PFC, the mains input needs to meet the standard THDI (total distortion rate of current harmonics). Typically around 10V at mains supply, the standard THDI is met, i.e. THDI < 5%.
In view of the above-mentioned related art, the inventor believes that, under the full load condition, the voltage range of the THDI that the mains supply input meets the standard is small, which results in that the mains supply input voltage cannot meet the standard THDI in the full range, and causes the defect that the PFC is not convenient.
Disclosure of Invention
In order to facilitate PFC, the application provides a PFC control system and a PFC control method.
In a first aspect, the present application provides a PFC control system, which employs the following technical solutions:
the PFC control system comprises a current sampling circuit, a PFC control circuit and a working circuit, wherein the input end of the working circuit is electrically connected with the commercial power VIN, and the output end of the working circuit is electrically connected with the LOAD LOAD;
the input end of the current sampling circuit is electrically connected with the working circuit, the output end of the current sampling circuit is grounded, and the current sampling circuit is electrically connected with the PFC control circuit and used for transmitting the acquired current information to the PFC control circuit;
the PFC control circuit is coupled with the working circuit and used for driving the full range of the mains supply input voltage to meet the standard THDI, wherein the standard THDI means that the THDI is less than 5%.
By adopting the technical scheme, the current sampling circuit is arranged for collecting the input current and transmitting the input current to the PFC control circuit, and the PFC control circuit corrects the power factor according to the change of the mains supply VIN, so that the mains supply voltage range suitable for PFC is enlarged, the full range of the mains supply input voltage meets THDI, and the PFC is convenient to carry out.
Optionally, the PFC control circuit includes a UC3843 chip, a UC3843 peripheral circuit, a resistor R2, a software compensation signal terminal, and a Vbus control terminal, where the UC3843 chip is coupled to the UC3843 peripheral circuit;
the software compensation signal terminal is electrically connected with the UC3843 peripheral circuit and is used for inputting a compensation signal adaptive to power factor correction;
the resistor R2 is electrically connected between the software compensation signal terminal and the UC3843 peripheral circuit;
the Vbus control terminal is electrically connected with a UC3843 peripheral circuit and is used for inputting a control signal for regulating and controlling Vbus;
the UC3843 peripheral circuit is electrically connected with the current sampling circuit and is used for receiving the current information acquired by the current sampling circuit;
the UC3843 peripheral circuit is electrically connected to the working circuit.
Through adopting above-mentioned technical scheme, UC3843 peripheral circuit is provided with and does benefit to UC3843 chip normal work, and the setting of software compensation signal terminal and Vbus control terminal does benefit to and controls power factor correction to be convenient for carry out PFC.
Optionally, the working circuit includes inductance L1, diode D1, electric capacity Cbus and switch tube T1, inductance L1's input and commercial power VIN's positive pole electric connection, the current sampling circuit is coupled between commercial power VIN's positive pole and inductance L1's input, inductance L1's output and diode D1's input, switch tube T1's drain electrode electric connection, diode D1's output and electric capacity Cbus's input electric connection, switch tube T1's grid and UC3843 chip's 6 th pin electric connection, switch tube T1's source and commercial power's negative pole electric connection, electric capacity Cbus's output and switch tube T1's source, VIN's negative pole electric connection, electric capacity Cbus's input be used for with LOAD's input electric connection, electric capacity lobus's output is used for with LOAD's output electric connection.
By adopting the technical scheme, when the 6 th pin of the UC3843 chip outputs high voltage, the switching tube T1 is conducted, the energy of commercial power is converted into the inductor by utilizing the characteristic of the inductor, the inductor stores the energy, and the LOAD LOAD is supplied with power by the Cbus; when the 6 th pin of UC3843 outputs a low level, the switching tube T1 is turned off, and by using the characteristic of inductance, the energy is released and the commercial power is supplied to LOAD through the diode D1 and charges the capacitor Cbus.
Optionally, the current sampling circuit includes a current transformer CT1 and a resistor RS, an input end of a primary side of the current transformer CT1 is electrically connected to an anode of the commercial power VIN, an output end of a primary side of the current transformer CT1 is electrically connected to an input end of the inductor L1, an input end of a secondary side of the current transformer CT1 is electrically connected to one end of the resistor RS, and an output end of a secondary side of the current transformer CT1 is electrically connected to a UC3843 peripheral circuit.
Through adopting above-mentioned technical scheme, being provided with of current transformer CT1 does benefit to and converts the heavy current in the circuit into the undercurrent of certain proportion to in measurement.
Optionally, the UC3843 peripheral circuit includes slope compensation circuit, filter circuit, stabilizing circuit, oscillator circuit and feedback circuit, slope compensation circuit, filter circuit, stabilizing circuit, oscillator circuit and feedback circuit respectively with UC3843 chip electric connection, resistance R2's output and slope compensation circuit electric connection, Vbus control terminal and feedback circuit electric connection.
By adopting the technical scheme, the normal work of the UC3843 chip is facilitated, and the control on the PFC is facilitated, so that the PFC is convenient to carry out.
Optionally, the slope compensation circuit includes an NPN triode Q1, a resistor R3, and a resistor R5, a base of the NPN triode Q1 is electrically connected to a4 th pin of the UC3843 chip, a collector of the NPN triode Q1 is electrically connected to a8 th pin of the UC3843 chip, an emitter of the NPN triode Q1 is electrically connected to an input of the resistor R3, an output of the resistor R3 is electrically connected to an input of the resistor R5, and an output of the resistor R5 is electrically connected to the filter circuit;
the output end of the resistor R2 is electrically connected with the output end of the resistor R3 and the input end of the resistor R5.
Through adopting above-mentioned technical scheme, be favorable to carrying out slope compensation better, and software compensation signal terminal passes through resistance R2 and resistance R5 electric connection, and then is favorable to the access of software compensation signal to be convenient for carry out PFC.
Optionally, the feedback circuit includes a resistor R4, a resistor R7, and a capacitor C5, the Vbus control terminal is electrically connected to an input terminal of the resistor R4, an output terminal of the resistor R4 is electrically connected to an input terminal of the capacitor C5, an output terminal of the capacitor C5 is grounded, an input terminal of the resistor R7 is electrically connected to an input terminal of the capacitor C5 and the stabilizing circuit, and an output terminal of the resistor R7 is grounded.
Through adopting above-mentioned technical scheme, resistance R4 and resistance R7's setting is favorable to carrying out the partial pressure, and the setting of electric capacity C5 is favorable to carrying out the filtering, also is favorable to among the Vbus control terminal access circuit to be convenient for carry out PFC.
In a second aspect, the present application provides a PFC control method, which adopts the following technical solution:
a PFC control method, a PFC control system adapted to any one of the above, comprising:
acquiring circuit information of a PFC control system;
obtaining an equation about the mains voltage and the adjustable parameter according to the circuit information; the equation for the adjustable parameter is applicable to the PFC control system in any of the above;
based on an equation, the adjustable parameter is adjusted according to the magnitude of the mains voltage, and is used for driving the full range of the mains input voltage to meet the standard THDI, wherein the standard THDI means that the THDI is less than 5%.
By adopting the technical scheme, the circuit information is used for analyzing an equation about the voltage of the mains supply and the adjustable parameter, and the equation is favorable for accurately adjusting the adjustable parameter, so that PFC is convenient to carry out.
Optionally, the equation of the adjustable parameter is:
Figure 195578DEST_PATH_IMAGE001
(ii) a Wherein
Figure 392204DEST_PATH_IMAGE002
、
Figure 84217DEST_PATH_IMAGE003
(ii) a Vbus and Vc are adjustable parameters, a7, a8, a9 are constants, Vin × sin (wt) is mains voltage; is input current, Rs Is resistance of resistor RS, and Kd Is 1.0 x 106The Fz is the oscillation frequency of the UC3843 chip, and both the a5 and the a6 are constants;
the size of the Vbus is adjusted through a Vbus control terminal, and the size of the Vc is adjusted through a software compensation signal terminal.
By adopting the technical scheme, the equation of the adjustable parameter is arranged, so that the PFC can be controlled more accurately, the input signals of the signal terminal and the Vbus control terminal can be compensated through software, the total range of the input voltage of the mains supply can meet THDI, and the PFC can be performed conveniently.
Optionally, the equation-based method of adjusting the adjustable parameter according to the magnitude of the mains voltage to drive the full range of the mains input voltage to meet the THDI standard includes:
a1, when the voltage value of the mains voltage is 220V, the bus voltage Vbus and the compensation point Vc voltage which meet the equation are used as references; at the moment, the size of the bus voltage Vbus is recorded as A, and the size of the voltage Vc at the compensation point is recorded as B;
a2, judging whether the voltage value of the mains voltage is less than or greater than 220V, if so, entering A3; if the voltage value of the mains voltage is larger than 220V, entering A4;
a3, reducing a and B by the Vbus control terminal and the software compensation signal terminal, and making the equation true;
a4, increasing a and B by the Vbus control terminal and the software compensation signal terminal, and making the equation true.
By adopting the technical scheme, when the mains voltage is 220V, the values of A and B are taken as the reference, both A and B meet the equation, and then the values of A and B are adjusted according to the change of the mains voltage, so that the equation is always established, and the adjustment is completed more quickly, and the PFC is facilitated.
In summary, the present application includes at least one of the following beneficial technical effects:
1. the current sampling circuit is used for collecting input current and transmitting the input current to the PFC control circuit, the PFC control circuit corrects power factors according to the change of the mains supply VIN, the mains supply voltage range suitable for PFC is enlarged, the full range of the mains supply input voltage meets THDI, and therefore PFC is convenient to carry out.
2. When the 6 th pin of the UC3843 chip outputs high voltage, the switching tube T1 is switched on, the energy of the commercial power is converted into the inductor by using the characteristic of the inductor, the inductor stores the energy, and the LOAD LOAD is supplied with power by the Cbus; when the 6 th pin of UC3843 outputs a low level, the switching tube T1 is turned off, and by using the characteristic of inductance, the energy is released and the commercial power is supplied to LOAD through the diode D1 and charges the capacitor Cbus.
3. The circuit information is used for analyzing an equation about the mains voltage and the adjustable parameter, and the equation is beneficial to accurately adjusting the adjustable parameter, so that PFC is facilitated.
Drawings
Fig. 1 is a schematic circuit connection diagram of a PFC control system according to an embodiment of the present application.
Fig. 2 is a schematic connection diagram of the UC3843 chip and the UC3843 peripheral circuit according to the embodiment of the present application.
Fig. 3 is a flowchart of a PFC control method according to another embodiment of the present application.
Fig. 4 is a flowchart illustrating a specific method of step S120 in fig. 3.
Description of reference numerals: 1. a current sampling circuit; 2. a PFC control circuit; 21. UC3843 chips; 22. UC3843 peripheral circuitry; 221. a slope compensation circuit; 222. a filter circuit; 223. a stabilization circuit; 224. an oscillation circuit; 225. a feedback circuit; 23. a software compensation signal terminal; 24. a Vbus control terminal; 3. and an operating circuit.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described in detail below with reference to fig. 1-4 and the embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Generally, a micro UPS performs PFC under a mains supply, where the PFC is power factor correction, and the power factor refers to a ratio of ac input active power to input apparent power. Under the condition of full UPS, the range of THDI (total harmonic distortion) of the mains supply input meeting the standard is small, and basically, the range is between 8V and 12V, so that PFC can be realized. To achieve a normal PFC the mains input needs a THDI that meets the standard, i.e. less than 5%. But the range of the mains input that meets the standard THDI is too small to facilitate PFC.
Referring to fig. 1, in the PFC control system disclosed in the embodiment of the present application, the PFC control system includes a current sampling circuit 1, a PFC control circuit 2, and a working circuit 3, an input end of the working circuit 3 is electrically connected to a commercial power VIN, and an output end of the working circuit 3 is electrically connected to a LOAD. The input end of the current sampling circuit 1 is electrically connected with the working circuit 3, the output end of the current sampling circuit 1 is grounded, and the current sampling circuit 1 is electrically connected with the PFC control circuit 2 and used for transmitting the collected current information to the PFC control circuit 2. The PFC control circuit 2 is coupled to the working circuit 3, and is configured to drive the full range of the mains input voltage to meet the THDI standard.
Referring to fig. 1 and 2, PFC control circuit 2 includes UC3843 chip 21, UC3843 peripheral circuit 22, resistor R2, software compensation signal terminal 23, and Vbus control terminal 24, where UC3843 chip 21 is coupled to UC3843 peripheral circuit 22, and the circuit connection relationship is as shown in fig. 2. The UC3843 peripheral circuit 22 is electrically connected to the current sampling circuit 1, and is configured to receive current information acquired by the current sampling circuit 1; the UC3843 peripheral circuit 22 is electrically connected to the operating circuit 3. The software compensation signal terminal 23 is electrically connected to the UC3843 peripheral circuit 22, and is used for inputting a compensation signal adapted to power factor correction; the resistor R2 is electrically connected between the software compensation signal terminal 23 and the UC3843 peripheral circuit 22. Vbus control terminal 24 is electrically connected to UC3843 peripheral circuit 22, and is used for inputting control signals for regulating Vbus.
Referring to fig. 1 and 2, the working circuit 3 includes an inductor L1, a diode D1, a capacitor Cbus, and a switch tube T1, the switch tube T1 is an N-channel MOS tube, an input end of the inductor L1 is electrically connected to an anode of a commercial power VIN, the current sampling circuit 1 is coupled between the anode of the commercial power VIN and an input end of the inductor L1, an output end of the inductor L1 is electrically connected to an input end of the diode D1 and a drain of the switch tube T1, an output end of the diode D1 is electrically connected to an input end of the capacitor Cbus, a gate of the switch tube T1 is electrically connected to a6 th pin of the UC3843 chip 21, a source of the switch tube T1 is electrically connected to a cathode of the commercial power VIN, an output end of the capacitor Cbus is electrically connected to a source of the switch tube T1 and a cathode of the commercial power VIN, an input end of the capacitor Cbus ad is electrically connected to an input end of the LOAD Cbus, and an output end of the capacitor Cbus is electrically connected to an output end of the LOAD.
Referring to fig. 2, when the pin 6 of the UC3843 chip 21 outputs a high voltage, the switching tube T1 is turned on, the energy of the commercial power is converted into the inductor and stored by the inductor, and the LOAD is powered by Cbus; when the 6 th pin of UC3843 outputs a low level, the switching tube T1 is turned off, and by using the characteristic of inductance, the energy is released and the commercial power is supplied to LOAD through the diode D1 and charges the capacitor Cbus.
Referring to fig. 1 and 2, the current sampling circuit 1 includes a current transformer CT1 and a resistor RS, an input terminal of a primary side of the current transformer CT1 is electrically connected to an anode of the utility power VIN, an output terminal of a primary side of the current transformer CT1 is electrically connected to an input terminal of the inductor L1, an input terminal of a secondary side of the current transformer CT1 is electrically connected to one end of the resistor RS, and an output terminal of a secondary side of the current transformer CT1 is electrically connected to the UC3843 peripheral circuit 22.
Referring to fig. 2, the UC3843 peripheral circuit 22 includes a slope compensation circuit 221, a filter circuit 222, a stabilization circuit 223, an oscillator circuit 224, and a feedback circuit 225, where the slope compensation circuit 221, the filter circuit 222, the stabilization circuit 223, the oscillator circuit 224, and the feedback circuit 225 are respectively electrically connected to the UC3843 chip 21, an output end of the resistor R2 is electrically connected to the slope compensation circuit 221, and the Vbus control terminal 24 is electrically connected to the feedback circuit 225. The filter circuit 222 is electrically connected to the output terminal of the secondary side of the current transformer CT 1.
Referring to fig. 2, the slope compensation circuit 221 includes an NPN transistor Q1, a resistor R3, and a resistor R5, wherein a base of the NPN transistor Q1 is electrically connected to the 4 th pin of the UC3843 chip 21, a collector of the NPN transistor Q1 is electrically connected to the 8 th pin of the UC3843 chip 21, an emitter of the NPN transistor Q1 is electrically connected to an input of the resistor R3, an output of the resistor R3 is electrically connected to an input of the resistor R5, and an output of the resistor R5 is electrically connected to the filter circuit 222. The output end of the resistor R2 is electrically connected with the output end of the resistor R3 and the input end of the resistor R5.
Referring to fig. 2, the filter circuit 222 includes a resistor R9 and a capacitor C6, an input terminal of the resistor R9 is electrically connected to an output terminal of the secondary side of the current transformer CT1, an output terminal of the resistor R9 is electrically connected to an input terminal of the capacitor C6 and the 3 rd pin of the UC3843 chip 21, and an output terminal of the capacitor C6 is grounded.
Referring to fig. 2, the stabilizing circuit 223 includes a capacitor C2, a capacitor C3, a capacitor C4, and a resistor R6, two ends of the capacitor C3 are electrically connected to the 1 st pin and the 2 nd pin of the UC3843 chip 21, and two ends of the capacitor C4 are electrically connected to two ends of the capacitor C3, respectively. The input end of the resistor R6 is electrically connected to the feedback circuit 225 and the input end of the capacitor C4, the output end of the resistor R6 is electrically connected to the input end of the capacitor C2, and the output end of the capacitor C2 is electrically connected to the output end of the capacitor C4.
Referring to fig. 2, the feedback circuit 225 includes a resistor R4, a resistor R7, and a capacitor C5, the Vbus control terminal 24 is electrically connected to the input terminal of the resistor R4, the output terminal of the resistor R4 is electrically connected to the input terminal of the capacitor C5, the output terminal of the capacitor C5 is grounded, the input terminal of the resistor R7 is electrically connected to the input terminal of the capacitor C5 and the input terminal of the resistor R6, and the output terminal of the resistor R7 is grounded.
Referring to fig. 1, the input power of the UPS is power factor corrected, and the input and output relationships are:
Figure 24491DEST_PATH_IMAGE004
d (T) is the duty cycle of the switching tube T1, Vin × sin (wt) is the mains input voltage, and Vbus is the output BUS voltage.
Referring to fig. 1 and 2, the working principle is as follows: the resistor R1 and the capacitor C1 form an oscillation frequency of the UC3843 chip 21, and the oscillation frequency is:
Figure 751139DEST_PATH_IMAGE005
tc is the charging time of the capacitor C1, Td is the discharging time of the capacitor C1, Fz is the oscillation frequency of the UC3843 chip 21, Ton is the output on-time of the 6 th pin of the UC3843 chip 21, and d (t) is the output on-duty cycle of the 6 th pin of the UC3843 chip 21. The transistor Q1, the resistor R3, and the resistor R5 form slope compensation of the UC3843 chip 21 to the 3 rd pin. The resistor R9 and the capacitor C6 form a filter circuit 222 for the sampled current Icurent. After voltage division by the resistor R4 and the resistor R7, the capacitor C5 filters the voltage and feeds the filtered voltage back to the 1 st pin of the UC3843 chip 21.
The resistor R6, the capacitor C2, the capacitor C4 and the capacitor C3 form a stabilizing circuit 223. The resistor R8 is a PWM driving current-limiting resistor of the 6 th pin of the UC3843 chip 21.
Vt is the voltage after slope compensation through the transistor:
Figure 118666DEST_PATH_IMAGE006
tt is the compensation slope linear rising time and also the output high time of the 6 th pin of the UC3843 chip 21.
When the 6 th pin of the UC3843 chip 21 outputs a high voltage, the switching tube T1 is turned on, and by using the characteristics of the inductor, the energy of the commercial power is exchanged into the inductor and stored by the inductor, and the LOAD is provided by Cbus; when the 6 th pin of the UC3843 chip 21 outputs a low level, the switching tube T1 is turned off, and by using the characteristic of inductance, energy and commercial power are released to provide a LOAD through the diode D1 and charge the capacitor Cbus.
According to the above principle, when the software compensation signal terminal 23 and the resistor R2 are not provided, the voltage for the 3 rd pin of the UC3843 chip 21 can be derived as the following equation:
Figure 563554DEST_PATH_IMAGE007
vcomp is the 1 st pin voltage of the UC3843 chip 21.
The simplification results in:
Figure 776361DEST_PATH_IMAGE008
(ii) a Wherein
Figure 623094DEST_PATH_IMAGE009
；
Substitution into
Figure 895943DEST_PATH_IMAGE010
And Kd =1.0 x 106And finishing to obtain:
Figure 828127DEST_PATH_IMAGE011
(ii) a Handle
Figure 844625DEST_PATH_IMAGE012
Substitution into
Figure 545865DEST_PATH_IMAGE013
Obtaining:
Figure 520774DEST_PATH_IMAGE014
；
further finishing to obtain:
Figure 409095DEST_PATH_IMAGE015
；
when in use
Figure 494863DEST_PATH_IMAGE016
Since Vcomp represents the voltage of pin 1 of the UC3843 chip 21, and since Vcomp passes through two diodes in the internal structure of the UC3843 chip 21, the voltage drop of each diode is 0.7V, then the voltage is divided into one third by a resistor, and since there is a 1V voltage regulator, the voltage is clamped to 1V by the internal structure of the UC3843 chip 21, so that the voltage is reduced to one third
Figure 50609DEST_PATH_IMAGE017
When, b = 1;
thereby to obtain
Figure 907403DEST_PATH_IMAGE018
The equivalence is as follows:
Figure 548600DEST_PATH_IMAGE019
(ii) a Since Rs, a1, a2, Kd, Fz are constants, Vbus is a constant value. Further equivalent is:
Figure 906900DEST_PATH_IMAGE020
(ii) a Wherein
Figure 582732DEST_PATH_IMAGE021
,
Figure 633865DEST_PATH_IMAGE022
；
Since a1, a3 and a4 are constants, the input current Is follows the waveform of the input voltage, thereby achieving the effect of PFC.
After the software compensation signal terminal 23 and the resistor R2 are added, the relationship is derived according to the voltage of the 3 rd pin of the UC3843 chip 21:
Figure 762358DEST_PATH_IMAGE023
；
and (3) sorting the relation to obtain:
Figure 924349DEST_PATH_IMAGE024
；
wherein the content of the first and second substances,
Figure 189108DEST_PATH_IMAGE025
；
will be provided with
Figure 411142DEST_PATH_IMAGE026
Substituting and simplifying to obtain:
Figure 26931DEST_PATH_IMAGE027
；
when in use
Figure 258192DEST_PATH_IMAGE017
In the process, since Vcomp represents the voltage of the 1 st pin of the UC3843 chip 21, and since Vcomp passes through two diodes in the internal structure of the UC3843 chip 21, the voltage drop of each diode is 0.7V, and then is divided into one third by a resistor, and since there is a 1V voltage regulator, the voltage is clamped to 1V by the internal structure of the UC3843 chip 21, so that the voltage is clamped to 1V, and thus the voltage is stable for the integrated circuit
Figure 377458DEST_PATH_IMAGE017
When, b =1. Since a5, a6 and a7 are constants, the simplification is continued to obtain:
Figure 770393DEST_PATH_IMAGE028
；
wherein
Figure 607899DEST_PATH_IMAGE029
(ii) a Vbus and Vc are adjustable parameters, a7, a8, a9 are constants, Vin × sin (wt) is mains voltage.
Referring to fig. 3, a PFC control method disclosed in an embodiment of the present application includes:
and S100, acquiring circuit information of the PFC control system.
Specifically, circuit connection diagram information of a PFC control system is obtained; and acquiring parameter information of each electronic element in the PFC control system.
The information of the circuit connection diagram of the PFC control system is obtained by shooting the PFC control system by a camera, and can also be directly input by a user. And carrying out image processing on the circuit connection diagram information, identifying the type of each electronic element, and then obtaining the parameter information of each electronic element in the PFC control system through a network, wherein the parameter information can also be directly input and obtained by a user.
And S110, obtaining an equation about the mains voltage and the adjustable parameter according to the circuit information.
Specifically, a mathematical relation between the mains voltage and the adjustable parameter is deduced according to the circuit connection diagram information and the parameter information of each electronic element; and obtaining an equation about the mains voltage and the adjustable parameter according to the mathematical relation between the mains voltage and the adjustable parameter.
The equation for the adjustable parameter is:
Figure 111693DEST_PATH_IMAGE030
(ii) a Wherein
Figure 616624DEST_PATH_IMAGE002
、
Figure 180460DEST_PATH_IMAGE031
(ii) a Vbus and Vc are adjustable parameters, a7, a8, a9 are constants, Vin × sin (wt) is mains voltage; is input current and Rs IsResistance of the resistor RS, said Kd being 1.0 x 106The Fz is the oscillation frequency of the UC3843 chip, and both the a5 and the a6 are constants;
the size of the Vbus is adjusted through a Vbus control terminal, and the size of the Vc is adjusted through a software compensation signal terminal.
And S120, based on the equation, adjusting the adjustable parameters according to the magnitude of the mains supply voltage, and driving the mains supply input voltage to meet the standard THDI in the full range.
Referring to fig. 3 and 4, specifically, based on an equation, according to the magnitude of the mains voltage, the adjustable parameter is adjusted to drive the mains input voltage to meet the standard THDI over the full range, including the following steps:
a1, when the voltage value of the mains voltage is 220V, the bus voltage Vbus and the compensation point Vc voltage which meet the equation are used as references; at this time, the magnitude of the bus voltage Vbus is recorded as a, and the magnitude of the compensation point Vc voltage is recorded as B.
A2, judging whether the voltage value of the mains voltage is less than or greater than 220V, if so, entering A3; if the voltage value of the mains voltage is greater than 220V, a4 is entered.
A3, reducing a and B by the Vbus control terminal and the software compensation signal terminal, and making the equation true;
a4, increasing a and B by the Vbus control terminal and the software compensation signal terminal, and making the equation true.
When the mains voltage is 220V, the values of A and B are taken as references, both A and B meet the equation, and then the values of A and B are adjusted according to the change of the mains voltage, so that the equation is always established, and the adjustment is completed more quickly, and the PFC is facilitated.
The foregoing is a preferred embodiment of the present application and is not intended to limit the scope of the application in any way, and any features disclosed in this specification (including the abstract and drawings) may be replaced by alternative features serving equivalent or similar purposes, unless expressly stated otherwise. That is, unless expressly stated otherwise, each feature is only an example of a generic series of equivalent or similar features.

Claims (1)

  1. The PFC control method is characterized by being applicable to a PFC control system, wherein the PFC control system comprises a current sampling circuit (1), a PFC control circuit (2) and a working circuit (3), the input end of the working circuit (3) is electrically connected with a mains supply VIN, the output end of the working circuit (3) is used for being electrically connected with a LOAD LOAD, the input end of the current sampling circuit (1) is electrically connected with the working circuit (3), the output end of the current sampling circuit (1) is grounded, and the current sampling circuit (1) is electrically connected with the PFC control circuit (2) and used for transmitting collected current information to the PFC control circuit (2); the PFC control circuit (2) is coupled with the working circuit (3) and is used for driving the full range of the mains supply input voltage to meet the THDI of the standard;
    the PFC control circuit (2) comprises a UC3843 chip (21), a UC3843 peripheral circuit (22), a resistor R2, a software compensation signal terminal (23) and a Vbus control terminal (24), the UC3843 chip (21) is coupled with the UC3843 peripheral circuit (22), the software compensation signal terminal (23) is electrically connected with the UC3843 peripheral circuit (22), the resistor R2 is electrically connected between the software compensation signal terminal (23) and the UC3843 peripheral circuit (22), the Vbus control terminal (24) is electrically connected with a UC3843 peripheral circuit (22), the UC3843 peripheral circuit (22) is electrically connected with the current sampling circuit (1), the UC3843 peripheral circuit (22) is electrically connected with the working circuit (3);
    the working circuit (3) comprises an inductor L1, a diode D1, a capacitor Cbus and a switching tube T1, the input end of the inductor L1 is electrically connected with the anode of the mains supply VIN, the current sampling circuit (1) is coupled between the anode of the mains supply VIN and the input end of the inductor L1, the output end of the inductor L1 is electrically connected with the input end of the diode D1 and the drain electrode of the switch tube T1, the output end of the diode D1 is electrically connected with the input end of the capacitor Cbus, the grid of the switch tube T1 is electrically connected with the UC3843 peripheral circuit (22), the source electrode of the switch tube T1 is electrically connected with the negative electrode of the commercial power VIN, the output end of the capacitor Cbus is electrically connected with the source electrode of the switch tube T1 and the negative electrode of the commercial power VIN, the input end of the capacitor Cbus is electrically connected with the input end of the LOAD LOAD, and the output end of the capacitor Cbus is electrically connected with the output end of the LOAD LOAD;
    the current sampling circuit (1) comprises a current transformer CT1 and a resistor RS, wherein the input end of the primary side of the current transformer CT1 is electrically connected with the anode of a commercial power VIN, the output end of the primary side of the current transformer CT1 is electrically connected with the input end of an inductor L1, the input end of the secondary side of the current transformer CT1 is electrically connected with one end of the resistor RS, and the output end of the secondary side of the current transformer CT1 is electrically connected with a UC3843 peripheral circuit (22);
    the UC3843 peripheral circuit (22) comprises a slope compensation circuit (221), a filter circuit (222), a stabilization circuit (223), an oscillation circuit (224) and a feedback circuit (225), wherein the slope compensation circuit (221), the filter circuit (222), the stabilization circuit (223), the oscillation circuit (224) and the feedback circuit (225) are respectively electrically connected with the UC3843 chip (21), the output end of the resistor R2 is electrically connected with the slope compensation circuit (221), and the Vbus control terminal (24) is electrically connected with the feedback circuit (225);
    the slope compensation circuit (221) comprises an NPN triode Q1, a resistor R3 and a resistor R5, wherein a base of the NPN triode Q1 is electrically connected with a4 th pin of the UC3843 chip (21), a collector of the NPN triode Q1 is electrically connected with an 8 th pin of the UC3843 chip (21), an emitter of the NPN triode Q1 is electrically connected with an input end of the resistor R3, an output end of the resistor R3 is electrically connected with an input end of the resistor R5, an output end of the resistor R5 is electrically connected with the filter circuit (222), and an output end of the resistor R2 is electrically connected with an output end of the resistor R3 and an input end of the resistor R5;
    the feedback circuit (225) comprises a resistor R4, a resistor R7 and a capacitor C5, the Vbus control terminal (24) is electrically connected with the input end of the resistor R4, the output end of the resistor R4 is electrically connected with the input end of the capacitor C5, the output end of the capacitor C5 is grounded, the input end of the resistor R7 is electrically connected with the input end of the capacitor C5 and the stabilizing circuit (223), and the output end of the resistor R7 is grounded;
    the PFC control method comprises the following steps:
    acquiring circuit information of a PFC control system;
    obtaining an equation about the mains voltage and the adjustable parameter according to the circuit information; the equation for the adjustable parameter is:
    Figure DEST_PATH_IMAGE001
    ；
    wherein
    Figure DEST_PATH_IMAGE002
    、
    Figure DEST_PATH_IMAGE003
    (ii) a Vbus and Vc are adjustable parameters, a7, a8 and a9 are constants,
    Figure DEST_PATH_IMAGE004
    is the mains voltage; is input current, Rs Is resistance of resistor RS, and Kd Is 1.0 x 106The Fz is the oscillation frequency of the UC3843 chip;
    Figure DEST_PATH_IMAGE005
    、
    Figure DEST_PATH_IMAGE006
    、
    Figure DEST_PATH_IMAGE007
    (ii) a The size of Vbus is adjusted through a Vbus control terminal, and the size of Vc is adjusted through a software compensation signal terminal;
    based on an equation, adjusting the adjustable parameters according to the magnitude of the mains supply voltage, wherein the adjustable parameters are used for driving the full range of the mains supply input voltage to meet the standard THDI;
    the equation-based THDI for driving the full range of the mains supply input voltage to meet the standard is realized by adjusting the adjustable parameter according to the magnitude of the mains supply voltage, and comprises the following steps:
    a1, when the voltage value of the mains voltage is 220V, the bus voltage Vbus and the compensation point Vc voltage which meet the equation are used as references; at the moment, the size of the bus voltage Vbus is recorded as A, and the size of the voltage Vc at the compensation point is recorded as B;
    a2, judging whether the voltage value of the mains voltage is less than or greater than 220V, if so, entering A3; if the voltage value of the mains voltage is larger than 220V, entering A4;
    a3, reducing a and B by the Vbus control terminal and the software compensation signal terminal, and making the equation true;
    a4, increasing a and B by the Vbus control terminal and the software compensation signal terminal, and making the equation true.
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