CN112967745B - Nonvolatile memory and verification reading method thereof - Google Patents
Nonvolatile memory and verification reading method thereof Download PDFInfo
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- CN112967745B CN112967745B CN202110302047.3A CN202110302047A CN112967745B CN 112967745 B CN112967745 B CN 112967745B CN 202110302047 A CN202110302047 A CN 202110302047A CN 112967745 B CN112967745 B CN 112967745B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
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Abstract
The present invention provides a nonvolatile memory, comprising: the storage unit array comprises a plurality of storage strings, wherein each storage string comprises a plurality of storage units, a bottom selection pipe and a top selection pipe; a plurality of word lines respectively connected to the plurality of memory cells; a string selection line connected to the top selection pipe; a ground selection line connected to the bottom selection pipe; a controller configured to controllably select the line to turn off a bottom select pipe of a selected memory string and/or a non-selected memory string in a pre-pulse phase prior to a verify-read phase; controlling the word line to make the memory cells in each memory string conductive; the string select line is controlled to turn off the top select tube in the selected memory string and/or the top select tube in the non-selected memory string for pre-pulsing.
Description
Technical Field
The present invention relates to semiconductor technologies, and in particular, to a nonvolatile memory and a verification reading method thereof.
Background
The semiconductor memory may include a Volatile Memory (VM) and a non-volatile memory (NVM). Volatile memory typically serves as a temporary storage medium, such as memory, for the operating system or other programs that are running. Volatile memory cannot retain data when power is turned off. The non-volatile memory is used for storing data that needs to be retained for a long time, such as a hard disk. Non-volatile memory retains data when power is suddenly turned off or turned off. Examples of the nonvolatile memory include a Flash memory (Flash memory), a read only memory ROM, an electrically erasable programmable read only EEPROM, or the like.
The 3D-Nand flash chip has wide application value in more and more fields. Such as smart phones, solid state storage, SD Card, and USB. The coming 5G era brings many opportunities and challenges to cloud storage and cloud interaction, which also puts higher demands on the performance of the storage.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a nonvolatile memory and a verification reading method thereof, which can effectively reduce the peak power consumption generated by the nonvolatile memory during the pre-pulse period of program verification.
To solve the above technical problem, the present invention provides a nonvolatile memory, including: the storage unit array comprises a plurality of storage strings, wherein each storage string comprises a plurality of storage units, a bottom selection pipe and a top selection pipe; a plurality of word lines respectively connected to the plurality of memory cells; a string selection line connected to the top selection pipe; a ground selection line connected to the bottom selection pipe; a controller configured to controllably select the line to turn off a bottom select pipe of a selected memory string and/or a non-selected memory string in a pre-pulse phase prior to a verify-read phase;
controlling the word line to make the memory cells in each memory string conductive;
the string select line is controlled to turn off the top select tube in the selected memory string and/or the top select tube in the non-selected memory string for pre-pulsing.
In an embodiment of the invention, the controller is further configured to control the string select line to turn off a top select pipe in the selected memory string and turn on a top select pipe in the non-selected memory string to pre-pulse the selected memory string in the pre-pulse phase.
In an embodiment of the invention, the controller is further configured to open a bottom select pipe of the selected memory string in the verification read phase; turning off a top selection pipe of the non-selected storage string and gating a top selection pipe of the selected storage string; and applying a turn-on voltage to the unselected word lines and a program verify voltage to the selected word line.
In an embodiment of the invention, the plurality of memory cell word lines are respectively connected to gates of the plurality of memory cells; the string selection line is connected with the grid electrode of the top selection tube; the ground selection line is connected with the grid electrode of the bottom selection tube.
In one embodiment of the present invention, the verify read phase follows the pre-pulse phase.
In an embodiment of the present invention, the non-volatile memory is a 3D NAND memory.
The invention also provides a verification reading method of the nonvolatile memory, wherein the nonvolatile memory comprises a memory cell array, the memory cell array comprises a plurality of memory strings, each memory string comprises a plurality of memory cells, a bottom selection pipe and a top selection pipe, and the nonvolatile memory also comprises a plurality of word lines, a ground selection line and a string selection line; the word lines are respectively connected with the memory cells, the string selection line is connected to the top selection tube, and the ground selection line is connected to the bottom selection tube; the method includes in a pre-pulse phase prior to a verify read phase, controllably selecting a line to turn off a bottom select pipe of a selected memory string and/or a non-selected memory string; controlling the word line to make the memory cells in each memory string conductive; the string select line is controlled to turn off the top select tube in the selected memory string and/or the top select tube in the non-selected memory string for pre-pulsing.
In an embodiment of the invention, in the pre-pulse phase, the method controls the string selection line to turn off the top selection pipe in the selected memory string and turn on the top selection pipe in the non-selected memory string to pre-pulse the selected memory string.
In an embodiment of the invention, the method further comprises, in the verification read phase, opening a bottom select pipe of the selected memory string; turning off a top selection pipe of the non-selected storage string and gating a top selection pipe of the selected storage string; and applying a turn-on voltage to the unselected word lines and a program verify voltage to the selected word line.
The present invention also provides a method of programming a nonvolatile memory including a memory cell array including a plurality of memory cells, the method including the steps of:
applying a program signal to the plurality of memory cells; program verifying the plurality of memory cells according to the method of any one of the preceding claims.
Compared with the prior art, the invention has the following advantages: during a pre-pulse prior to a verify read phase of the non-volatile memory, the bottom select transistors of the select and/or non-select strings are turned off, so in the pre-pulse phase, the transistors of the memory cells of the select or non-select strings are not turned on, thereby reducing power consumption. Meanwhile, in the technical scheme of the application, in the pre-pulse stage, for the non-selected memory strings, the non-selected word lines are gated; for the selected memory string, the selected word line is strobed. Therefore, the technical scheme of the application can also realize the prevention of hot carrier injection crosstalk between the storage strings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principle of the invention. In the drawings:
FIG. 1 is a functional block diagram of a non-volatile memory according to an embodiment of the present invention.
FIG. 2 is a circuit schematic of a memory array that can be used in embodiments of the invention.
FIG. 3 is a waveform diagram of a non-volatile memory programming in a pre-pulse phase and a read phase according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating the comparison between the power consumption of the non-volatile memory in the pre-pulse phase and the power consumption of the prior art in the pre-pulse phase.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
In the description of the present application, it is to be understood that the orientation or positional relationship indicated by the directional terms such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal" and "top, bottom", etc., are generally based on the orientation or positional relationship shown in the drawings, and are used for convenience of description and simplicity of description only, and in the case of not making a reverse description, these directional terms do not indicate and imply that the device or element being referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore, should not be considered as limiting the scope of the present application.
Flow charts are used herein to illustrate operations performed by systems according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes.
Embodiments of the present application describe a non-volatile memory and a method of programming the same.
FIG. 1 is a functional block diagram of a non-volatile memory according to an embodiment of the present invention. Referring to fig. 1, the nonvolatile memory includes a memory cell array 11 and a controller 12. The memory cell array 11 includes a plurality of memory cells, which may be flash memory cells, such as 3D NAND flash memory cells.
In the present embodiment, each memory cell included in the memory cell array 11 may be a single-level memory cell SLC in which 1-bit data is stored, or a multi-level memory cell (MLC) in which 2-bit or more data may be stored, such as MLC, TLC, QLC, and the like, or any combination of a single-level memory cell and a multi-level memory cell.
In the present embodiment, the memory cells in the memory cell array 11 may be connected to word lines WL and bit lines BL. Meanwhile, the memory cell array 11 may also be connected to other selection lines such as a string selection line SSL, a ground selection line GSL, and the like. Specifically, the memory cell array 11 may be connected to a word line decoder 15 via a word line WL or a select line (SSL and/or GSL), and further connected to a voltage generator 16. The memory cell array 11 may be connected to a bit line decoder 13 via a bit line BL and further connected to an input/output (I/O) circuit 14. The controller 12 is connected to a bit line decoder 13, an I/O circuit 14, a word line decoder 15, and a voltage generator 16, respectively.
When it is desired to perform an erase, program, read-write or verify operation on one or more memory cells, the controller 12 may send the address of the one or more memory cells to the bit line decoder 13 and the word line decoder 15, and then addressed via the bit line decoder 13 by the bit line BL, and via the word line decoder 15 by the word line WL.
In some embodiments, the functions of bit line decoder 13 and word line decoder 15 may be implemented by a unified address decoder. The address decoder may also include components such as an address buffer.
The I/O circuit 14 may receive data from the controller 12 and/or the outside and store the received data in the memory cell array 11 for a write operation on the one hand, and may read data from the memory cell array 11 and output the read data to the controller 12 and/or the outside for a read operation on the other hand.
The voltage generator 16 may generate various voltages for performing operations of erasing, programming, reading, writing, verifying, and the like on the memory cell array 11 in response to a control signal from the controller 12. Specifically, the voltage generator 16 may generate word line voltages, such as a program voltage (or a write voltage), a program inhibit voltage, a read voltage, a verify voltage, and the like. The voltage generator 16 may generate a bit line voltage, such as a bit line force voltage or an inhibit voltage.
The controller 12 may output control signals to the bit line decoder 13, the I/O circuit 14, the word line decoder 15, and the voltage generator 16. For example, the controller 12 may output a voltage control signal to the voltage generator 16, a word line address to the word line decoder 15, a bit line address to the bit line decoder 13, write data to the I/O circuit 14, and read data from the I/O circuit 14.
In some embodiments, the controller 12 controls the bit line decoder 13 to select some bit lines BL and controls the word line decoder 15 to select some bit lines WL, and the voltage generator 16 applies a certain voltage to these bit lines BL and word lines WL. For example, during a read operation, a read voltage may be applied to a selected word line WL, and for a memory cell inhibited from reading, a read inhibit voltage may be applied to unselected bit lines BL. During a program operation, a program voltage and a verify voltage may be applied to a selected word line WL, and a program inhibit voltage may be applied to unselected bit lines BL.
The controller 12 of the present embodiment may also include components such as a processor, I/O interfaces, and the like. The control logic of controller 12 to bit line decoder 13, I/O circuit 14, word line decoder 15, and voltage generator 16 is not limited to the above. The controller 12 may also implement any other logic control functions for the non-volatile memory as will be appreciated by those skilled in the art.
In some embodiments, the controller 12 may instruct the memory cell array 11 to perform a desired memory operation based on software.
The memory cell array 11 may include a plurality of memory strings (strng). Each Memory string includes a plurality of Memory Cells (MC), and further includes a bottom select pipe (BSG) and a top select pipe (TSG).
FIG. 2 is a circuit schematic of a memory array that can be used in embodiments of the invention. In fig. 2, each black solid dot represents one memory cell. The storage array structure comprises a plurality of storage units which are arranged in a three-dimensional space in an array mode to form a plurality of storage strings, and channels of the storage units in the same storage string are physically connected. The transistor at the top of each memory string is a top selection tube, the top selection tube is connected to a bit line, the transistor at the bottom of the memory string is a bottom selection tube, and different memory strings are distinguished through the top selection tube and the bottom selection tube. The gates of the memory cells in different memory strings but in the same memory row are physically connected and are all connected to the same word line.
When a certain memory cell in the memory structure is read, a memory string and a row of the selected memory cell are determined, the memory string of the selected memory cell is used as a selected memory string, and the row of the selected memory cell is used as a selected row. For example, to read the information of the selected memory cell 201 in fig. 2, it is necessary to apply a driving voltage to a string selection line and a ground selection line, respectively turn on the top selection transistor 1 and the bottom selection transistor 1 of the selected memory string in which the selected memory cell is located, and apply a turn-on voltage to the word lines 1 and 3 of the non-selected rows other than the row in which the memory cell is located, thereby turning on the channel of the selected memory string; the top selection tube 2 and the bottom selection tube 2 of the non-selection storage string are turned off, and channels of other non-selection storage strings are prevented from being conducted; a read voltage is applied to the word line 2 in the selected row to read information in the selected memory cell.
And the memory string where the memory cell to be read is located is used as a selected memory string, the memory row where the memory cell to be read is located is used as a selected row, and the word line connected to the selected row is used as a selected word line. According to the technical scheme, a pre-pulse stage exists before the memory cell is read.
FIG. 3 is a waveform diagram of a non-volatile memory programming in a pre-pulse phase and a read phase according to an embodiment of the present invention.
In one embodiment, as illustrated in fig. 3, in a pre-pulse phase prior to a verify read phase of a memory, a controller of a non-volatile memory is configured to: the control ground select line turns off the bottom select pipe of the selected memory string and/or the non-selected memory string. In some cases, for example, the bottom select pipes of both selected and non-selected memory strings are turned off. At the same time, the word lines are controlled to turn on the memory cells in each memory string, and the string selection lines are controlled to turn off the top selection transistors in the selected memory string and/or the top selection transistors in the unselected memory string for pre-pulsing.
In some embodiments, during a verify read phase of the non-volatile memory, the bottom select pipe of the selected memory string is turned on (i.e., turned on); turning off a top selection pipe of the non-selected storage string and gating a top selection pipe of the selected storage string; and applying a pass voltage to the unselected word lines and a program verify voltage to the selected word line, the Vpv1, Vpv2 being, for example, different levels of program verify voltages. The verify read phase may be immediately adjacent to the pre-pulse phase. In one embodiment, the bottom select pipes of the selected memory string and the non-selected memory string are opened in the verify-read phase, and in an actual situation, if the bottom select pipes of the selected memory string or the non-selected memory string are already in an open state in the previous pre-pulse phase, the open phase is maintained in the verify-read phase. If the selected memory string or the non-selected memory string is in the off state during the previous pre-pulse phase, the bottom select transistor of the selected memory string or the non-selected memory string needs to be turned on during the verify read phase, as illustrated by the waveforms of FIG. 3.
The selected memory string is the memory string in which the memory cell 201 of the read data is located, and the rest are the non-selected memory strings. The selected memory string and the non-selected memory string may vary with the memory cell from which data is read during programming of the non-volatile memory, but at a particular time from which data is read, the selected memory string is determined.
FIG. 4 is a power consumption comparison diagram of non-volatile memory programming according to an embodiment of the invention.
In the technical solution of the present application, in the pre-pulse (pre) phase, the bottom selection transistors of the selected string and/or the unselected string are turned off, and specifically, for example, the bottom selection transistors may be controlled by controlling the voltage applied to the ground selection line connected to the gate of the bottom selection transistor. The transistors of the memory cells of the selected or non-selected string are not turned on during the pre-pulse phase, thereby reducing power consumption. Meanwhile, in the technical scheme of the application, in the pre-pulse stage, for the non-selected memory strings, the non-selected word lines are gated; for the selected memory string, the selected word line is strobed. That is, in the pre-pulse phase, the word lines are controlled to turn on the memory cells in each memory string. Therefore, the technical scheme of the application can also prevent Hot Carrier Injection (HCI) crosstalk between the storage strings.
The conduction of the memory cell does not mean the conduction of the memory string, and the conduction of the memory string also requires the corresponding control of the top selection pipe and the bottom selection pipe.
Through the operation of the pre-pulse stage, the threshold voltage of the memory cells in the memory array cannot be easily changed in the later verification reading stage, and the reading performance of the nonvolatile memory is ensured.
In the prior art, in the pre-read stage (which is actually the same time period as the pre-pulse stage in the present embodiment) before the read stage, both the bottom select transistor and the top select transistor of the selected memory string and the unselected memory string are turned on (i.e., turned on), and meanwhile, the word line of the memory cell of the unselected memory string needs to be set high to turn on the transistors corresponding to the plurality of memory cells. At this time, in the pre-read stage, the power consumption generated by the nonvolatile memory is large. For mobile devices, such as smart phones, the consumption of electric power is large, so that the endurance time of the devices is reduced, and the use experience of users is affected.
In the technical scheme of the present application, the pre-pulse stage before the read stage of the non-volatile memory is, as described above, turned off due to the bottom select transistor of the select string or the non-select string. The transistors of the memory cells of the selected or non-selected string are not turned on during the pre-pulse phase, thereby reducing power consumption. Meanwhile, in the technical scheme of the application, in the pre-pulse stage, for the non-selected memory strings, the non-selected word lines are gated; for the selected memory string, the selected word line is strobed. Therefore, the technical scheme of the application can also prevent Hot Carrier Injection (HCI) crosstalk between the storage strings.
FIG. 4 is a diagram illustrating a comparison between the power consumption of the non-volatile memory in the pre-pulse phase according to an embodiment of the present application and the power consumption of the prior art. As can be seen from fig. 4, the technical solution of the present application significantly reduces the value of the parameter Icc characterizing the peak power consumption during the pre-pulse phase of the program verification of the non-volatile memory, compared to the prior art. According to the test, in the pre-pulse stage of the programming verification of the nonvolatile memory, under the condition that the selection tubes at the bottoms of the selection string and the non-selection string are both turned off, the peak power consumption can be reduced by 17 percent, so that the power consumption of the equipment is reduced, the endurance time of the equipment is favorably prolonged, and the user experience is ensured.
The application also provides a verification reading method of the nonvolatile memory, wherein the nonvolatile memory comprises a memory cell array, the memory cell array comprises a plurality of memory strings, each memory string comprises a plurality of memory cells, a bottom selection tube and a top selection tube, and the nonvolatile memory further comprises a plurality of word lines, a ground selection line and a string selection line; the word lines are respectively connected with the memory cells, the string selection line is connected to the top selection tube, and the ground selection line is connected to the bottom selection tube.
In some embodiments, a verify-read method for a non-volatile memory includes, in a pre-pulse phase prior to a verify-read phase, controllably turning off a bottom select pipe of a selected memory string and/or a non-selected memory string; controlling the word line to make the memory cells in each memory string conductive; the string select line is controlled to turn off the top select tube in the selected memory string and/or the top select tube in the non-selected memory string for pre-pulsing.
In another embodiment, a program verification method of a non-volatile memory, in a pre-pulse phase, a string select line is controlled to turn off a top select pipe in a selected memory string and turn on a top select pipe in a non-selected memory string to pre-pulse the selected memory string.
In one embodiment, the program verification method of the non-volatile memory further includes, in a verification read phase, opening a bottom select pipe of a selected memory string; turning off a top selection pipe of the non-selected storage string and gating a top selection pipe of the selected storage string; and applying a turn-on voltage to the unselected word lines and a program verify voltage to the selected word line.
According to the verification reading method of the nonvolatile memory, the peak power consumption of the pre-pulse stage of the programming verification of the nonvolatile memory can be reduced, so that the power consumption of equipment is reduced, and the service life of the equipment is prolonged.
The present application also provides a method of programming a non-volatile memory, the method comprising the steps of: applying a program signal to the plurality of memory cells; program verification is performed on a plurality of memory cells of the non-volatile memory according to the aforementioned method.
In the technical scheme of the application, the pre-pulse phase and the verification read phase can be combined to be called a program verification phase. The program verify phase is after the program phase.
Having thus described the basic concept, it will be apparent to those skilled in the art that the foregoing disclosure is by way of example only, and is not intended to limit the present application. Various modifications, improvements and adaptations to the present application may occur to those skilled in the art, although not explicitly described herein. Such modifications, improvements and adaptations are proposed in the present application and thus fall within the spirit and scope of the exemplary embodiments of the present application.
Also, this application uses specific language to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.
It should be noted that in the foregoing description of embodiments of the present application, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to require more features than are expressly recited in the claims. Indeed, the embodiments may be characterized as having less than all of the features of a single embodiment disclosed above.
Although the present application has been described with reference to the present specific embodiments, it will be recognized by those skilled in the art that the foregoing embodiments are merely illustrative of the present application and that various changes and substitutions of equivalents may be made without departing from the spirit of the application, and therefore, it is intended that all changes and modifications to the above-described embodiments that come within the spirit of the application fall within the scope of the claims of the application.
Claims (10)
1. A non-volatile memory, comprising:
the storage unit array comprises a plurality of storage strings, wherein each storage string comprises a plurality of storage units, a bottom selection pipe and a top selection pipe;
a plurality of word lines respectively connected to the plurality of memory cells;
a string selection line connected to the top selection pipe;
a ground selection line connected to the bottom selection pipe;
a controller configured to, in a pre-pulse phase prior to a verify read phase,
controllably selecting the line to turn off the bottom select transistor of the selected memory string and/or the non-selected memory string;
controlling the word line to make the memory cells in each memory string conductive;
the string select line is controlled to cause the top select tube in the selected memory string and/or the top select tube in the non-selected memory string to be turned off for pre-pulsing throughout the pre-pulse phase.
2. The non-volatile memory of claim 1, wherein the controller is configured to, in the pre-pulse phase,
the string select line is controlled to turn off the top select transistor in the selected memory string and to turn on the top select transistor in the non-selected memory string to pre-pulse the selected memory string.
3. The non-volatile memory according to claim 1 or 2, wherein the controller is further configured in the verify read phase,
opening a bottom selection pipe of the selected storage string;
turning off a top selection pipe of the non-selected storage string and gating a top selection pipe of the selected storage string; and
a turn-on voltage is applied to unselected word lines and a program verify voltage is applied to a selected word line.
4. The nonvolatile memory according to claim 1, wherein gates of the plurality of memory cells are connected to a plurality of memory cell word lines, respectively;
the string selection line is connected with the grid electrode of the top selection tube;
the ground selection line is connected with the grid electrode of the bottom selection tube.
5. The non-volatile memory as claimed in claim 1, wherein the verify read phase follows the pre-pulse phase.
6. The non-volatile memory of claim 1, wherein the non-volatile memory is a 3D NAND memory.
7. A verification reading method of a nonvolatile memory comprises a memory cell array, wherein the memory cell array comprises a plurality of memory strings, each memory string comprises a plurality of memory cells, a bottom selection pipe and a top selection pipe, and the nonvolatile memory further comprises a plurality of word lines, a ground selection line and a string selection line; the word lines are respectively connected with the memory cells, the string selection line is connected to the top selection tube, and the ground selection line is connected to the bottom selection tube; the method includes in a pre-pulse phase prior to a verify read phase,
controllably selecting the line to turn off the bottom select transistor of the selected memory string and/or the non-selected memory string;
controlling the word line to make the memory cells in each memory string conductive;
the string select line is controlled to cause the top select tube in the selected memory string and/or the top select tube in the non-selected memory string to be turned off for pre-pulsing throughout the pre-pulse phase.
8. The verification read method of a nonvolatile memory according to claim 7, wherein, in the pre-pulse phase,
the string select line is controlled to turn off the top select transistor in the selected memory string and to turn on the top select transistor in the non-selected memory string to pre-pulse the selected memory string.
9. The verification read method of the nonvolatile memory according to claim 7 or 8, further comprising, in the verification read phase,
opening a bottom selection pipe of the selected storage string;
turning off a top selection pipe of the non-selected storage string and gating a top selection pipe of the selected storage string; and
a turn-on voltage is applied to unselected word lines and a program verify voltage is applied to a selected word line.
10. A method of programming a non-volatile memory, the non-volatile memory comprising a memory cell array, the memory cell array comprising a plurality of memory cells, the method comprising the steps of:
applying a program signal to the plurality of memory cells;
the method of any of claims 7-9, performing program verification on the plurality of memory cells.
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| US6014331A (en) * | 1998-08-27 | 2000-01-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Circuit for programming a programmable memory cell |
| CN1720587A (en) * | 2002-11-14 | 2006-01-11 | 柰米闪芯集成电路有限公司 | Combination nonvolatile memory using unified technology |
| CN101471047B (en) * | 2007-12-28 | 2011-02-02 | 联咏科技股份有限公司 | Apparatus for improving output voltage accuracy in source driver of LCD |
| KR20130003252A (en) * | 2011-06-30 | 2013-01-09 | 삼성디스플레이 주식회사 | Stage circuit and scan driver using the same |
| US20190311749A1 (en) * | 2018-04-09 | 2019-10-10 | Anaflash Inc. | Logic Compatible Embedded Flash Memory |
| CN109065091B (en) * | 2018-08-01 | 2022-11-08 | 长江存储科技有限责任公司 | Reading method of 3D NAND flash memory |
| CN110289034A (en) * | 2019-06-28 | 2019-09-27 | 长江存储科技有限责任公司 | Nonvolatile memory and its operating method |
| CN111758130B (en) * | 2020-05-19 | 2021-04-16 | 长江存储科技有限责任公司 | 3D NAND flash memory and operation method thereof |
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