CN112967352A - Multilayer logic picture generation method and device - Google Patents

Multilayer logic picture generation method and device Download PDF

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Publication number
CN112967352A
CN112967352A CN202110256894.0A CN202110256894A CN112967352A CN 112967352 A CN112967352 A CN 112967352A CN 202110256894 A CN202110256894 A CN 202110256894A CN 112967352 A CN112967352 A CN 112967352A
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module
fpga
coordinate
picture
image
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王斌
万勤华
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Suzhou Jiazhicai Optoelectronics Technology Co ltd
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Suzhou Jiazhicai Optoelectronics Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T11/00—2D [Two Dimensional] image generation
    • G06T11/001—Texturing; Colouring; Generation of texture or colour
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/451—Execution arrangements for user interfaces
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Abstract

The invention relates to a method and a device for generating a multilayer logic picture, comprising the following steps: s1, an upper computer edits images and synchronously previews the images, and generates a parameter file and then transmits the parameter file to an ARM; s2, reading the parameter file by the ARM, and sending the drawing parameters and the drawing area to the FPGA; s3, the FPGA carries out image drawing according to the drawing parameters and writes the image into a designated area of the memory; s4, after the FPGA finishes drawing of one layer of pictures, sending feedback information to the ARM, informing the ARM to continuously read the residual content in the parameter file and transmit the information of the next layer of pictures, and repeating the step S2; and S5, drawing a plurality of layers of logic pictures by multiple operations until the pictures are completely drawn, sending a command to inform the FPGA to display the pictures in the area by the ARM, and reading the images in the memory by the FPGA to refresh the images to the display. The ARM is used for managing the memory address and the flow, so that the resource consumption of the FPGA is reduced, and the flexibility of the system is improved. And the FPGA is used for drawing, so that higher real-time performance can be achieved. The advantages of ARM and FPGA are comprehensively utilized.

Description

Multilayer logic picture generation method and device
Technical Field
The invention relates to the field of display panel production detection, in particular to a method and a device for generating a multilayer logic picture.
Background
In the production process of the display panel, a plurality of different pictures are needed to detect the defects of the panel, however, the re-editing of the picture by the panel with different resolution ratio wastes time and labor, and the transmission and downloading of the image with large resolution ratio consumes longer time, which affects the production efficiency of the production line.
Disclosure of Invention
The invention provides a method and a device for generating a multilayer logic picture, aiming at realizing resolution self-adaptation, reducing repeated labor of re-editing pictures, improving the transmission efficiency of images and reducing the transmission time.
The invention provides a method for generating a multilayer logic picture, which comprises the following steps:
s1, an upper computer edits images and synchronously previews the images, and generates a parameter file and then transmits the parameter file to an ARM;
s2, the ARM reads the parameter file and sends the drawing parameters and the drawing area to the FPGA;
s3, the FPGA carries out image drawing according to the drawing parameters and writes the image into a target memory address;
s4, after the FPGA finishes drawing of one layer of pictures, sending feedback information to the ARM, informing the ARM to continuously read the content of the parameter file and transmit the information of the next layer of pictures, and repeating the step S2;
and S5, drawing a multilayer logic picture by multiple operations until no content remains in the parameter file, completely drawing the picture, sending a command by the ARM to inform the FPGA to switch the displayed frame address to the target memory address written just now, and displaying the drawn content to the display panel.
ARM is as the data transmission medium between host computer and the FPGA, ARM carries out the preliminary treatment to the parameter that FPGA needs to be drawn, drawing for FPGA transmitting, FPGA drawing mode adopts the one deck back of drawing, ARM just exports the picture data of next floor, the operation has reduced FPGA drawing processing's pressure like this, avoided data once only give too much to cause FPGA drawing processing speed to slow down, data extrusion or chaotic problem, FPGA's resource consumption has been reduced, and the flexibility of system has been improved.
As a further improvement of the present invention, the step S2 specifically further includes:
s21, reading the parameter file by the ARM, converting the proportion information into specific coordinate information according to the image resolution, and transmitting the coordinate information to the FPGA;
and S22, the ARM transmits the drawing parameters of the logic picture to the FPGA, and the drawing parameters comprise frame information, a target image memory address and resolution.
The ARM can directly read parameters, such as frame information, target image memory address and resolution, of the FPGA, and directly transmits the parameters to the FPGA; and for parameters which can not be directly read by the FPGA, the parameters are preprocessed, for example, information related to position coordinates is transmitted to the FPGA, the trouble of the FPGA in processing the data is reduced, and the FPGA can conveniently and rapidly draw.
As a further improvement of the present invention, the step S3 specifically includes:
s31, the command management module receives a command from the ARM and sends the drawing parameters to a drawing memory address and pixel coordinate generation module;
s32, the drawing memory address and pixel coordinate generating module generates a memory address and image X coordinates and image Y coordinates of a corresponding address according to resolution, layer initial coordinates and layer length and width in drawing parameters, and transmits the memory address and the image X coordinates and the image Y coordinates to the logic picture generating module and the layer outer frame generating module;
s33, generating an image outer frame by the image layer outer frame generating module, displaying a logic picture in the image outer frame, and displaying a lower layer picture outside the outer frame;
s34, the logic picture generation module calculates and draws a logic picture according to X, Y coordinates of the pixels;
s35, the logic picture generation module, the drawing memory address and the pixel coordinate generation module are synchronously output to the memory access arbitration module, and the picture is written into the target memory address by the memory access arbitration module.
And each module in the FPGA is drawn into an image according to the parameters, so that the required layer of logic picture is drawn and stored in a memory, the function of drawing the FPGA is fully used, and higher real-time performance is achieved.
As a further improvement of the present invention, the step S32 specifically includes:
generation of coordinates and memory addresses: the drawing memory address and pixel coordinate generating module generates an accumulated X coordinate and Y coordinate according to the frame address and the resolution information transmitted by the ARM, and the accumulated X coordinate and the accumulated Y coordinate are cleared and the counting is restarted until the coordinate is accumulated to a horizontal or vertical resolution value; every time the coordinates are cleared, the memory addresses are accumulated by one layer.
In the drawing, after the X coordinate and the Y coordinate are accumulated to the top value of the resolution ratio, the drawing of a layer of image is completed, the drawn layer of image is stored in a memory, the coordinates are cleared to draw the next layer of image, meanwhile, the memory addresses are accumulated by one layer, and a space is reserved for storing the next layer of image. The image data of each layer is stored in sequence, the FPGA can draw in order, and the storage speed of the FPGA after drawing is improved.
As a further improvement of the present invention, the step S33 specifically includes: judging whether the pixel point is inside the outer frame or outside the outer frame according to the shape of the outer frame:
s331, judging a rectangular outer frame: from the X, Y coordinate position of the image and the starting address X in the parameter0、Y0The length H and the height V of the rectangle are determined, when X is>X0、X<X0+H、Y>Y0、Y<Y0When the four conditions of + V are met, judging that the coordinate is in the rectangular outer frame, otherwise, judging that the coordinate is outside the rectangular outer frame;
s332, judging a circular outer frame: according to the centre coordinates X0、Y0Circle radius R, X, Y coordinate location of the image; when (X-X)0)2+(Y-Y0)2 < R2And judging that the coordinate is in the circular outer frame, otherwise, the coordinate is outside the circular outer frame.
According to the needs of the image, the shape of the outer frame of the image can be diversified, but the data of the outer frames with different shapes can be represented by coordinates, the position outside the inner frame of the frame can be judged through coordinate operation, the positioning can be more accurate, the data reading is convenient, and the error rate is low.
As a further improvement of the present invention, in step S34, the picture types of the logical picture include: gradient pictures, pure color pictures, flick pictures, checkerboard pictures. The logical picture can be selected according to the detection requirement, and the method can also adapt to the application of various different types of pictures.
As a further improvement of the present invention, step S34 includes: and (3) generating a checkerboard picture:
s341, setting the initial coordinate X of the chessboard according to the X, Y coordinate position of the pixel coordinate generating module0、Y0Width H of the checkerboard in the horizontal direction, height V of the checkerboard in the vertical direction, color C1Color C2；
S342. when X = X0While emptying XCNTCounter, XFLAGSet to 0, update X each timeCNT+1, up to XCNTAdding up to the H value, then zero clearing XCNTAnd mixing XFLAGTaking the inverse;
s343. when Y = Y0While, empty YCNTCounter, YFLAGSet to 0, and update Y each time Y is updatedCNT+1, up to YCNTAdding up to the value of V and then zero clearing YCNTAnd a radical of YFLAGTaking the inverse;
s344. mixing YFLAGAnd XFLAGThe same region is set to color C1Is a reaction of YFLAGAnd XFLAGThe different regions are set to color C2。
The color data in the checkerboard is obtained through coordinate operation, and the checkerboard logic image can be drawn more accurately.
As a further improvement of the present invention, step S34 includes: generation of a gradient picture:
s345, setting a starting coordinate X according to the X, Y coordinate position of the pixel coordinate generating module0、Y0Each time of gradual change of brightness value CXInitial color C0The width H of each gradient, the gradient direction DIR;
s346. when X = X0When, the color is set to C0，XCNTSet to 0, every time X changes, XCNTPlus one when XCNTWhen H is added, XCNTZero clearing, color value increasing or decreasing CX；
S347. when Y = Y0When, the color is set to C0，YCNTSet to 0, every time Y changes, YCNTPlus one when YCNTWhen H is added, YCNTZero clearing, color value increasing or decreasingLess CY。
The color data of the gradual change picture is obtained through coordinate operation, and the logic image of the gradual change picture can be drawn more accurately.
The invention provides a multilayer logic picture generation device which comprises an upper computer, an ARM processor, an FPGA module, a memory and a display, wherein the output end of the upper computer is connected with the ARM processor through an interface, the ARM processor is connected with the FPGA module and is in signal intercommunication with the FPGA module, the memory is connected with the FPGA module and is in signal intercommunication with the FPGA module, and the display is connected with the FPGA module and is in signal intercommunication with the FPGA module. The ARM process is used as a data transmission medium between the upper computer and the FPGA module, and memory addresses and flows are managed in the multi-layer logic picture generation process, so that the FPGA module can conveniently and rapidly draw and output and store images.
As a further improvement of the present invention, the FPGA module includes a command management module, a drawing address and pixel coordinate generation module, a logical picture generation module, a layer outer frame generation module, a memory access arbitration module, and a display driving module, one end of the command management module is connected to the ARM processor and receives a command from the ARM processor, the other end of the command management module is connected to the drawing address and pixel coordinate generation module and outputs an image parameter to the drawing address and pixel coordinate generation module, the drawing address and pixel coordinate generation module is connected to the layer outer frame generation module and outputs an image parameter and a pixel coordinate to the layer outer frame generation module, the drawing address and pixel coordinate generation module is connected to the logical picture generation module and outputs an image parameter and a pixel coordinate to the logical picture generation module, the drawing address and pixel coordinate generation module is connected to the memory access module and outputs a memory address to the memory access module, the layer outer frame generation module is connected to the logical picture generation module and outputs a parameter in The layer outer frame generating module is connected with the memory access arbitration module and outputs image data to the memory access arbitration module, and the memory access arbitration module is connected with the display driving module and outputs image pictures to the display driving module. And each submodule in the FPGA module finishes drawing through transmission of information data, and the drawing function of the FPGA is realized.
The invention has the beneficial effects that: the ARM is used for managing the memory address and the flow, so that the resource consumption of the FPGA is reduced, and the flexibility of the system is improved. And the FPGA is used for drawing, so that higher real-time performance can be achieved. The respective advantages of the ARM and the FPGA are comprehensively utilized.
Drawings
FIG. 1 is a block diagram of a multi-layer logical picture generating apparatus according to the present invention;
FIG. 2 is a block diagram of the FPGA module of the present invention;
FIG. 3 is a diagram of the final effect of checkerboard logical picture generation in the present invention;
fig. 4 is a diagram of the final effect of the gradual logical picture generation in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments.
The first embodiment is as follows:
as shown in fig. 1, the method for generating a multi-layer logical picture of the present invention is based on upper computer software, where the FPGA is matched with the ARM processor: the method comprises the following steps:
s1, an upper computer edits images and synchronously previews the images, and generates a parameter file and then transmits the parameter file to an ARM;
s2, the ARM reads the parameter file and sends the drawing parameters and the drawing area to the FPGA;
s3, the FPGA carries out image drawing according to the drawing parameters and writes the image into a target memory address;
s4, after the FPGA finishes drawing of one layer of pictures, sending feedback information to the ARM, informing the ARM to continuously read the content of the parameter file and transmit the information of the next layer of pictures, and repeating the step S2;
and S5, drawing a multilayer logic picture by multiple operations until no content remains in the parameter file, completely drawing the picture, sending a command by the ARM to inform the FPGA to switch the displayed frame address to the target memory address written just now, and displaying the drawn content to the display panel.
And editing the picture through the upper computer, and synchronously previewing the picture to generate a parameter file. The ARM receives a parameter file generated by the upper computer, converts the proportion information into specific coordinate information according to the resolution ratio, and transmits the coordinate information to the FPGA; and simultaneously, other specific parameters of the logic picture are as follows: and frame information, target image memory address, resolution and the like are transmitted to the FPGA.
The FPGA generates a layer of picture according to the parameters transmitted by the ARM, then sends feedback information to the ARM, informs the ARM to continuously transmit the information of the next layer of picture until the picture is completely drawn, and informs the FPGA to switch the address of the display module and switch to the picture for display. The ARM is used as a transitional unit, the parameters of each layer are analyzed one by one, and then the information layer by layer is sequentially transmitted to the FPGA for production, so that redundancy of excessive data sent once in the FPGA can be avoided, confusion when the FPGA processes and generates images is avoided, the operating pressure of the FPGA is reduced, the resource consumption of the FPGA is reduced, and the flexibility of the system is improved. And the display panel is generally not provided with a display memory, can only receive a complete frame of image at a time and cannot transmit the image layer by layer, so that the FPGA generates the image layer by layer and then uses a target memory address as buffer memory, and the multi-layer image is uniformly displayed on the display panel after the target memory address is combined, thereby solving the problem that the display panel cannot transmit the image layer by layer, and ensuring that the finally combined image can be centralized and synchronized on the display panel in real time.
Wherein, step S2 of ARM transmitting information to FPGA specifically further includes:
s21, reading the parameter file by the ARM, converting the proportion information into specific coordinate information according to the image resolution, and transmitting the coordinate information to the FPGA;
and S22, the ARM transmits the drawing parameters of the logic picture to the FPGA, and the drawing parameters comprise frame information, a target image memory address and resolution.
And the upper computer transmits the edited parameter file to the ARM, and the ARM controls the FPGA to perform the image drawing process and address management. The ARM converts the proportion into specific coordinates according to the image resolution and the proportion information in the parameter file, and can realize resolution self-adaptation.
Example two:
as shown in fig. 2, on the basis of the first embodiment, the specific flow step S3 of drawing by the FPGA includes:
s31, the command management module receives a command from the ARM and sends the drawing parameters to a drawing memory address and pixel coordinate generation module;
s32, the drawing memory address and pixel coordinate generating module generates a memory address and image X coordinates and image Y coordinates of a corresponding address according to resolution, layer initial coordinates and layer length and width in drawing parameters, and transmits the memory address and the image X coordinates and the image Y coordinates to the logic picture generating module and the layer outer frame generating module;
s33, the image layer outer frame generating module generates an image outer frame, wherein the shape of the outer frame can be rectangular, circular and other outer frames, and the final effect is that a logic picture is displayed inside the image outer frame, and the outer part of the outer frame is displayed to be transparent, namely a lower-layer picture;
s34, the logic picture generation module calculates and draws a logic picture according to X, Y coordinates of the pixels, and the specific picture types comprise: gradient pictures, pure color pictures, flick pictures, checkerboard pictures, etc.;
s35, a logic picture generation module, a drawing memory address and pixel coordinate generation module are synchronously output to a memory access arbitration module, and the picture is written into a target memory address by the memory access arbitration module.
Example three:
as shown in fig. 1 and fig. 2, before drawing by the FPGA, the ARM first transmits a target memory address of a picture to the FPGA, and then the ARM stores a parameter file transmitted from the upper computer, which is received by interfaces such as a network port/USB, on a local file system, and analyzes parameters in the file: and the frame type, the coordinate of the frame and the size information are transmitted to the FPGA one by one. The ARM converts the proportional relation into specific coordinates according to the picture resolution and then transmits the specific coordinates to the FPGA, and the FPGA is responsible for specific drawing work. And when the FPGA finishes the drawing of one layer of image layer, the ARM is informed, the ARM continues to read the residual content in the file, the next operation is carried out until no residual content exists in the file, the ARM informs the FPGA to switch the displayed frame address to the address of the image which is written just now, and the drawn content is displayed on the display panel.
When the FPGA draws, the embodiment of each part in the image is generated as follows:
generation of coordinates and memory addresses:
the memory address and pixel coordinate generating module generates an accumulated X coordinate and Y coordinate according to the frame address and the resolution information transmitted by the ARM, and the counting is restarted after the coordinates are accumulated to the horizontal/vertical resolution. Correspondingly, the memory addresses are also accumulated all the time, so that the image data generated by other modules can be in one-to-one correspondence with the memory addresses.
Outer frame generation:
the rectangular outer frame requires parameters: the rectangular outer frame can be determined according to the X, Y coordinate position of the pixel coordinate generating module and the starting address X in the parameter0、Y0The length H and the height V of the rectangle are determined, when X is>X0、X<X0+H、Y>Y0、Y<Y0And if the four conditions of + V are met, judging that the coordinate is in the rectangular outer frame, otherwise, judging that the coordinate is outside the rectangular outer frame.
The circular outer frame requires parameters: circle center coordinate X0、Y0Circle radius R, the X, Y coordinate location of the pixel coordinate generation module. When (X-X)0)2+(Y-Y0)2 < R2When the coordinate is in the circular outer frame, the coordinate can be judged, otherwise, the coordinate is outside the circular outer frame.
And (3) generating a logical picture:
generating a checkerboard picture: requires the start coordinate (X) of the board0、Y0) Width H of the checkerboard in the horizontal direction, height V of the checkerboard in the vertical direction, color C1Color C2The pixel coordinates generate the X, Y coordinate location of the module. When X = X0While emptying XCNTCounter, XFLAGSet to 0, update X each timeCNT+1, up to XCNTAdding up to the H value, then zero clearing XCNTAnd mixing XFLAGAnd (6) taking the inverse. Similarly, when Y = Y0While, empty YCNTCounter, YFLAGSet to 0, and update Y each time Y is updatedCNT+1, up to YCNTAdding up to the value of V and then zero clearing YCNTAnd a radical of YFLAGAnd (6) taking the inverse. Thus Y can be substitutedFLAGAnd XFLAGThe same region is set to color C1Is a reaction of YFLAGAnd XFLAGThe different regions are set to color C2. The final effect is shown in fig. 3. The pure color picture only needs the color C of the picture1And filling the memory.
XCNT The counter indicating the horizontal direction, i.e. the pixel which is the second pixel in the horizontal direction, YCNT Similarly, the counter represents the vertical direction; xFLAG An odd-even flag bit indicating the horizontal direction, the first lattice being 0, the second lattice being 1, the third lattice being 0, and so on, YFLAGThe same is true.
In the generation process of the checkerboard logical picture, X is added after X, Y is updated every timeCNT、YCNTAccumulating X after full valueFLAG、YFLAGThe operation mode of negation is simple to realize, a multiplier and a divider are not needed, the complexity in the operation process is reduced, the occupation of logic resources is less, the operation is quick, and the flexibility of the system is improved.
Gradual change of pictures:
requires a starting coordinate X0、Y0X, Y coordinate position of pixel coordinate generating module, brightness value C of each gradual changeXInitial color C0The width H of each gradient, the gradient direction DIR. Take a horizontal gradation example when X = X0When, the color is set to C0，XCNTSet to 0, every time X changes, XCNTPlus one when XCNTWhen H is added, XCNTZero clearing, color value increasing or decreasing CX. The final effect is shown in fig. 4. Similarly, for the example of vertical tapering, when Y = Y0When, the color is set to C0，YCNTSet to 0, every time Y changes, YCNTPlus one when YCNTWhen H is added, YCNTZero clearing, color value increasing or decreasing CY。
Wherein, XCNT、YCNTMeaning the same as a checkerboard, DIR denotes direction, only horizontal/vertical, and fig. 4 is a horizontal progression.
By "whenever X changes, XCNTPlus one when XCNTWhen H is added, XCNTZero clearing, color value increasing or decreasing CX"OR" whenever Y changes, YCNTPlus one when YCNTWhen H is added, YCNTZero clearing, color value increasing or decreasing CYThe method is simple to realize, occupies less logic resources, does not need a multiplier or a divider, has quick operation and improves the flexibility of the system when generating the gradual change picture.
Example four:
as shown in fig. 1 and fig. 2, when implementing a multi-layer logical picture generating method, the multi-layer logical picture generating device provided by the present invention includes an upper computer 1, an ARM processor 2, an FPGA module 3, a memory 4, and a display 5, wherein an output end of the upper computer 1 is connected to the ARM processor 2 through an interface, the ARM processor 2 is connected to the FPGA module 3 and communicates with the FPGA module 3, the memory 4 is connected to the FPGA module 3 and communicates with the FPGA module 3, and the display 5 is connected to the FPGA module 3 and communicates with the FPGA module 3.
Wherein, the FPGA module 3 includes a command management module 31, a drawing address and pixel coordinate generating module 32, a logical picture generating module 33, a layer outer frame generating module 34, a memory access arbitration module 35, and a display driving module 36, one end of the command management module 31 is connected with the ARM processor 2 and receives a command from the ARM processor 2, the other end of the command management module 31 is connected with the drawing address and pixel coordinate generating module 32 and outputs an image parameter to it, the drawing address and pixel coordinate generating module 32 is connected with the layer outer frame generating module 34 and outputs an image parameter and a pixel coordinate to it, the drawing address and pixel coordinate generating module 32 is connected with the logical picture generating module 33 and outputs an image parameter and a pixel coordinate to it, the drawing address and pixel coordinate generating module 32 is connected with the memory access arbitration module 35 and outputs a memory address to it, the layer outer frame generating module 34 is connected with the logical picture generating module 33 and outputs a parameter in an outer frame boundary to it, the layer frame generating module 34 is connected to the memory access arbitration module 35 and outputs image data to the memory access arbitration module 35, and the memory access arbitration module 35 is connected to the display driving module 36 and outputs image frames to the display driving module 36.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (10)

1.A method for generating a multi-layer logical picture, comprising the steps of:
s1, an upper computer edits images and synchronously previews the images, and generates a parameter file and then transmits the parameter file to an ARM;
s2, the ARM reads the parameter file and sends the drawing parameters and the drawing area to the FPGA;
s3, the FPGA carries out image drawing according to the drawing parameters and writes the image into a target memory address;
s4, after the FPGA finishes drawing of one layer of pictures, sending feedback information to the ARM, informing the ARM to continuously read the content of the parameter file and transmit the information of the next layer of pictures, and repeating the step S2;
and S5, drawing a multilayer logic picture by multiple operations until no content remains in the parameter file, completely drawing the picture, sending a command by the ARM to inform the FPGA to switch the displayed frame address to the target memory address written just now, and displaying the drawn content to the display panel.
2. The method for generating a multi-layer logical screen according to claim 1, wherein the step S2 further includes:
s21, reading the parameter file by the ARM, converting the proportion information into specific coordinate information according to the image resolution, and transmitting the coordinate information to the FPGA;
and S22, the ARM transmits the drawing parameters of the logic picture to the FPGA, and the drawing parameters comprise frame information, a target image memory address and resolution.
3. The method for generating a multi-layer logical screen according to claim 1, wherein the step S3 specifically includes:
s31, the command management module receives a command from the ARM and sends the drawing parameters to a drawing memory address and pixel coordinate generation module;
s32, the drawing memory address and pixel coordinate generating module generates a memory address and image X coordinates and image Y coordinates of a corresponding address according to resolution, layer initial coordinates and layer length and width in drawing parameters, and transmits the memory address and the image X coordinates and the image Y coordinates to the logic picture generating module and the layer outer frame generating module;
s33, generating an image outer frame by the image layer outer frame generating module, displaying a logic picture in the image outer frame, and displaying a lower layer picture outside the outer frame;
s34, the logic picture generation module calculates and draws a logic picture according to X, Y coordinates of the pixels;
s35, the logic picture generation module, the drawing memory address and the pixel coordinate generation module are synchronously output to the memory access arbitration module, and the picture is written into the target memory address by the memory access arbitration module.
4. The method for generating a multi-layer logical screen according to claim 3, wherein the step S32 specifically includes:
generation of coordinates and memory addresses: the drawing memory address and pixel coordinate generating module generates an accumulated X coordinate and Y coordinate according to the frame address and the resolution information transmitted by the ARM, and the accumulated X coordinate and the accumulated Y coordinate are cleared and the counting is restarted until the coordinate is accumulated to a horizontal or vertical resolution value; every time the coordinates are cleared, the memory addresses are accumulated by one layer.
5. The method for generating a multi-layer logical screen according to claim 3, wherein the step S33 specifically includes: judging whether the pixel point is inside the outer frame or outside the outer frame according to the shape of the outer frame:
s331, judging a rectangular outer frame: from the X, Y coordinate position of the image and the starting address X in the parameter0、Y0The length H and the height V of the rectangle are determined, when X is>X0、X<X0+H、Y>Y0、Y<Y0When the four conditions of + V are all satisfied, the seat is judgedMarking the coordinate in the rectangular outer frame, otherwise, the coordinate is outside the rectangular outer frame;
s332, judging a circular outer frame: according to the centre coordinates X0、Y0Circle radius R, X, Y coordinate location of the image; when (X-X)0)2+(Y-Y0)2 < R2And judging that the coordinate is in the circular outer frame, otherwise, the coordinate is outside the circular outer frame.
6. The multi-layer logical picture generation method according to claim 3, wherein in step S34, the picture types of the logical picture include: gradient pictures, pure color pictures, flick pictures, checkerboard pictures.
7. The multi-layer logical picture generation method according to claim 6, wherein said step S34 includes: and (3) generating a checkerboard picture:
s341, setting the initial coordinate X of the chessboard according to the X, Y coordinate position of the pixel coordinate generating module0、Y0Width H of the checkerboard in the horizontal direction, height V of the checkerboard in the vertical direction, color C1Color C2；
S342. when X = X0While emptying XCNTCounter, XFLAGSet to 0, update X each timeCNT+1, up to XCNTAdding up to the H value, then zero clearing XCNTAnd mixing XFLAGTaking the inverse;
s343. when Y = Y0While, empty YCNTCounter, YFLAGSet to 0, and update Y each time Y is updatedCNT+1, up to YCNTAdding up to the value of V and then zero clearing YCNTAnd a radical of YFLAGTaking the inverse;
s344. mixing YFLAGAnd XFLAGThe same region is set to color C1Is a reaction of YFLAGAnd XFLAGThe different regions are set to color C2。
8. The multi-layer logical picture generation method according to claim 6, wherein said step S34 includes: generation of a gradient picture:
s345, setting a starting coordinate X according to the X, Y coordinate position of the pixel coordinate generating module0、Y0Each time of gradual change of brightness value CXInitial color C0The width H of each gradient, the gradient direction DIR;
s346. when X = X0When, the color is set to C0，XCNTSet to 0, every time X changes, XCNTPlus one when XCNTWhen H is added, XCNTZero clearing, color value increasing or decreasing CX；
S347. when Y = Y0When, the color is set to C0，YCNTSet to 0, every time Y changes, YCNTPlus one when YCNTWhen H is added, YCNTZero clearing, color value increasing or decreasing CY。
9. A multi-layer logic picture generation device based on the method of any one of claims 1 to 8, comprising an upper computer, an ARM processor, an FPGA module, a memory and a display, wherein the output end of the upper computer is connected with the ARM processor through an interface, the ARM processor is connected with the FPGA module and is in signal communication with the FPGA module, the memory is connected with the FPGA module and is in signal communication with the FPGA module, and the display is connected with the FPGA module and is in signal communication with the FPGA module.
10. The multi-layer logical picture generating apparatus according to claim 9, wherein the FPGA module includes a command management module, a drawing address and pixel coordinate generating module, a logical picture generating module, a layer outer frame generating module, a memory access arbitration module, and a display driving module, one end of the command management module is connected to the ARM processor and receives a command from the ARM processor, the other end of the command management module is connected to the drawing address and pixel coordinate generating module and outputs an image parameter to the drawing address and pixel coordinate generating module, the drawing address and pixel coordinate generating module is connected to the layer outer frame generating module and outputs an image parameter and a pixel coordinate to the layer outer frame generating module, the drawing address and pixel coordinate generating module is connected to the logical picture generating module and outputs an image parameter and a pixel coordinate to the logic picture generating module, the drawing address and pixel coordinate generating module is connected to the memory access arbitration module and outputs a memory address to the memory access arbitration module, the layer outer frame generating module is connected with the logic picture generating module and outputs parameters in the outer frame boundary to the logic picture generating module, the layer outer frame generating module is connected with the memory access arbitration module and outputs image data to the memory access arbitration module, and the memory access arbitration module is connected with the display driving module and outputs image pictures to the display driving module.
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