CN112953860A - Frame splitting control method compatible with HINOC2.0 and 3.0 protocols - Google Patents
Frame splitting control method compatible with HINOC2.0 and 3.0 protocols Download PDFInfo
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- H—ELECTRICITY
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Abstract
The invention belongs to the technical field of frame splitting of an HINOC3.0 system, and discloses a frame splitting control method, a system, a storage medium, a terminal and an application compatible with HINOC2.0 and 3.0 protocols, wherein a framework of a reordering function is realized through two sections of flow; and the framework of the frame splitting function is realized through two sections of flow lines. The speed of 10Gbps is supported, and the streamlined design is fully applied in the architecture design; various HINOC frame formats are supported, and the commonalities and differences of the various HINOC frame formats are considered in the architecture design so as to reduce the complexity of code design; the method supports the processing of various HINOC frames with errors caused by physical channels, and the unicast frames of non-HINOC 3.0 are subjected to artificial sequence number adding reordering operation in the architectural design to filter out various errors; various information frame processing is supported, the information frames are transparently transmitted in the reordering, and are reordered as intermediate fragments; and the complexity of splicing of the frame splitting device caused by large bit width is reduced.
Description
Technical Field
The invention belongs to the technical field of frame splitting of an HINOC3.0 system, and particularly relates to a frame splitting control method, a frame splitting control system, a frame splitting control storage medium, a frame splitting control terminal and application compatible with HINOC2.0 and 3.0 protocols.
Background
At present: the HINOC network of the coaxial cable can realize the bidirectional transmission of various high-speed data services only by adding relevant HINOC modulation and demodulation equipment head ends and terminals in corridors and indoors and without any modification on the line of the cable leading to the home. Ethernet carries ethernet data which is transported in a HINOC network as HINOC frames, and the ethernet data is passed through the HINOC network to a destination node, must be encapsulated into a HINOC frame format suitable for transport in the HINOC network, and decapsulated at the peer level. Through framing, a plurality of Ethernet frames can be packaged and encapsulated into one HINOC frame, the transmission efficiency of an HINOC network MAC layer is improved, and the protocol overhead is reduced. Meanwhile, according to the HINOC frame format and the packing rule, the method has the characteristics of high speed and high efficiency in framing and unfreezing the EMAC frame in hardware.
Change on the framing side of the HINOC3.0 MAC layer: 1. the HINOC3.0 is that the framing module is placed before enqueuing, each framing instruction can be directly dequeued from a buffer memory, the dequeuing speed can reach 10Gbps line speed, and therefore the frame disassembling module needs to reach 10Gbps line speed; 2. since the equipment compatible with HINOC2.0 is required at HINOC3.0 equipment, the frame splitting module is required to support the resolution of the frame format of HINOC 2.0; 3. since HINOC3.0 unicast frames can be transmitted on each phy channel in HINOC3.0, the framing module needs to reorder the HINOC3.0 unicast frames due to the non-uniform rates of the phy channels.
Through the above analysis, the problems and defects of the prior art are as follows:
(1) as the HINOC3.0 is that the framing module is placed before enqueuing, each framing instruction can be directly dequeued from the buffer, the dequeuing speed can reach 10Gbps line speed, and the frame disassembling module needs to reach 10Gbps line speed.
(2) Since a HINOC2.0 compliant device is required at a HINOC3.0 device, a frame stripping module is required to support parsing of the frame format of HINOC 2.0.
(3) Since HINOC3.0 unicast frames can be transmitted on each phy channel in HINOC3.0, the framing module needs to reorder the HINOC3.0 unicast frames due to the non-uniform rates of the phy channels.
The difficulty in solving the above problems and defects is: the de-framing device needs to support a rate of 10 Gbps; the frame disassembling device needs to support various HINOC frame formats; the framing device needs to support various HINOC processes caused by errors of physical channels; the frame disassembling device needs to support the processing of various information frames; the large bit width of 128 bits brings a high complexity to the splicing of the deframing means.
The significance of solving the problems and the defects is as follows: the flow design is fully applied in the architecture design, so that the frame disassembling device supports the speed of 10 Gbps; the common and difference of various HINOC frame formats are fully considered in the architecture design, so that the complexity of code design is greatly reduced, and the frame splitting device supports various HINOC frame formats; the method has the advantages that the unicast frames of non-HINOC 3.0 are subjected to manual sequence number adding and reordering operation in the architectural design, various errors can be filtered, and the processing of various HINOC frames with errors caused by physical channels is supported.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a frame splitting control method, a system, a storage medium, a terminal and an application compatible with HINOC2.0 and 3.0 protocols.
The invention is realized in such a way that a frame splitting control method compatible with HINOC2.0 and 3.0 protocols comprises the following steps:
the framework of the reordering function is realized through two sections of flow; the first section of flow realizes polling of each phy channel, mapping from phy _ id and hm _ id to device _ id, filtering crc error frames, moving ram data in phy, and maintaining and updating artificial sequence numbers of HINOC frames without sequence numbers; the second stage of the pipeline realizes the enqueue management, overtime judgment, dequeue judgment, moving of HINOC data of ram in the middle of the pipeline to the reordering queue and transparent transmission of information frames;
the framework of the function of frame splitting is realized through two sections of flow lines; the first stage of flow realizes the analysis of a frame dismantling instruction, the moving of HINOC frame data in a reordering queue, the dequeue management of the reordering queue and the analysis of an HINOC frame header; the second stage of the pipeline realizes the processing of eif frames, the processing of new fragment heads of frame splitting, the processing of frame splitting overtime instructions, the processing of three frame splitting and splicing modes and the processing of a frame splitting mode without splicing.
Further, the reordering enqueuing and dequeuing process of the frame tearing control method compatible with the HINOC2.0 and 3.0 protocols comprises the following steps: input frame sequence number X, the position at which the HINOC frame is written to (X-S + Ph) mod (l); if the RQInfoRAM corresponding to the position is not 0, the HINOC frame is discarded; extracting frame header information and writing the frame header information into RQInfoRAM;
1) and updating Smax:
if Smax is greater than S & & X is greater than Smax, Smax is X;
if Smax > S & & X < S, Smax ═ X;
if Smax < S & & X < S & & X > Smax, Smax ═ X;
2) judging overtime, wherein the sequence number S of a head Ph frame of the queue and the current maximum frame sequence number Smax are obtained; if Smax-S > T, showing that a frame is discarded after the Ph of the current queue head 3) if not, and directly entering dequeue judgment 4);
3) discarding overtime, starting from Ph, inquiring RQInfoRAM, and finding a first empty position; continuously inquiring RQInfoRAM, finding the position of the next EMAC head fragment or the complete EMAC frame, updating the position to be a new Ph, and updating S; meanwhile, resetting the corresponding RQInfoRAM; entering dequeue judgment 4) dequeue judgment, wherein RQInfoRAM is inquired from Ph until an empty position is inquired; if an EMAC tail fragment or a complete EMAC frame appears in the query process, writing a frame splitting instruction to give the number of the HINOC frames to be dequeued; simultaneously Ph is shifted to the next position of the last EMAC tail fragment or complete frame;
4) and dequeuing, namely dequeuing and frame splitting according to the frame splitting instruction, and resetting the position of the corresponding RQInfoRAM when reading out one HINOC frame.
Further, the description of the states of the code first section of the reordering function of the frame tearing control method compatible with the HINOC2.0 and 3.0 protocols is as follows:
PRE _ INIT: initializing some information ram;
PRE _ IDLE: polling ping-pong rams of each phy;
PRE _ READ _ HINOC _ INFO: reading the first two 128 bits of the ping-pong ram of the polled phy, and mapping device _ id according to the source hm _ id in the first 128bit and the polled phy _ id;
PRE _ WAIT _ DEVICE _ ID, which is to analyze the frame information in the second 128 bits and judge whether the unicast frame is 3.0 or not, to jump to the PRE _ WRITE _ INFO state or not, and to jump to the PRE _ READ _ SERIAL _ NUMBER state or not;
PRE _ READ _ SERIAL _ NUMBER: the method is not unicast of HINOC3.0, and no serial number needs to read and update an artificially added serial number according to device;
PRE _ WRITE _ INFO: if there is no CRC error and no frame head error, the information fifo in the middle of two sections of the flow is written.
Further, the description of each state of the code second stage pipeline state machine of the reordering function of the frame disassembling control method compatible with the HINOC2.0 and 3.0 protocols is as follows:
IDLE: jumping to READ _ flag when detecting that the information fifo in the middle of the running water is not empty;
READ _ flag: reading information such as Ph, S, SMAX and the like according to the intermediate information, and jumping to a READ _ RQINFORAM;
READ _ RQINFORAM: acquiring the position of RQInfoRAM according to (X-S + Ph) mod (L), reading, AND jumping to RQINFO _ ERR if the position indicates that the corresponding queue has HINOC, otherwise jumping to a WRITE _ RQINFORAM _ AND _ XRAM state;
WRITE _ RQINFORAM _ AND _ XRAM: updating the corresponding RQINFORAM and the serial number ram;
JUDGE _ TIMEOUT: judging overtime, jumping to a TIMEOUT _ DISCARD state if overtime exists, otherwise, jumping to a JUDGE _ UNQUEUE state;
TIMEOUT _ DISCARD: obtaining information such as a READ _ RQINFORAM position to be cleared according to a rule of overtime discarding of reordering enqueuing, and jumping to a CLAR _ RQINFORAM state;
CLAR _ RQINFORAM: clearing information of a corresponding position of the READ _ RQINFORAM, and jumping to a READ _ XRAM state;
judge _ UNQUEUE: dequeuing, judging a frame writing and disassembling instruction, and jumping to a READ _ XRAM state;
READ _ XRAM: reading the sequence number of the new Ph position, and jumping to a UPDATA _ Ph _ S state;
UPDATA _ Ph _ S: updating Ph, S and SMAX information, and jumping to a WAIT state;
WAIT: waiting for the data in the phy RAM to be moved to the corresponding queue, and jumping to the READ _ AFIFO state;
READ _ AFIFO: clearing the fifo with the effective indication corresponding to the phyram, and jumping to the END state;
END: and (6) ending.
Further, the description of the states of the first section of the code of the frame tearing function of the frame tearing control method compatible with the HINOC2.0 and 3.0 protocols of the pipeline state machine is as follows:
PRE _ IDLE: in the idle state, detecting that the framing command fifo is not empty, if the ping-pong rams of the internal flow of the module are not all full, jumping to PRE _ READ _ HEAD _ AND _ RQIINFO, otherwise jumping to PRE _ PAUSE1 state;
PRE _ PAUSE 1: in the waiting state, when the ping-pong rams of the internal flow of the waiting module are not all full, jumping to a PRE _ READ _ HEAD _ AND _ RQIINFO state;
PRE _ READ _ HEAD _ AND _ RQINFO: according to the frame disassembling instruction, starting to move the HINOC frame at the corresponding position of the queue and clear the corresponding queue information;
PRE _ READ _ HEAD _ AND _ RQINFO _ REG: waiting for reading of frame data header data of the HINOC;
PRE _ PARSING: parsing a header of HINOC frame data;
PRE _ WAIT: waiting for the completion of ping-pong ram movement of the HINOC frame data from the queue to the interior of the module, if the HINOC frame is the last frame dismantling instruction, jumping to a PRE _ END state, otherwise, jumping to a PRE _ PAUSE2 state;
PRE _ PAUSE 2: in the waiting state, when the ping-pong rams of the internal flow of the waiting module are not all full, jumping to a PRE _ READ _ HEAD _ AND _ RQIINFO state;
RE _ END: finishing;
description of the various states of the second section of the code pipeline state machine for the unframing function:
IDLE: in the idle state, jumping to a CHOOSE state when detecting that the ping-pong rams in the two sections of flowing water are not both empty;
choose: determining to jump to READ _ FRAG, EIF _ FRM, FRIST _ FRM, SECOND _ FRM and PAUSE states according to the frame splitting instruction;
EIF _ FRM: reading an eif subframe corresponding to the ping-pong ram according to the information analyzed by the first-stage running water;
READ _ FRAG: reading the last head fragment;
FRIST _ FRM: reading a first Ethernet subframe corresponding to the ping-pong ram according to the information analyzed by the first-stage pipeline, and jumping to an END state if the subframe is the last subframe of the HINOC frame and the HINOC frame is the last subframe of the frame splitting instruction after the reading is finished, or jumping to a WAIT state if the subframe is the last subframe of the HINOC frame and the HINOC frame is the last subframe of the frame splitting instruction;
SECOND _ FRM, THIRD _ FRM, FURTH _ FRM, FIFTH _ FRM: these several states are similar to the FRITH _ FRM state;
WAIT: according to frame information obtained by the first-stage pipeline, determining to jump to the next subframe state or the CHOOSE state;
PAUSE: waiting for the data in the next polled ping-pong ram to be valid;
END: and (6) ending.
Further, the splicing description of the EIF field and the EMAC frame of the frame tearing control method compatible with the HINOC2.0 and 3.0 protocols includes: judging the corresponding type field according to the data read in the EIF _ FRM state, and writing the information field into the corresponding ram;
processing of a new fragment head of the defragmentation, namely splicing the tail of the fragment ram data and the first Ethernet sub-frame data of the HINOC, wherein the key point is the judgment of sop in the loclink;
processing of a time-out frame splitting instruction: after the last timeout, if the first HINOC frame is tail fragment or middle fragment, discarding is needed, and the key point is that if the first HINOC frame only has middle fragment, the next HINOC frame is to continue judging;
processing of three frame splitting and splicing modes: splicing the head fragments with tail fragments in the HINOC frame, wherein the tail fragments are all at the head 128 of the HINOC frame; splicing the head fragments with tail fragments in the HINOC frame, wherein the tail fragments are not all at the head 128 of the HINOC frame, and the data during first splicing is more than or equal to 128 bits; splicing the head fragments with tail fragments in the HINOC frame, wherein the tail fragments are not all at the head 128 of the HINOC frame, and data is less than 128 bits during first splicing;
processing of the split frame mode without splicing: and judging whether one Ethernet subframe in the HINOC frame is a complete Ethernet frame or not according to the first-stage pipelining information, and if so, directly outputting the frame.
It is another object of the present invention to provide a computer-readable storage medium storing a computer program which, when executed by a processor, causes the processor to perform the steps of:
the framework of the reordering function is realized through two sections of flow; the first section of flow realizes polling of each phy channel, mapping from phy _ id and hm _ id to device _ id, filtering crc error frames, moving ram data in phy, and maintaining and updating artificial sequence numbers of HINOC frames without sequence numbers; the second stage of the pipeline realizes the enqueue management, overtime judgment, dequeue judgment, moving of HINOC data of ram in the middle of the pipeline to the reordering queue and transparent transmission of information frames;
the framework of the function of frame splitting is realized through two sections of flow lines; the first stage of flow realizes the analysis of a frame dismantling instruction, the moving of HINOC frame data in a reordering queue, the dequeue management of the reordering queue and the analysis of an HINOC frame header; the second stage of the pipeline realizes the processing of eif frames, the processing of new fragment heads of frame splitting, the processing of frame splitting overtime instructions, the processing of three frame splitting and splicing modes and the processing of a frame splitting mode without splicing.
Another object of the present invention is to provide an information data processing terminal, which is configured to implement the method for controlling frame tearing compatible with the HINOC2.0 and 3.0 protocols.
Another object of the present invention is to provide a HINOC2.0 and 3.0 protocol-compatible frame tearing control system implementing the HINOC2.0 and 3.0 protocol-compatible frame tearing control method, the HINOC2.0 and 3.0 protocol-compatible frame tearing control system comprising:
the reordering function module is used for realizing polling of each phy channel, mapping of phy _ id and hm _ id to device _ id, filtering of crc error frames, moving ram data in phy, maintaining and updating artificial sequence numbers of HINOC frames without sequence numbers, performing enqueue management of reordering queues, performing overtime judgment and dequeue judgment, moving HINOC data of ram in the middle of pipelining to reordering queues and transparently transmitting information frames by adopting two sections of pipelining;
and the frame disassembling functional module is used for realizing the analysis of a frame disassembling instruction, the moving of HINOC frame data in a reordering queue, the dequeuing management of the reordering queue, the analysis of HINOC frame headers, the processing of eif frames, the processing of new fragment headers of disassembled frames, the processing of overtime frame disassembling instructions, the processing of three frame disassembling and splicing modes and the processing of a frame disassembling mode without splicing by adopting two sections of flow lines.
The invention also aims to provide a method for realizing the frame splitting technology of the MAC layer in the HINOC3.0 system, and the method for realizing the frame splitting technology of the MAC layer in the HINOC3.0 system is used for realizing the HINOC frame splitting control method.
By combining all the technical schemes, the invention has the advantages and positive effects that: the architecture of the reordering function of the present invention is implemented by two segments of flow water; the first section of the pipeline realizes polling of each phy channel, mapping of phy _ id and hm _ id to device _ id, filtering of crc error frames, moving of ram data in phy, and maintenance and updating of artificial sequence numbers of HINOC frames without sequence numbers. The second stage of the pipeline realizes the enqueue management of the reordering queue, the timeout judgment, the dequeue judgment, the moving of the HINOC data of the middle ram of the pipeline to the reordering queue and the transparent transmission of the information frame (the transparent transmission refers to the information frame as the middle fragment). The frame splitting function is also implemented architecturally through two stages of pipelining. The first stage of the pipeline realizes the analysis of a frame splitting instruction, the moving of HINOC frame data in a reordering queue, the dequeuing management of the reordering queue and the analysis of HINOC frame headers. The second section of the pipeline realizes the processing of eif frames, the processing of new fragment heads of frame splitting, the processing of frame splitting overtime instructions, the processing of three frame splitting and splicing modes and the processing of a frame splitting mode without splicing.
The invention realizes the framework of the function of frame splitting through two sections of flow lines. The invention supports the speed of 10Gbps, and fully utilizes the streamlined design in the architecture design; various HINOC frame formats are supported, and the commonalities and differences of the various HINOC frame formats are fully considered in the architecture design so as to reduce the complexity of code design; the method supports the processing of various HINOC frames with errors caused by physical channels, and the unique sequence number of the unicast frame of non-HINOC 3.0 is added artificially in the architectural design to carry out reordering operation so as to filter out various errors; the processing of various information frames is supported, the information frames are transparently transmitted in the reordering, and the information frames are reordered as intermediate fragments; and the complexity of splicing of the frame splitting device caused by large bit width is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained from the drawings without creative efforts.
Fig. 1 is a flowchart of a framing control method compatible with HINOC2.0 and 3.0 protocols according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a framing control system compatible with HINOC2.0 and 3.0 protocols according to an embodiment of the present invention;
in fig. 2: 1. a reordering function module; 2. and a frame disassembling function module.
Fig. 3 is a frame format of a compatible HINOC2.0 defined in the HINOC3.0 protocol provided by an embodiment of the present invention.
Fig. 4 is a diagram of placement and definition of meaning of the special fields required separately in the HINOC3.0 frame format provided by an embodiment of the present invention.
Fig. 5 is a diagram of some field definitions and unique field descriptions for different versions and types of HINOC frames provided by embodiments of the present invention.
Fig. 6 is a schematic diagram of a frame disassembling apparatus according to an embodiment of the present invention.
FIG. 7 is a waveform illustrating simulation of a reordered dequeue decision provided by an embodiment of the present invention.
Fig. 8 is a waveform diagram illustrating simulation of timeout clearing for reordering provided by an embodiment of the present invention.
Fig. 9 is an EMAC frame simulation waveform diagram in the locallink format obtained after the frame is removed according to the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In view of the problems in the prior art, the present invention provides a method, a system, a storage medium, a terminal and an application for controlling frame tearing compatible with HINOC2.0 and 3.0 protocols, and the present invention is described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the method for controlling frame tearing in compliance with HINOC2.0 and 3.0 protocols provided by the present invention includes the following steps:
s101: the structure of the reordering function is realized by two sections of running water; the first section of the pipeline realizes polling of each phy channel, mapping from phy _ id and hm _ id to device _ id, filtering of crc error frames, moving ram data in phy, and maintaining and updating artificial sequence numbers of HINOC frames without sequence numbers; the second stage of the pipeline realizes the enqueue management of the reordering queue, the timeout judgment, the dequeue judgment, the moving of the HINOC data of the middle ram of the pipeline to the reordering queue and the transparent transmission of the information frame (the transparent transmission refers to the information frame as the middle fragment).
S102: the frame splitting function is realized by two sections of flow; the first stage of the pipeline realizes the analysis of a frame dismantling instruction, the moving of HINOC frame data in a reordering queue, the dequeue management of the reordering queue and the analysis of an HINOC frame header; the second section of the pipeline realizes the processing of eif frames, the processing of new fragment heads of frame splitting, the processing of frame splitting overtime instructions, the processing of three frame splitting and splicing modes and the processing of a frame splitting mode without splicing.
The HINOC2.0 and 3.0 protocol compatible frame tearing control method provided by the present invention may also be implemented by other steps, and the HINOC2.0 and 3.0 protocol compatible frame tearing control method provided by the present invention in fig. 1 is only a specific embodiment.
As shown in fig. 2, the system for controlling frame tearing compatible with HINOC2.0 and 3.0 protocols provided by the present invention includes:
the reordering function module 1 is used for implementing polling of each phy channel, mapping of phy _ id and hm _ id to device _ id, filtering of crc error frames, moving ram data in phy, maintaining and updating artificial sequence numbers of HINOC frames without sequence numbers, performing enqueue management of reordering queues, performing timeout judgment, determining dequeue, moving HINOC data of ram in the middle of pipelining to reordering queues, and transparently transmitting information frames by adopting two sections of pipelining.
And the frame disassembling functional module 2 is used for realizing the analysis of a frame disassembling instruction, the moving of HINOC frame data in a reordering queue, the dequeuing management of the reordering queue, the analysis of HINOC frame headers, the processing of eif frames, the processing of new fragment headers of disassembled frames, the processing of overtime frame disassembling instructions, the processing of three frame disassembling and splicing modes and the processing of a frame disassembling mode without splicing by adopting two sections of flow lines.
The technical solution of the present invention is further described below with reference to the accompanying drawings.
The frame-splitting control method compatible with the HINOC2.0 and 3.0 protocols provided by the invention realizes the structure of the reordering function through two sections of flow water. The first section of the pipeline realizes polling of each phy channel, mapping of phy _ id and hm _ id to device _ id, filtering of crc error frames, moving of ram data in phy, and maintenance and updating of artificial sequence numbers of HINOC frames without sequence numbers. The second stage of the pipeline realizes the enqueue management, overtime judgment, dequeue judgment, the moving of HINOC data of ram in the middle of the pipeline to the reordering queue and the 'transparent transmission' of information frames.
Description of some nouns in the reordering enqueue dequeue flow:
sequencing queue rq (ranking queue): and setting the length L of each queue, addressing the range of each queue to be 0-L-1, and circularly and sequentially storing the addresses (address pointers) of the received HINOC frame stored in the DDR. L is configurable in size, maximum 128.
HINOC frame number: each priority queue of the HINOC3.0 unicast frame has an independent sequence number, the circulation counting is carried out, each time of queuing is carried out, the expected HINOC frame minimum sequence number S is obtained, and the currently received HINOC frame sequence number is X; for determining an offset location stored in the RQ queue; the maximum value Smax of the HINOC frame number has been entered.
A queue threshold T: t < L, when the sequence number X of the incoming frame minus the sequence number S of the head of the queue exceeds the threshold T, judging that the prior HINOC frame is lost, and storing the new incoming frame after a certain space is overtime; L-T > 8.
RQ queue info table RQInfoRAM: whether an HINOC frame exists in 0-L-1 addresses used for storing an RQ queue, whether the HINOC frame comprises an EMAC head, an EMAC tail, an EMAC middle and complete EMAC frame and the like, and the ratio of a pointer Ph: the head node is used for indicating the position of the first fragmented ethernet frame in the sequencing queue RQ; the frame number S pointed to.
And (3) reordering enqueuing and dequeuing processes:
input frame sequence number X, the position at which the HINOC frame is written to (X-S + Ph) mod (l); if the RQInfoRAM corresponding to the position is not 0, the HINOC frame is discarded; and extracting frame header information and writing the frame header information into RQInfoRAM.
1) And updating Smax:
if Smax is greater than S & & X is greater than Smax, Smax is X;
if Smax > S & & X < S, Smax ═ X;
if Smax < S & & X < S & & X > Smax, Smax ═ X.
2) Judging overtime, wherein the sequence number S of a head Ph frame of the queue and the current maximum frame sequence number Smax are obtained; if Smax-S > T, it shows that there is a frame overtime to discard 3) after the current queue head Ph, otherwise, it directly enters dequeue judgment 4).
3) Discarding overtime, starting from Ph, inquiring RQInfoRAM, and finding a first empty position; continuously inquiring RQInfoRAM, finding the position of the next EMAC head fragment or the complete EMAC frame, updating the position to be a new Ph, and updating S; meanwhile, resetting the corresponding RQInfoRAM; entering dequeue judgment 4) dequeue judgment, wherein RQInfoRAM is inquired from Ph until an empty position is inquired; if an EMAC tail fragment or a complete EMAC frame appears in the query process, writing a frame splitting instruction to give the number of the HINOC frames to be dequeued; and Ph is shifted to the next position of the last EMAC tail slice or complete frame.
4) And dequeuing, namely dequeuing and frame splitting according to the frame splitting instruction, and resetting the position of the corresponding RQInfoRAM when reading out one HINOC frame.
The first section of code of the reordering function is the specification of each state of the pipeline state machine:
PRE _ INIT: some information ram is initialized.
PRE _ IDLE: and polling ping-pong rams of each phy.
PRE _ READ _ HINOC _ INFO: and reading the first two 128 bits of the ping-pong ram of the polled phy, and mapping the device _ id according to the source hm _ id in the first 128bit and the polled phy _ id.
PRE _ WAIT _ DEVICE _ ID, which resolves the frame information in the second 128 bits and judges if the unicast frame is 3.0, it jumps to PRE _ WRITE _ INFO state, if it jumps to PRE _ READ _ SERIAL _ NUMBER state.
PRE _ READ _ SERIAL _ NUMBER: not unicast with HINOC3.0, no sequence number needs to be read and updated according to device.
PRE _ WRITE _ INFO: if there is no CRC error and no frame head error, the information fifo in the middle of two sections of the flow is written.
The description of each state of the second section of code pipeline state machine of the reordering function:
IDLE: and jumping to the READ _ flag when detecting that the information fifo in the middle of the running water is not empty.
READ _ flag: and reading information such as Ph, S, SMAX and the like according to the intermediate information, and jumping to the READ _ RQINFORAM.
READ _ RQINFORAM: AND acquiring the position of the RQInfoRAM according to (X-S + Ph) mod (L), reading, AND jumping to RQINFO _ ERR if the position indicates that the corresponding queue has HINOC, otherwise jumping to a WRITE _ RQINFORAM _ AND _ XRAM state.
WRITE _ RQINFORAM _ AND _ XRAM: the corresponding RQINFORAM and sequence ram are updated.
JUDGE _ TIMEOUT: and judging the TIMEOUT, jumping to a TIMEOUT _ DISCARD state when the TIMEOUT is judged, and otherwise, jumping to a JUDGE _ UNQUEUE state.
TIMEOUT _ DISCARD: and obtaining information such as the position of the READ _ RQINFORAM to be cleared according to a rule of overtime discarding of reordering enqueuing, and jumping to a CLAR _ RQINFORAM state.
CLAR _ RQINFORAM: clearing the information of the corresponding position of the READ _ RQINFORAM and jumping to the READ _ XRAM state.
Judge _ UNQUEUE: and dequeuing to judge the frame writing and splitting instruction and jumping to a READ _ XRAM state.
READ _ XRAM: the sequence number of the new Ph location is read and the transition is made to the UPDATA _ Ph _ S state.
UPDATA _ Ph _ S: and updating information such as Ph, S, SMAX and the like, and jumping to a WAIT state.
WAIT: and waiting for the data in the phy RAM to be moved to the corresponding queue, and jumping to the READ _ AFIFO state.
READ _ AFIFO: clearing the fifo with the effective indication corresponding to the phyram, and jumping to the END state.
END: and (6) ending.
The frame splitting function of the frame splitting control method compatible with the HINOC2.0 and 3.0 protocols is realized by two sections of flow water. The first stage of the pipeline realizes the analysis of a frame splitting instruction, the moving of HINOC frame data in a reordering queue, the dequeuing management of the reordering queue and the analysis of HINOC frame headers. The second segment of the pipeline realizes the processing of eif frames, the processing of new fragment heads of frame splitting, the processing of frame splitting overtime instructions, the processing of four frame splitting and splicing modes and the processing of a frame splitting mode without splicing.
Description of the various states of the first section of the code pipeline state machine of the deframing function:
PRE _ IDLE: AND in an idle state, detecting that the framing command fifo is not empty, AND if the ping-pong rams of the internal pipelines of the modules are not all full, jumping to PRE _ READ _ HEAD _ AND _ RQIINFO, AND otherwise, jumping to PRE _ PAUSE1 state.
PRE _ PAUSE 1: AND in a waiting state, jumping to a PRE _ READ _ HEAD _ AND _ RQIINFO state when the ping-pong rams of the internal flow of the waiting module are not all full.
PRE _ READ _ HEAD _ AND _ RQINFO: and starting to move the HINOC frame at the corresponding position of the queue and clear the corresponding queue information according to the frame disassembling instruction.
PRE _ READ _ HEAD _ AND _ RQINFO _ REG: waiting for reading of the header data of the HINOC frame data.
PRE _ PARSING: the header of the HINOC frame data is parsed.
PRE _ WAIT: waiting for the completion of the ping-pong ram movement of the HINOC frame data from the queue to the interior of the module, if the HINOC frame is the last frame-tearing instruction, jumping to the PRE _ END state, otherwise, jumping to the PRE _ PAUSE2 state.
PRE _ PAUSE 2: AND in a waiting state, jumping to a PRE _ READ _ HEAD _ AND _ RQIINFO state when the ping-pong rams of the internal flow of the waiting module are not all full.
RE _ END: and (6) ending.
Description of the various states of the second section of the code pipeline state machine for the unframing function:
IDLE: and in an idle state, jumping to a CHOOSE state when detecting that the ping-pong rams in the two sections of streaming water are not all empty.
Choose: and deciding to jump to the states of READ _ FRAG, EIF _ FRM, FRIST _ FRM, SECOND _ FRM and PAUSE according to the frame splitting instruction.
EIF _ FRM: reading an eif subframe corresponding to the ping-pong ram according to the information analyzed by the first-stage running water.
READ _ FRAG: the last head fragment is read.
FRIST _ FRM: and reading a first Ethernet subframe corresponding to the ping-pong ram according to the information analyzed by the first-stage pipeline, and jumping to an END state if the subframe is the last subframe of the HINOC frame and the HINOC frame is the last subframe of the frame splitting instruction after the reading is finished, or jumping to a WAIT state if the subframe is the last subframe of the HINOC frame and the HINOC frame is the last subframe of the frame splitting instruction.
SECOND _ FRM, THIRD _ FRM, FURTH _ FRM, FIFTH _ FRM: these several states are similar to the FRITH _ FRM state.
WAIT: and according to the frame information obtained by the first-stage pipeline, determining to jump to the next subframe state or the Choose state.
PAUSE: and waiting for the data in the next polled ping-pong ram to be valid.
END: and (6) ending.
Splicing description of EIF field and EMAC frame:
and judging the corresponding type field according to the data read by the EIF _ FRM state, and writing the information field into the corresponding ram.
And (3) framing the new fragment head, namely splicing the tail part of the fragment ram data and the first Ethernet sub-frame data of the HINOC, wherein the key point is the judgment of sop in the loclink.
Processing of a time-out frame splitting instruction: it is referred to that after the last timeout, if the first HINOC frame is tail fragment or middle fragment, it needs to be discarded, and the key point is that if the first HINOC frame only has middle fragment, the next HINOC frame will continue to judge.
Processing of three frame splitting and splicing modes: splicing the head fragments with tail fragments in the HINOC frame, wherein the tail fragments are all at the head 128 of the HINOC frame; splicing the head fragments with tail fragments in the HINOC frame, wherein the tail fragments are not all at the head 128 of the HINOC frame, and the data during first splicing is more than or equal to 128 bits; and splicing the head fragments with tail fragments in the HINOC frame, wherein the tail fragments are not all at the head 128 of the HINOC frame, and the data is less than 128 bits when the tail fragments are spliced for the first time.
Processing of the split frame mode without splicing: and judging whether one Ethernet subframe in the HINOC frame is a complete Ethernet frame or not according to the first-stage pipelining information, and if so, directly outputting the frame.
In order to support the speed of 10Gbps, the invention fully utilizes the streamlined design in the architecture design; in order to support multiple HINOC frame formats, the commonality and difference of the various HINOC frame formats are fully considered in the architecture design so as to reduce the complexity of code design; in order to support various HINOC treatments which cause errors by physical channels, the construction design originally carries out reordering operation on unicast frames of non-HINOC 3.0 by artificially adding sequence numbers, thus not only filtering out various errors such as CRC errors and fragmentation errors; in order to support the processing of various frames of information, the frames of information are "transparently transported" in the reordering, taking the frames of information into the reordering as an intermediate fragment. In order to reduce the large bit width, high complexity is brought to the splicing of the frame splitting device, and several conditions encountered by the splicing are comprehensively analyzed and summarized.
It should be noted that the embodiments of the present invention can be realized by hardware, software, or a combination of software and hardware. The hardware portion may be implemented using dedicated logic; the software portions may be stored in a memory and executed by a suitable instruction execution system, such as a microprocessor or specially designed hardware. Those skilled in the art will appreciate that the apparatus and methods described above may be implemented using computer executable instructions and/or embodied in processor control code, such code being provided on a carrier medium such as a disk, CD-or DVD-ROM, programmable memory such as read only memory (firmware), or a data carrier such as an optical or electronic signal carrier, for example. The apparatus and its modules of the present invention may be implemented by hardware circuits such as very large scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., or by software executed by various types of processors, or by a combination of hardware circuits and software, e.g., firmware.
The above description is only for the purpose of illustrating the present invention and the appended claims are not to be construed as limiting the scope of the invention, which is intended to cover all modifications, equivalents and improvements that are within the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A frame splitting control method compatible with HINOC2.0 and 3.0 protocols is characterized by comprising the following steps:
the framework of the reordering function is realized through two sections of flow; the first section of flow realizes polling of each phy channel, mapping from phy _ id and hm _ id to device _ id, filtering of crc error frames and empty frames, moving ram data in phy, and maintaining and updating artificial sequence numbers of HINOC frames without sequence numbers; the second stage of the pipeline realizes the enqueue management, overtime judgment, dequeue judgment, moving of HINOC data of ram in the middle of the pipeline to the reordering queue and transparent transmission of information frames;
the framework of the function of frame splitting is realized through two sections of flow lines; the first stage of flow realizes the analysis of a frame dismantling instruction, the moving of HINOC frame data in a reordering queue, the dequeue management of the reordering queue and the analysis of an HINOC frame header; the second stage of the pipeline realizes the processing of eif frames, the processing of new fragment heads of frame splitting, the processing of frame splitting overtime instructions, the processing of three frame splitting and splicing modes and the processing of a frame splitting mode without splicing.
2. The HINOC2.0 and 3.0 protocol-compatible frame tearing-down control method of claim 1, wherein the reordering enqueue and dequeue flow of the HINOC2.0 and 3.0 protocol-compatible frame tearing-down control method comprises the following steps: input frame sequence number X, the position at which the HINOC frame is written to (X-S + Ph) mod (l); if the RQInfoRAM corresponding to the position is not 0, the HINOC frame is discarded; extracting frame header information and writing the frame header information into RQInfoRAM;
1) and updating Smax:
if Smax is greater than S & & X is greater than Smax, Smax is X;
if Smax > S & & X < S, Smax ═ X;
if Smax < S & & X < S & & X > Smax, Smax ═ X;
2) judging overtime, wherein the sequence number S of a head Ph frame of the queue and the current maximum frame sequence number Smax are obtained; if Smax-S > T, showing that a frame is discarded after the Ph of the current queue head 3) if not, and directly entering dequeue judgment 4);
3) discarding overtime, starting from Ph, inquiring RQInfoRAM, and finding a first empty position; continuously inquiring RQInfoRAM, finding the position of the next EMAC head fragment or the complete EMAC frame, updating the position to be a new Ph, and updating S; meanwhile, resetting the corresponding RQInfoRAM; entering dequeue judgment 4) dequeue judgment, wherein RQInfoRAM is inquired from Ph until an empty position is inquired; if an EMAC tail fragment or a complete EMAC frame appears in the query process, writing a frame splitting instruction to give the number of the HINOC frames to be dequeued; simultaneously Ph is shifted to the next position of the last EMAC tail fragment or complete frame;
4) and dequeuing, namely dequeuing and frame splitting according to the frame splitting instruction, and resetting the position of the corresponding RQInfoRAM when reading out one HINOC frame.
3. The HINOC2.0 and 3.0 protocol-compatible frame tearing control method of claim 1, wherein a first section of code of the reordering function of the HINOC2.0 and 3.0 protocol-compatible frame tearing control method is used for describing the states of a pipeline state machine:
PRE _ INIT: initializing some information ram;
PRE _ IDLE: polling ping-pong rams of each phy;
PRE _ READ _ HINOC _ INFO: reading the first two 128 bits of the ping-pong ram of the polled phy, and mapping device _ id according to the source hm _ id in the first 128bit and the polled phy _ id;
PRE _ WAIT _ DEVICE _ ID, which is to analyze the frame information in the second 128 bits and judge whether the unicast frame is 3.0 or not, to jump to the PRE _ WRITE _ INFO state or not, and to jump to the PRE _ READ _ SERIAL _ NUMBER state or not;
PRE _ READ _ SERIAL _ NUMBER: the method is not unicast of HINOC3.0, and no serial number needs to read and update an artificially added serial number according to device;
PRE _ WRITE _ INFO: if there is no CRC error and no frame head error, the information fifo in the middle of two sections of the flow is written.
4. The HINOC2.0 and 3.0 protocol-compatible frame tearing control method of claim 1, wherein the HINOC2.0 and 3.0 protocol-compatible frame tearing control method comprises a description of the states of a code second stage pipeline state machine of a reordering function of the HINOC2.0 and 3.0 protocol-compatible frame tearing control method:
IDLE: jumping to READ _ flag when detecting that the information fifo in the middle of the running water is not empty;
READ _ flag: reading information such as Ph, S, SMAX and the like according to the intermediate information, and jumping to a READ _ RQINFORAM;
READ _ RQINFORAM: acquiring the position of RQInfoRAM according to (X-S + Ph) mod (L), reading, AND jumping to RQINFO _ ERR if the position indicates that the corresponding queue has HINOC, otherwise jumping to a WRITE _ RQINFORAM _ AND _ XRAM state;
WRITE _ RQINFORAM _ AND _ XRAM: updating the corresponding RQINFORAM and the serial number ram;
JUDGE _ TIMEOUT: judging overtime, jumping to a TIMEOUT _ DISCARD state if overtime exists, otherwise, jumping to a JUDGE _ UNQUEUE state;
TIMEOUT _ DISCARD: obtaining information such as a READ _ RQINFORAM position to be cleared according to a rule of overtime discarding of reordering enqueuing, and jumping to a CLAR _ RQINFORAM state;
CLAR _ RQINFORAM: clearing information of a corresponding position of the READ _ RQINFORAM, and jumping to a READ _ XRAM state;
judge _ UNQUEUE: dequeuing, judging a frame writing and disassembling instruction, and jumping to a READ _ XRAM state;
READ _ XRAM: reading the sequence number of the new Ph position, and jumping to a UPDATA _ Ph _ S state;
UPDATA _ Ph _ S: updating Ph, S and SMAX information, and jumping to a WAIT state;
WAIT: waiting for the data in the phy RAM to be moved to the corresponding queue, and jumping to the READ _ AFIFO state;
READ _ AFIFO: clearing the fifo with the effective indication corresponding to the phyram, and jumping to the END state;
END: and (6) ending.
5. The HINOC2.0 and 3.0 protocol-compatible frame tearing control method of claim 1, wherein the first section of code for the frame tearing function of the HINOC2.0 and 3.0 protocol-compatible frame tearing control method is used for describing the states of a pipeline state machine:
PRE _ IDLE: in the idle state, detecting that the framing command fifo is not empty, if the ping-pong rams of the internal flow of the module are not all full, jumping to PRE _ READ _ HEAD _ AND _ RQIINFO, otherwise jumping to PRE _ PAUSE1 state;
PRE _ PAUSE 1: in the waiting state, when the ping-pong rams of the internal flow of the waiting module are not all full, jumping to a PRE _ READ _ HEAD _ AND _ RQIINFO state;
PRE _ READ _ HEAD _ AND _ RQINFO: according to the frame disassembling instruction, starting to move the HINOC frame at the corresponding position of the queue and clear the corresponding queue information;
PRE _ READ _ HEAD _ AND _ RQINFO _ REG: waiting for reading of frame data header data of the HINOC;
PRE _ PARSING: parsing a header of HINOC frame data;
PRE _ WAIT: waiting for the completion of ping-pong ram movement of the HINOC frame data from the queue to the interior of the module, if the HINOC frame is the last frame dismantling instruction, jumping to a PRE _ END state, otherwise, jumping to a PRE _ PAUSE2 state;
PRE _ PAUSE 2: in the waiting state, when the ping-pong rams of the internal flow of the waiting module are not all full, jumping to a PRE _ READ _ HEAD _ AND _ RQIINFO state;
RE _ END: finishing;
description of the various states of the second section of the code pipeline state machine for the unframing function:
IDLE: in the idle state, jumping to a CHOOSE state when detecting that the ping-pong rams in the two sections of flowing water are not both empty;
choose: determining to jump to READ _ FRAG, EIF _ FRM, FRIST _ FRM, SECOND _ FRM and PAUSE states according to the frame splitting instruction;
EIF _ FRM: reading an eif subframe corresponding to the ping-pong ram according to the information analyzed by the first-stage running water;
READ _ FRAG: reading the last head fragment;
FRIST _ FRM: reading a first Ethernet subframe corresponding to the ping-pong ram according to the information analyzed by the first-stage pipeline, and jumping to an END state if the subframe is the last subframe of the HINOC frame and the HINOC frame is the last subframe of the frame splitting instruction after the reading is finished, or jumping to a WAIT state if the subframe is the last subframe of the HINOC frame and the HINOC frame is the last subframe of the frame splitting instruction;
SECOND _ FRM, THIRD _ FRM, FURTH _ FRM, FIFTH _ FRM: these several states are similar to the FRITH _ FRM state;
WAIT: according to frame information obtained by the first-stage pipeline, determining to jump to the next subframe state or the CHOOSE state;
PAUSE: waiting for the data in the next polled ping-pong ram to be valid;
END: and (6) ending.
6. The method for controlling frame tearing of compatible HINOC2.0 and 3.0 protocols according to claim 1, wherein the EIF field and the splicing specification of the EMAC frame of the frame tearing control method of compatible HINOC2.0 and 3.0 protocols are as follows: judging the corresponding type field according to the data read in the EIF _ FRM state, and writing the information field into the corresponding ram;
processing of a new fragment head of the defragmentation, namely splicing the tail of the fragment ram data and the first Ethernet sub-frame data of the HINOC, wherein the key point is the judgment of sop in the loclink;
processing of a time-out frame splitting instruction: after the last timeout, if the first HINOC frame is tail fragment or middle fragment, discarding is needed, and the key point is that if the first HINOC frame only has middle fragment, the next HINOC frame is to continue judging;
processing of three frame splitting and splicing modes: splicing the head fragments with tail fragments in the HINOC frame, wherein the tail fragments are all at the head 128 of the HINOC frame; splicing the head fragments with tail fragments in the HINOC frame, wherein the tail fragments are not all at the head 128 of the HINOC frame, and the data during first splicing is more than or equal to 128 bits; splicing the head fragments with tail fragments in the HINOC frame, wherein the tail fragments are not all at the head 128 of the HINOC frame, and data is less than 128 bits during first splicing;
processing of the split frame mode without splicing: and judging whether one Ethernet subframe in the HINOC frame is a complete Ethernet frame or not according to the first-stage pipelining information, and if so, directly outputting the frame.
7. A computer-readable storage medium storing a computer program which, when executed by a processor, causes the processor to perform the steps of:
the framework of the reordering function is realized through two sections of flow; the first section of flow realizes polling of each phy channel, mapping from phy _ id and hm _ id to device _ id, filtering crc error frames, moving ram data in phy, and maintaining and updating artificial sequence numbers of HINOC frames without sequence numbers; the second stage of the pipeline realizes the enqueue management, overtime judgment, dequeue judgment, moving of HINOC data of ram in the middle of the pipeline to the reordering queue and transparent transmission of information frames;
the framework of the function of frame splitting is realized through two sections of flow lines; the first stage of flow realizes the analysis of a frame dismantling instruction, the moving of HINOC frame data in a reordering queue, the dequeue management of the reordering queue and the analysis of an HINOC frame header; the second stage of the pipeline realizes the processing of eif frames, the processing of new fragment heads of frame splitting, the processing of frame splitting overtime instructions, the processing of three frame splitting and splicing modes and the processing of a frame splitting mode without splicing.
8. An information data processing terminal, wherein the information data processing terminal is configured to implement the method for controlling frame tearing compatible with the HINOC2.0 and 3.0 protocols as claimed in any one of claims 1 to 6.
9. An HINOC2.0 and 3.0 protocol-compatible frame splitting control system for implementing the HINOC2.0 and 3.0 protocol-compatible frame splitting control method as claimed in any one of claims 1 to 6, wherein the HINOC2.0 and 3.0 protocol-compatible frame splitting control system comprises:
the reordering function module is used for realizing polling of each phy channel, mapping of phy _ id and hm _ id to device _ id, filtering of crc error frames, moving ram data in phy, maintaining and updating artificial sequence numbers of HINOC frames without sequence numbers, performing enqueue management of reordering queues, performing overtime judgment and dequeue judgment, moving HINOC data of ram in the middle of pipelining to reordering queues and transparently transmitting information frames by adopting two sections of pipelining;
and the frame disassembling functional module is used for realizing the analysis of a frame disassembling instruction, the moving of HINOC frame data in a reordering queue, the dequeuing management of the reordering queue, the analysis of HINOC frame headers, the processing of eif frames, the processing of new fragment headers of disassembled frames, the processing of overtime frame disassembling instructions, the processing of three frame disassembling and splicing modes and the processing of a frame disassembling mode without splicing by adopting two sections of flow lines.
10. An implementation method of a frame splitting technology of a MAC layer in an HINOC3.0 system is characterized in that the implementation method of the frame splitting technology of the MAC layer in the HINOC3.0 system is used for implementing the frame splitting control method compatible with HINOC2.0 and 3.0 protocols, and the frame splitting control method is as claimed in any one of claims 1 to 6.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114401072A (en) * | 2021-12-12 | 2022-04-26 | 西安电子科技大学 | Dynamic cache control method and system for frame splitting and reordering queue based on HINOC protocol |
| CN114465696A (en) * | 2022-04-12 | 2022-05-10 | 井芯微电子技术(天津)有限公司 | State machine verification method and system based on state transition mode |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103220231A (en) * | 2012-01-19 | 2013-07-24 | 上海未来宽带技术股份有限公司 | HiNOC data flow processing system and method |
| US20160006580A1 (en) * | 2014-07-01 | 2016-01-07 | Netronome Systems, Inc. | Reordering pcp flows as they are assigned to virtual channels |
| US20160006677A1 (en) * | 2014-07-01 | 2016-01-07 | Netronome Systems, Inc. | Inverse pcp flow remapping for pfc pause frame generation |
| US20160173396A1 (en) * | 2013-07-30 | 2016-06-16 | Entropic Communications, Llc | Method and apparatus for combined access network and home network using a dual-role device |
| CN108462642A (en) * | 2018-03-16 | 2018-08-28 | 西安电子科技大学 | UDP/IP hardware protocol stacks based on FPGA and implementation method |
| CN110290074A (en) * | 2019-07-01 | 2019-09-27 | 西安电子科技大学 | The Crossbar crosspoint design method interconnected between FPGA piece |
| CN111010253A (en) * | 2019-11-06 | 2020-04-14 | 西安电子科技大学 | HIMAC frame splitting system and method based on HINOC protocol |
| CN111614527A (en) * | 2020-04-26 | 2020-09-01 | 北京瀚诺半导体科技有限公司 | Method and device for on-line of HINOC terminal, storage medium and terminal |
| CN111614526A (en) * | 2020-04-20 | 2020-09-01 | 北京瀚诺半导体科技有限公司 | Method, device, storage medium and terminal for rapidly maintaining HINOC link |
| CN111669262A (en) * | 2020-05-11 | 2020-09-15 | 北京瀚诺半导体科技有限公司 | Data transmission method and device, electronic equipment and medium |
| CN112084136A (en) * | 2020-07-23 | 2020-12-15 | 西安电子科技大学 | Queue cache management method, system, storage medium, computer device and application |
-
2021
- 2021-01-26 CN CN202110114965.3A patent/CN112953860B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103220231A (en) * | 2012-01-19 | 2013-07-24 | 上海未来宽带技术股份有限公司 | HiNOC data flow processing system and method |
| US20160173396A1 (en) * | 2013-07-30 | 2016-06-16 | Entropic Communications, Llc | Method and apparatus for combined access network and home network using a dual-role device |
| US20160006580A1 (en) * | 2014-07-01 | 2016-01-07 | Netronome Systems, Inc. | Reordering pcp flows as they are assigned to virtual channels |
| US20160006677A1 (en) * | 2014-07-01 | 2016-01-07 | Netronome Systems, Inc. | Inverse pcp flow remapping for pfc pause frame generation |
| CN108462642A (en) * | 2018-03-16 | 2018-08-28 | 西安电子科技大学 | UDP/IP hardware protocol stacks based on FPGA and implementation method |
| CN110290074A (en) * | 2019-07-01 | 2019-09-27 | 西安电子科技大学 | The Crossbar crosspoint design method interconnected between FPGA piece |
| CN111010253A (en) * | 2019-11-06 | 2020-04-14 | 西安电子科技大学 | HIMAC frame splitting system and method based on HINOC protocol |
| CN111614526A (en) * | 2020-04-20 | 2020-09-01 | 北京瀚诺半导体科技有限公司 | Method, device, storage medium and terminal for rapidly maintaining HINOC link |
| CN111614527A (en) * | 2020-04-26 | 2020-09-01 | 北京瀚诺半导体科技有限公司 | Method and device for on-line of HINOC terminal, storage medium and terminal |
| CN111669262A (en) * | 2020-05-11 | 2020-09-15 | 北京瀚诺半导体科技有限公司 | Data transmission method and device, electronic equipment and medium |
| CN112084136A (en) * | 2020-07-23 | 2020-12-15 | 西安电子科技大学 | Queue cache management method, system, storage medium, computer device and application |
Non-Patent Citations (6)
| Title |
|---|
| DENG CHEN ET AL: "The design of HIMAC coprocessor based on HINOC 2.0", 《2014 12TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING (ICSP)》 * |
| 欧阳峰等: "基于UVM的HIMAC验证平台的设计", 《电视技术》 * |
| 潘伟涛等: "HINOC系统MAC协处理器的设计与测试", 《网络新媒体技术》 * |
| 潘伟涛等: "一种HIMAC硬件协处理器的设计与FPGA实现", 《电子器件》 * |
| 王敏超等: "基于TTCN-3的HINOC MAC测试软件TRI和TCI接口设计", 《网络新媒体技术》 * |
| 赵骞等: "HIMAC调度的C语言实现", 《电子科技》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114401072A (en) * | 2021-12-12 | 2022-04-26 | 西安电子科技大学 | Dynamic cache control method and system for frame splitting and reordering queue based on HINOC protocol |
| CN114401072B (en) * | 2021-12-12 | 2024-02-06 | 西安电子科技大学 | Dynamic buffer control method and system for frame disassembly reordering queue based on HINOC protocol |
| CN114465696A (en) * | 2022-04-12 | 2022-05-10 | 井芯微电子技术(天津)有限公司 | State machine verification method and system based on state transition mode |
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