CN112953679B - Method, device, medium, terminal and system for controlling data transmission coprocessor in deterministic network - Google Patents
Method, device, medium, terminal and system for controlling data transmission coprocessor in deterministic network Download PDFInfo
- Publication number
- CN112953679B CN112953679B CN202110175099.9A CN202110175099A CN112953679B CN 112953679 B CN112953679 B CN 112953679B CN 202110175099 A CN202110175099 A CN 202110175099A CN 112953679 B CN112953679 B CN 112953679B
- Authority
- CN
- China
- Prior art keywords
- data
- crc
- network
- sending
- check
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/12—Applying verification of the received information
- H04L63/126—Applying verification of the received information the source of the received data
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
- H04L69/164—Adaptation or special uses of UDP protocol
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2463/00—Additional details relating to network architectures or network communication protocols for network security covered by H04L63/00
- H04L2463/121—Timestamp
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The invention belongs to the technical field of data transmission networks, and discloses a control method, a system and an application of a data transmission coprocessor in a deterministic network, wherein a sending end is sent to the coprocessor when needing to send data; firstly, entering a check information adding module to add a sending serial number and a sending timestamp; when the receiving end receives the data frame, checking through the source end identification of the network configured by the user in advance to verify the source correctness of the data; calculating the consumed time in the sending process according to the local time value which is synchronized by combining the synchronization function in the network; after the calculation is finished, comparing the time delay with the transmission time delay determined in advance in the network; the receiving end may continuously maintain a register in accordance with the above problems when data originating from a link occurs. The invention can reduce the collision rate of the data check code while ensuring that the data is not modified in the data transmission process, and can actively report the abnormal link.
Description
Technical Field
The invention belongs to the technical field of data transmission networks, and particularly relates to a control method, a system and application of a data transmission coprocessor in a deterministic network.
Background
At present: in a traditional data transmission network, the UDP layer and the IP layer both have header checksum contents to guarantee data, but the generation mode of the checksum is simple and is only used for judging whether the data has errors in the transmission process, and the problem that the data is tampered in the transmission process cannot be detected. In the MAC layer, cyclic redundancy check of data is performed, and a cyclic redundancy check is performed on the data that has been encapsulated in the MAC as a basis for data correctness. The data error detection mode of the above general protocol layer is known by the general public, and can only deal with the case that data is in error in the transmission process, and is useless for the case that data is maliciously tampered in the transmission process.
Additionally, there is only one reception check function for time triggered traffic in time triggered ethernet, which checks whether the received MAC frame arrives at the receiving end at the expected time. However, the two functions are not implemented in the same module, and because a certain time difference exists between the lengths of the data transmission between the two modules and the time recording points of the two modules are not symmetrical between the transmitting side and the receiving side, the statistical transmission time cannot be real and accurate, and finally whether the data arrives at the specified time cannot be accurately judged; in the aspect of data source inspection, besides encryption of transmission data, no relatively complete scheme is available for verification, and data from a network cannot be source-confirmed at a data receiving end, so that the currently received data can be identified as originating from members inside the network or originating from attackers outside the network.
With the advanced development of network technology, the application of network technology to industrial control is increasing, and the most popular solution for the industrial control network in the aerospace scene is time-triggered ethernet. However, a single event upset effect exists during data transmission in aerospace, which may cause unpredictable errors in the data transmission process, and finally cause the receiving end to fail to correctly receive the data that the transmitting end expects to receive. For this situation, it is necessary to detect the correctness of data transmitted in the network. Meanwhile, as a plurality of different types and different sending rules exist in the network, a congestion situation may occur when the data service planning is too dense, and naturally, the data cannot reach a receiving end at a specified time due to the congestion situation in the network. For this situation, data real-time detection needs to be performed on data transmitted in the network. In some specific cases, there may be a usage error or a situation of deliberate destruction, which causes a device to erroneously send misleading data to a target device, which causes a target receiving end to perform an erroneous response action, and finally causes an unknown error of the network and finally affects the operation of the whole network. For this situation, it is necessary to detect the correctness of the data source of the data transmitted in the network.
All the above problems need to be solved by that the end node of the network can have a function of detecting the correctness, real-time property and source correctness of data at the same time, so that a detection mode with load and a data frame structure suitable for the current network data message are needed.
Through the above analysis, the problems and defects of the prior art are as follows:
(1) The protection method for the data transmission process in the traditional Ethernet comprises a checksum method in UDP/IP and a CRC (cyclic redundancy check) method in an MAC (media access control) layer, and the network development time is long, so that the verification method of each layer in the traditional Ethernet is widely spread.
(2) And the problem of inaccurate time caused by the traditional receiving and checking function.
(3) The data bit width used when generating the CRC in the conventional MAC is 8 bits, and the rate is slow when transmitting data.
The difficulty in solving the above problems and defects is:
(1) The invention provides a brand-new method for verifying data, aiming at the problem that how to break through the limitation of the traditional method in the widely used transmission mode of the existing Ethernet, and simultaneously, the transmitted data is verified and protected in multiple modes.
(2) The problem of statistics on data receiving and sending time needs to be solved in a synchronous network, and because the data transmission lengths are different and a phenomenon that multiple paths of data are transmitted simultaneously exists, how to correctly make correct transmission time statistics on transmitted data is a technical problem.
(3) In the conventional MAC, when performing CRC calculation on data during transmission and reception, bit width conversion is required first, and then CRC check code generation is performed, so that the time for transmitting data is multiplied, and how to perform CRC check code calculation in a high bit width state is a problem in academia at present.
The significance of solving the problems and the defects is as follows:
(1) The transmitted data is protected in a multi-layer way by customizing the private protocol in the special deterministic network, and a new idea and solution are provided for the development of the transmission way of the future public network.
(2) The transmission delay statistical work of the same data is very meaningful, because the deterministic network has a strict requirement on the real-time performance of the data, the transmission time point of the data needs to be determined, the time spent in the transmission process is determined, the receiving time point is also determined, and after the time spent on data transmission is fully grasped, the bandwidth utilization rate of the whole network can be better controlled, and more data can be transmitted.
(3) The traditional CRC generation method has too low processing rate, can become a bottleneck in the data transmission process, and in order to avoid generating unnecessary time delay influence in the module and absorb the defect of CRC generation in MAC, the CRC is calculated by using 32bit width and matched with a 32bit bus for data transceiving outside the module, so that the optimization of data processing rate is achieved.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a method, a system and an application for controlling a data transmission coprocessor in a deterministic network.
The invention is realized in such a way that a data transmission coprocessor control method in a deterministic network comprises the following steps:
when a sending end needs to send data, the sending end is sent to the coprocessor; firstly, entering a check information adding module to add a sending serial number and a sending time stamp;
when the receiving end receives the data frame, checking through the source end identification of the network configured by the user in advance to verify the source correctness of the data;
combining the synchronization function in the network, inputting the time point when the data is sent, extracting the sending time point of the sending end after the receiving side at the other end receives the data, and then calculating the consumed time in the sending process according to the local time value after the synchronization is finished;
after the calculation is finished, comparing the data with the transmission time delay determined in advance in the network, judging the data as overtime data once the data exceeds the maximum threshold value specified by the user, and not receiving the data;
when data originating from a link appears: when the continuous serial number is lost or disordered, the time consumed in the sending process is too long, and the source end fails in verification, the receiving end can continuously maintain a register according to the problems as the 'life value' of the link, and once the 'life value' of the link is lower than the minimum threshold required by a user, the current connection can be disconnected.
The CRC check code generated in a special mode can better ensure the verification of the data source during data transmission, and the verification not only needs to have a correct CRC generating polynomial, but also needs to have a correct source end number. The addition of the serial number can enable the receiving end to check the continuity of the received data, and verify whether the currently received data is continuous with the last data through the recorded serial number. The existence of the 'life value' can monitor the condition of the data link in real time in the data transmission process, and continuously and quantitatively update the individual data link according to the identification of the received data.
Further, the control method of the data transmission coprocessor in the deterministic network comprises a frame format for carrying out secondary packaging on data in a UDP layer, and packaged contents;
a method for judging whether the data accords with the receiving rule or not by the three elements of the serial number, the timestamp and the CRC check code in the packaged content;
and the CRC verification code in the encapsulated content is calculated by adding a source end number which is not transmitted when the sending end generates the CRC verification code, and the receiving end needs to calculate again by combining the source end number when receiving the CRC verification code so as to verify the correctness of the data source.
Further, the processing procedure of the data sending end of the data transmission coprocessor control method in the deterministic network includes:
(1) Inputting data;
(2) Judging according to the length of the data, and judging whether the length of the data is integral multiple of 4 bytes or not because the internal transmission width is 32 bits, and judging whether the operation of adding 0 is required to be carried out at the front end of the data or not;
(3) After the operation of adding 0 is completed, adding header information to the head of the data, and adding a sequence number and a sending time stamp to the head;
(4) After the serial number and the timestamp of the head are added, the data enters different directions in two paths, and is sent to a cache block for caching while being sent to a CRC generation module for generating a CRC calculation result after the unique network identifier of the local equipment is added to the head;
(5) When the data sent to the CRC generation module is finished, two CRC calculation results of the data are obtained, and the CRC results are input into a buffer area;
(6) And outputting the data frame added by the verification information.
Further, the CRC of the data transmission coprocessor control method in the deterministic network generates input and output time sequences, and after the data are added with the unique identifier, the serial number and the timestamp of the source end system, the data are sent to a CRC generation module for CRC generation; the input signals of the CRC module are: CRC _ data _ input data input to be calculated, 32-bit width data signal) a CRC _ init CRC module initialization signal, a high level valid signal and a CRC _ data _ en CRC input data valid signal; high level is effective, a CRC _ getResult CRC check code result acquires a signal, and a high level single pulse is effective;
in the process of continuously inputting data, the CRC generation module continuously calculates the CRC check code of the currently input data, and after the data input is finished, a single-pulse high level is given to CRC _ getResult, so that the CRC check code result can be output in the next clock cycle.
Further, the processing procedure of the data receiving end of the data transmission coprocessor control method in the deterministic network includes:
(1) Inputting data;
(2) Judging according to the length of the data, and judging whether the length of the data is integral multiple of 4 bytes or not because the internal transmission width is 32 bits, and judging whether the operation of adding 0 is required to be carried out at the front end of the data or not;
(3) After the operation of adding 0 is completed, extracting a serial number, a timestamp and a CRC (cyclic redundancy check) code at the tail part attached in the data frame to prepare for subsequent information check;
(4) After the extraction of the serial number and the time stamp of the head is finished, the data enters different directions in two paths. While sending to the cache block for caching, the head needs to be added with the network unique identifier of the source end device and then sent to a CRC generation module for generating a CRC calculation result; checking the serial number and the timestamp at the same time, and checking the serial number continuity of a serial number register maintained by the current link; checking whether excessive time is spent in the data frame transmission process by checking the local synchronization time and the extracted frame transmission time point;
(5) When the data sent to the CRC generation module is finished, two CRC calculation results of the data are obtained, and the CRC results are compared with the CRC check codes extracted before to check whether the CRC results are consistent or not;
(6) And a checking information checking part for determining whether the data frame meets the checking requirement and judging whether to output the data frame according to the checking result.
It is a further object of the invention to provide a computer device comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, causes the processor to perform the steps of:
when the sending end needs to send data, the sending end is sent to the coprocessor; firstly, entering a check information adding module to add a sending serial number and a sending timestamp;
when the receiving end receives the data frame, checking through the source end identification of the network configured by the user in advance to verify the source correctness of the data;
combining the synchronization function in the network, inputting the time point when the data is sent, extracting the sending time point of the sending end after the receiving side at the other end receives the data, and then calculating the consumed time in the sending process according to the local time value after the synchronization is finished;
after the calculation is finished, comparing the data with the transmission time delay determined in advance in the network, judging the data as overtime data once the data exceeds the maximum threshold value specified by the user, and not receiving the data;
when data originating from a link appears: when the continuous serial number is lost or disordered, the time consumed in the sending process is too long, and the source end fails in verification, the receiving end can continuously maintain a register according to the problems as the 'life value' of the link, and once the 'life value' of the link is lower than the minimum threshold required by a user, the current connection can be disconnected.
It is another object of the present invention to provide a computer-readable storage medium storing a computer program which, when executed by a processor, causes the processor to perform the steps of:
when the sending end needs to send data, the sending end is sent to the coprocessor; firstly, entering a check information adding module to add a sending serial number and a sending time stamp;
when a receiving end receives a data frame, verifying the source correctness of the data through the identifiers of the source ends of the network, which are configured in advance by a user;
combining with a synchronization function in a network, inputting a time point when data is transmitted, extracting the transmission time point of a transmitting end after a receiving side at the other end receives the data, and then calculating the consumed time in the transmission process according to a local time value after synchronization is completed;
after the calculation is finished, comparing the data with the transmission delay determined in advance in the network, judging the data as overtime data once the data exceeds the maximum threshold value specified by the user, and not receiving the data;
when data originating from a link appears: when the continuous serial number is lost or disordered, the consumption time in the sending process is too long, and the source end fails to verify, the receiving end can continuously maintain a register according to the problems to be used as the 'life value' of the link, and once the 'life value' of the link is lower than the minimum threshold value required by a user, the current connection can be disconnected.
Another object of the present invention is to provide an information data processing terminal for implementing the data transfer coprocessor control method in a deterministic network.
Another object of the present invention is to provide a data transfer coprocessor control system in a deterministic network implementing the data transfer coprocessor control method in the deterministic network, the data transfer coprocessor control system in the deterministic network comprising:
receiving end: the system comprises a check information adding module, a CRC-X generating module and a CRC-Y generating module;
a sending end: the system comprises a check information verification module, a CRC-X generation module and a CRC-Y generation module;
a check information adding module: adding check information to the data issued by the upper layer to complete the detection of adding 0 to the data, so that the data are aligned, and the subsequent generation of CRC results is facilitated;
a verification information verification module: verifying the verification information of the data from the network, and locally verifying the pre-filled sending end information;
CRC-X and CRC-Y modules: the user can pre-configure a corresponding CRC polynomial with a width of 16 bits, and perform CRC operation on the input data and the identifier of the source end device to obtain a CRC calculation result.
Another object of the present invention is to provide a data transfer network control system for operating the data transfer coprocessor control method in the deterministic network.
By combining all the technical schemes, the invention has the advantages and positive effects that:
(1) The protection method for the data transmission process in the traditional Ethernet comprises a checksum method in UDP/IP and a CRC (cyclic redundancy check) method in an MAC (media access control) layer, and the network development time is long, so that the verification method of each layer in the traditional Ethernet is widely spread. Therefore, the data cannot be detected if the data is modified maliciously in the data transmission process. Aiming at the situation, the invention adds two additional CRC checks in the UDP layer and generates two check codes by using different polynomials, thereby ensuring that the data transmission process is not modified and simultaneously reducing the collision rate of the data check codes.
(2) Compared with the receiving and checking function of the traditional deterministic Ethernet, the invention effectively avoids the problem of inaccurate time brought by the traditional receiving and checking function by arranging symmetrical modules at the receiving and sending ends for transmission time statistics. The invention also supports the management function of the link, and can actively report the abnormal link after the excessive time spent on the continuity of a certain link is found for a plurality of times for transmission.
(3) Compared with the prior art, the invention develops the function of authenticating the data source end, and the sending end adds the unique serial number of the local machine in the network without transmission in the data generating the CRC code when sending the data, so that the receiving end can correctly verify the source of the data only by using the correct serial number of the source end after receiving the data. The source end number should be planned perfectly when planning the network, and the whole network should be completely configured after being electrified. According to the characteristics of the deterministic network and the topology of the network as a whole, the number of devices should be determined, so each device should know the number corresponding to the source of the data.
(4) The bit width of data used when CRC is generated in the traditional MAC is 8 bits, and the rate is slower when the data is transmitted, but because an additional non-data field is added when the CRC is calculated, in order to improve the calculation speed, the calculation is carried out by adopting the width of 32 bits, and the CRC calculation problem of the data when the length is not 4 bytes integral multiple is solved by adding 0 at the head.
The data transmission control coprocessor developed based on the FPGA supports the functions of receiving, sending and detecting data to and from a network. By adopting the improved 32-bit CRC calculation mode, data can be transmitted into the CRC generator in a 32-bit mode, and the CRC result is directly output when the data is finished, so that the data with the same length is transmitted by only consuming 25% of the original time compared with the mode of generating 8 bits in the MAC.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and it is obvious for those skilled in the art that other drawings can be obtained from the drawings without creative efforts.
Fig. 1 is a flowchart of a method for controlling a data transfer coprocessor in a deterministic network according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a data transfer coprocessor control system in a deterministic network according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a data processing process according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a protocol hierarchy provided by an embodiment of the present invention.
Fig. 5 is a schematic diagram of a data encapsulation frame structure according to an embodiment of the present invention.
Fig. 6 is a flowchart of processing at a data transmitting end according to an embodiment of the present invention.
Fig. 7 is a schematic diagram of input and output timing sequences of a CRC generation module according to an embodiment of the present invention.
Fig. 8 is a flowchart of a data receiving end process according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In view of the problems in the prior art, the present invention provides a method, a system and an application for controlling a data transfer coprocessor in a deterministic network, and the present invention is described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the method for controlling a data transfer coprocessor in a deterministic network provided by the present invention includes the following steps:
s101: when the sending end needs to send data, the sending end is sent to the coprocessor; firstly, entering a check information adding module to add a sending serial number and a sending timestamp;
s102: when a receiving end receives a data frame, verifying the source correctness of the data through the identifiers of the source ends of the network, which are configured in advance by a user;
s103: combining the synchronization function in the network, inputting the time point when the data is sent, extracting the sending time point of the sending end after the receiving side at the other end receives the data, and then calculating the consumed time in the sending process according to the local time value after the synchronization is finished;
s104: after the calculation is finished, comparing the data with the transmission time delay determined in advance in the network, judging the data as overtime data once the data exceeds the maximum threshold value specified by the user, and not receiving the data;
s105: when data originating from a link appears: when the continuous serial number is lost or disordered, the time consumed in the sending process is too long, the source end verification fails and the like, the receiving end can continuously maintain a register according to the problems to be used as the 'life value' of the link, and once the 'life value' of the link is lower than the minimum threshold value required by a user, the current connection can be disconnected.
The invention provides a guarantee method for data transmission in a deterministic network, which comprises a frame format for carrying out secondary encapsulation on data in a UDP layer and encapsulated contents;
and the serial number, the time stamp and the CRC code in the packaged content jointly judge whether the data conforms to the receiving rule.
And the CRC verification code in the encapsulated content is calculated by adding a source end number which is not transmitted when the sending end generates the CRC verification code, and the receiving end needs to calculate again by combining the source end number when receiving the CRC verification code so as to verify the correctness of the data source.
Those skilled in the art of the method for controlling a coprocessor for data transfer in a deterministic network provided by the present invention may also implement other steps, and the method for controlling a coprocessor for data transfer in a deterministic network provided by the present invention in fig. 1 is only one specific embodiment.
As shown in fig. 2, the data transfer coprocessor control system in the deterministic network provided by the present invention includes:
receiving end: comprises a check information adding module, a CRC-X generating module and a CRC-Y generating module.
A sending end: the system comprises a check information verification module, a CRC-X generation module and a CRC-Y generation module.
A check information adding module: and performing check information adding operation on the data issued by the upper layer to complete the '0 adding' detection on the data, so that the data are aligned, and the subsequent generation of a CRC result is facilitated.
A verification information verification module: and verifying the verification information of the data from the network, and locally verifying the pre-filled sending end information.
CRC-X and CRC-Y modules: the user can pre-configure a corresponding CRC polynomial with a width of 16 bits, and perform CRC operation on the input data and the identifier of the source end device to obtain a CRC calculation result.
The technical solution of the present invention is further described below with reference to the accompanying drawings.
Fig. 3 is a detailed analysis diagram of the data processing process. When the sending end needs to send data, the sending end is sent to the coprocessor. The method comprises the steps of firstly entering a check information adding module to add a sending serial number and a sending time stamp. In the figure, the EQ _ ID is the unique identifier of the sending source end in the network, the identifier is not put into a data frame for transmission, and is added into the data frame for calculation only when CRC is generated, and when the receiving end receives the data frame, the source correctness of the data is verified through the identifiers of the source ends of the network, which are configured in advance by a user, so that the data attack caused by a third party pretending the source end is avoided. In the figure, "SN" is identified as a sending sequence number, which can ensure the continuity of current data and avoid the situation that data is lost in the transmission process but is not detected to be lost. "TS" in the figure identifies a time point when the transmitting end transmits data. Combining the synchronization function in the network, the time point of sending is input when the data is sent, the sending time point of the sending end can be extracted after the receiving side at the other end receives the data, and then the consumed time calculation in the sending process is carried out according to the time value of local synchronization. After the calculation is completed, the data is judged as overtime data by comparing with the transmission delay determined in advance in the network, and the data is not received once the maximum threshold value specified by the user is exceeded. When data originating from a link appears: when the continuous serial number is lost or disordered, the consumption time in the sending process is too long, the source end fails to verify and the like, the receiving end can continuously maintain a register according to the problems to be used as the 'life value' of the link, and once the 'life value' of the link is lower than the minimum threshold value required by a user, the current connection can be disconnected.
Fig. 4 is a protocol level of the method of the present invention. The data encapsulation is positioned in the UDP load, the addition of the verification information is directly carried out on the data of the user after the data is transmitted, and the data can be used together with a hardware protocol stack or used with a software protocol stack. Fig. 5 is a data frame structure of the method of the present invention. The frame structure of the data frame in the transmission process is shown in the figure, and comprises an SN (namely a sequence number) field with the width of 32 bits, a TS (namely a time stamp) field with the width of 48 bits, a user data load with the length of 1-1476 bytes, and CRC-X and CRC-Y check calculation results with the width of 16 bits.
The following explains the working principle flow of the technical scheme.
1. Data sending terminal
(1) And (6) inputting data.
(2) And judging according to the length of the data, wherein the internal transmission width is 32 bits, so that whether the length of the data is an integral multiple of 4 bytes or not needs to be checked, and whether 0 adding operation needs to be carried out at the front end of the data or not is judged.
(3) After the "add 0" operation is completed, header information is added to the header of the data, and a sequence number and a transmission time stamp are added to the header.
(4) After the serial number and the time stamp of the head are added, the data enter different directions in two paths. While sending to the cache block for caching, the head needs to be added with the network unique identifier of the local equipment and then sent to the CRC generation module for generating the CRC calculation result.
(5) When the data to the CRC generation module is finished, two CRC calculation results of the data are obtained and the CRC results are input into the buffer.
(6) And outputting the data frame added with the check information.
Fig. 6 is a flow chart of data processing at the transmitting end.
Fig. 7 is an input and output timing of the CRC generation module.
After the unique identifier, the serial number and the timestamp of the source end system are added, the data are sent to a CRC generation module for CRC generation. The input signals of the CRC module are respectively: CRC _ data _ input (data input to be calculated, 32bit wide data signal), CRC _ init (CRC module initialization signal, active high), CRC _ data _ en (CRC input data valid signal, active high), CRC _ getResult (CRC check code result acquisition signal, active high).
In the process of continuously inputting data, the CRC generation module continuously calculates the CRC check code of the currently input data, and after the data input is finished, a single-pulse high level is given to CRC _ getResult, so that the CRC check code result can be output in the next clock cycle.
2. Data receiving terminal
(1) And (6) inputting data.
(2) And judging according to the length of the data, wherein the internal transmission width is 32 bits, so that whether the length of the data is an integral multiple of 4 bytes or not needs to be checked, and whether 0 adding operation needs to be carried out at the front end of the data or not is judged.
(3) After the operation of adding 0 is completed, extracting the sequence number, the timestamp and the CRC code at the tail part attached in the data frame to prepare for the subsequent information check.
(4) After the extraction of the serial number and the timestamp of the head is completed, the data enters different directions in two paths. While sending to the cache block for caching, the head needs to be added with the network unique identifier of the source end device and then sent to the CRC generation module for generating the CRC calculation result. In addition, the checking work of the serial number and the timestamp is carried out simultaneously, and the serial number continuity check is carried out on a serial number register maintained by the current link; by checking the local synchronization time and the extracted frame transmission time point, it is checked whether the data frame transmission process takes too much time.
(5) When the data sent to the CRC generation module is finished, two CRC calculation results of the data are obtained, and the CRC results are compared with the CRC check codes extracted previously to check whether the data are consistent.
(6) And a check information checking part for checking whether the data frame meets the check requirement and judging whether to output the data frame according to the check result.
Fig. 8 is a flow chart of a data reception process.
It should be noted that the embodiments of the present invention can be realized by hardware, software, or a combination of software and hardware. The hardware portions may be implemented using dedicated logic; the software portions may be stored in a memory and executed by a suitable instruction execution system, such as a microprocessor or specially designed hardware. Those skilled in the art will appreciate that the apparatus and methods described above may be implemented using computer executable instructions and/or embodied in processor control code, such code being provided on a carrier medium such as a disk, CD-or DVD-ROM, programmable memory such as read only memory (firmware), or a data carrier such as an optical or electronic signal carrier, for example. The apparatus of the present invention and its modules may be implemented by hardware circuits such as very large scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field programmable gate arrays, programmable logic devices, or software executed by various types of processors, or a combination of hardware circuits and software, e.g., firmware.
The above description is only for the purpose of illustrating the present invention and the appended claims are not to be construed as limiting the scope of the invention, and any modifications, equivalents and improvements made by those skilled in the art within the spirit and principle of the present invention are intended to be covered by the present invention.
Claims (10)
1. A method for controlling a data transfer coprocessor in a deterministic network, the method comprising:
when the sending end needs to send data, the sending end is sent to the coprocessor; firstly, entering a check information adding module to add a sending serial number and a sending time stamp;
when a receiving end receives a data frame, checking through the numbers of the source ends of the network, which are configured by a user in advance, and verifying the source correctness of the data;
combining with a synchronization function in a network, inputting a time point when data is transmitted, extracting the transmission time point of a transmitting end after a receiving side at the other end receives the data, and then calculating the consumed time in the transmission process according to a local time value after synchronization is completed;
after the calculation is finished, comparing the data with the transmission time delay determined in advance in the network, judging the data as overtime data once the data exceeds the maximum threshold value specified by the user, and not receiving the data;
when data originating from a link appears: when the continuous serial number is lost or disordered, the time consumed in the sending process is too long, and the source end fails in verification, the receiving end can continuously maintain a register according to the problems as the 'life value' of the link, and once the 'life value' of the link is lower than the minimum threshold required by a user, the current connection can be disconnected.
2. A method for data transfer coprocessor control in a deterministic network as claimed in claim 1, characterized in that it comprises encapsulating data in a UDP layer;
the serial number, the time stamp and the CRC code in the packaged content jointly judge whether the data accords with the receiving rule;
and the CRC code in the encapsulated content is calculated by adding a source end number which is not transmitted when the transmitting end generates the CRC code, and the receiving end needs to calculate again by combining the source end number when receiving the CRC code so as to verify the correctness of the data source.
3. The method of claim 1, wherein the processing at the data sender of the deterministic network comprises:
(1) Inputting data;
(2) Judging according to the length of the data, and judging whether the length of the data is integral multiple of 4 bytes or not because the internal transmission width is 32 bits, and judging whether the operation of adding 0 is required to be carried out at the front end of the data or not;
(3) After the operation of adding 0 is completed, adding header information to the header of the data, and adding a sequence number and a sending time stamp to the header;
(4) After the serial number and the timestamp of the head are added, the data enters different directions in two paths, and is sent to a cache block for caching while being sent to a CRC generation module for generating a CRC calculation result after the unique network identifier of the local equipment is added to the head;
(5) When the data sent to the CRC generation module is finished, two CRC calculation results of the data are obtained, and the CRC results are input into a buffer area;
(6) And outputting the data frame added with the check information.
4. The method of claim 1, wherein the CRC of the method generates input and output timing sequences, and the data is sent to the CRC generation module for CRC check code generation after the addition of the unique identifier, the sequence number, and the timestamp of the source system is completed; the input signals of the CRC module are: inputting CRC _ data _ input data to be calculated, and outputting a data signal with the width of 32 bits; the CRC _ init CRC module initializes signals, and the high level is effective; the CRC _ data _ en CRC inputs a data valid signal, the high level is valid; a CRC _ getResult CRC code result acquires a signal, and a high-level single pulse is effective;
during the process of data input continuously, the CRC generation module can continuously calculate the CRC check code of the currently input data, and after the data input is finished, a single pulse high level is given to CRC _ getResult, so that the CRC check code result can be output in the next clock cycle.
5. The method for controlling a data transfer coprocessor in a deterministic network according to claim 1, characterized in that the processing at the data receiving end of the method for controlling a data transfer coprocessor in a deterministic network comprises:
(1) Inputting data;
(2) Judging according to the length of the data, wherein the internal transmission width is 32 bits, whether the length of the data is an integral multiple of 4 bytes or not needs to be checked, and whether 0 adding operation needs to be carried out at the front end of the data or not is judged;
(3) After the operation of adding 0 is completed, extracting a sequence number, a timestamp and a CRC (cyclic redundancy check) code at the tail part attached to the data frame to prepare for subsequent information check;
(4) After the extraction of the serial number and the timestamp of the head is finished, the data enters different directions in two paths, is sent to a cache block for caching while being sent to a CRC generation module for generating a CRC calculation result after the unique network identifier of the source-end equipment is added to the head; simultaneously, checking the serial number and the timestamp, and checking the serial number continuity of a serial number register maintained by the current link; checking whether excessive time is spent in the data frame transmission process by checking the local synchronization time and the extracted frame transmission time point;
(5) When the data sent to the CRC generation module is finished, two CRC calculation results of the data are obtained, and the CRC results are compared with the CRC check codes extracted previously to check whether the two CRC calculation results are consistent;
(6) And a check information checking part for checking whether the data frame meets the check requirement and judging whether to output the data frame according to the check result.
6. A computer device, characterized in that the computer device comprises a memory and a processor, the memory storing a computer program which, when executed by the processor, causes the processor to carry out the steps of:
when a sending end needs to send data, the sending end is sent to the coprocessor; firstly, entering a check information adding module to add a sending serial number and a sending timestamp;
when the receiving end receives the data frame, checking through the source end identification of the network configured by the user in advance to verify the source correctness of the data;
combining the synchronization function in the network, inputting the time point when the data is sent, extracting the sending time point of the sending end after the receiving side at the other end receives the data, and then calculating the consumed time in the sending process according to the local time value after the synchronization is finished;
after the calculation is finished, comparing the data with the transmission time delay determined in advance in the network, judging the data as overtime data once the data exceeds the maximum threshold value specified by the user, and not receiving the data;
when data originating from a link appears: when the continuous serial number is lost or disordered, the consumption time in the sending process is too long, and the source end fails to verify, the receiving end can continuously maintain a register according to the problems to be used as the 'life value' of the link, and once the 'life value' of the link is lower than the minimum threshold value required by a user, the current connection can be disconnected.
7. A computer-readable storage medium storing a computer program which, when executed by a processor, causes the processor to perform the steps of:
when the sending end needs to send data, the sending end is sent to the coprocessor; firstly, entering a check information adding module to add a sending serial number and a sending time stamp;
when the receiving end receives the data frame, checking through the source end identification of the network configured by the user in advance to verify the source correctness of the data;
combining with a synchronization function in a network, inputting a time point when data is transmitted, extracting the transmission time point of a transmitting end after a receiving side at the other end receives the data, and then calculating the consumed time in the transmission process according to a local time value after synchronization is completed;
after the calculation is finished, comparing the data with the transmission delay determined in advance in the network, judging the data as overtime data once the data exceeds the maximum threshold value specified by the user, and not receiving the data;
when data originating from a link appears: when the continuous serial number is lost or disordered, the consumption time in the sending process is too long, and the source end fails to verify, the receiving end can continuously maintain a register according to the problems to be used as the 'life value' of the link, and once the 'life value' of the link is lower than the minimum threshold value required by a user, the current connection can be disconnected.
8. An information data processing terminal, characterized in that the information data processing terminal is adapted to implement the data transfer coprocessor control method in a deterministic network according to any of claims 1 to 5.
9. A data transfer coprocessor control system in a deterministic network implementing the data transfer coprocessor control method in the deterministic network according to any of claims 1 to 5, characterized in that said data transfer coprocessor control system in the deterministic network comprises:
a sending end: the system comprises a check information adding module, a CRC-X generating module and a CRC-Y generating module;
receiving end: the system comprises a check information verification module, a CRC-X generation module and a CRC-Y generation module;
a check information adding module: adding check information to the data issued by the upper layer to complete the detection of adding 0 to the data, so that the data are aligned, and the subsequent generation of CRC results is facilitated;
a verification information verification module: verifying the verification information of the data from the network, and locally verifying the pre-filled sending end information;
CRC-X and CRC-Y modules: the user can pre-configure a corresponding CRC polynomial with a width of 16 bits, and perform CRC operation on the input data and the identifier of the source end device to obtain a CRC calculation result.
10. A data transmission network control system, characterized in that the data transmission network control system is adapted to operate the data transmission co-processor control method in a deterministic network according to any of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110175099.9A CN112953679B (en) | 2021-02-09 | 2021-02-09 | Method, device, medium, terminal and system for controlling data transmission coprocessor in deterministic network |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110175099.9A CN112953679B (en) | 2021-02-09 | 2021-02-09 | Method, device, medium, terminal and system for controlling data transmission coprocessor in deterministic network |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112953679A CN112953679A (en) | 2021-06-11 |
| CN112953679B true CN112953679B (en) | 2022-11-15 |
Family
ID=76244410
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110175099.9A Active CN112953679B (en) | 2021-02-09 | 2021-02-09 | Method, device, medium, terminal and system for controlling data transmission coprocessor in deterministic network |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112953679B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114253211B (en) * | 2021-12-15 | 2024-09-20 | 意欧斯智能科技股份有限公司 | Method for performing interactive verification on PLC and upper computer WCS signals |
| CN114448956A (en) * | 2022-01-25 | 2022-05-06 | 中电科航空电子有限公司 | Airborne digital audio system middleware protocol method based on universal data network |
| CN115150251B (en) * | 2022-05-27 | 2023-11-03 | 中国南方电网有限责任公司 | Fault diagnosis method, system and management platform for dispatching communication link of power private network |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108155982A (en) * | 2016-12-02 | 2018-06-12 | 深圳市中兴微电子技术有限公司 | A kind of timestamp processing method and equipment |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7649912B2 (en) * | 2005-04-27 | 2010-01-19 | Rockwell Automation Technologies, Inc. | Time synchronization, deterministic data delivery and redundancy for cascaded nodes on full duplex ethernet networks |
| US9031071B2 (en) * | 2005-08-26 | 2015-05-12 | Alcatel Lucent | Header elimination for real time internet applications |
| US10620241B2 (en) * | 2012-02-17 | 2020-04-14 | Perspecta Labs Inc. | Method and system for packet acquisition, analysis and intrusion detection in field area networks |
| US10135711B2 (en) * | 2015-12-22 | 2018-11-20 | Intel Corporation | Technologies for sideband performance tracing of network traffic |
-
2021
- 2021-02-09 CN CN202110175099.9A patent/CN112953679B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108155982A (en) * | 2016-12-02 | 2018-06-12 | 深圳市中兴微电子技术有限公司 | A kind of timestamp processing method and equipment |
Non-Patent Citations (1)
| Title |
|---|
| 龚晨亮等.HIMAC协处理器的调度方案.《网络新媒体技术》.2013,(第05期), * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112953679A (en) | 2021-06-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112953679B (en) | Method, device, medium, terminal and system for controlling data transmission coprocessor in deterministic network | |
| US9253062B2 (en) | Byte by byte received data integrity check | |
| CN108462642B (en) | UDP/IP hardware protocol stack based on FPGA and implementation method | |
| US7668107B2 (en) | Hardware implementation of network testing and performance monitoring in a network device | |
| CN109586959B (en) | Fault detection method and device | |
| US11240150B2 (en) | Applying attestation to segment routing | |
| WO2015096636A1 (en) | Method for measuring lost packets and network device | |
| US20230171175A1 (en) | Real-time network-wide link latency monitoring with in-network int sampling and aggregation | |
| CN112350897B (en) | Network testing device based on dynamic connection end-to-end reliable transmission protocol | |
| CN111026324B (en) | Updating method and device of forwarding table entry | |
| CN108449228A (en) | Message processing method and the network equipment | |
| JP2013030909A (en) | Processing device, test signal generating device, and test signal generating method | |
| US20100309908A1 (en) | Method and system for communicating with a network device | |
| Varga et al. | Robustness and reliability provided by deterministic packet networks (TSN and DetNet) | |
| CN111682966B (en) | Network communication device with fault active reporting function, system and method thereof | |
| EP4277206A1 (en) | Securing network access using dynamically generated baud-rates | |
| JP2005142976A (en) | Communication tester | |
| CN107612848B (en) | Debugging method and device and computer readable storage medium | |
| CN116614481A (en) | Multimedia data transmission method, device, equipment and storage medium | |
| CN103516631A (en) | Communication device | |
| CN111083115A (en) | Data transmission method and system | |
| CN110868321B (en) | Fault positioning method and system based on edge calculation algorithm verification | |
| CN112291148B (en) | Method for detecting BFD forwarding path quality through BFD ping | |
| CN111901363B (en) | 5G-Profibus-DP data encryption transmission device based on FPGA | |
| Liu et al. | IP Design and Implementation of TCP Protocol Attack Identification |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |