CN112953224B - DC-DC conversion circuit and power supply - Google Patents

DC-DC conversion circuit and power supply Download PDF

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CN112953224B
CN112953224B CN202110328037.7A CN202110328037A CN112953224B CN 112953224 B CN112953224 B CN 112953224B CN 202110328037 A CN202110328037 A CN 202110328037A CN 112953224 B CN112953224 B CN 112953224B
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mos tube
flip
flop
signal
current
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CN112953224A (en
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叶强
牛海领
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Anbao Integrated Circuit (Xi'an) Co.,Ltd.
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Guangzhou Shikun Electronic Technology Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection

Abstract

The application provides a DC-DC converting circuit and power, this DC-DC converting circuit includes: current sampling module, peak current limiting circuit, logic module, biasing module and oscillator slope compensation module, wherein: the logic module is used for outputting a segmented frequency control logic signal under the action of the oscillator signal, the peak current limiting signal and the minimum current peak value signal, and the segmented frequency control logic signal is used for segmented frequency modulation of different phase intervals; the oscillator slope compensation module is used for outputting an oscillator signal and slope compensation current under the action of the segmented frequency control logic signal, and the duty ratios of the oscillator signal in different phase regions are different; the peak current limiting circuit is used for outputting a minimum current peak value signal under the action of the slope compensation current, the sampling current and the bias current, and the peak current limiting circuit is used for controlling the minimum current peak value during light load. The application reduces output ripples while lightly loading the high efficiency.

Description

DC-DC conversion circuit and power supply
Technical Field
The embodiment of the application relates to the electronic technology, in particular to a DC-DC conversion circuit and a power supply.
Background
For the DC-DC conversion circuit, low ripple and light load high efficiency play a very important role in the system standby power consumption and safe operation of the DC-DC conversion circuit. Therefore, in order to save energy and reduce the standby power consumption of the system, a Pulse Skip Modulation (PSM) mode is adopted during light load. However, for PSM, when the load changes suddenly, the output ripple is large, so there is a contradiction between light load efficiency and low ripple.
Disclosure of Invention
The application provides a DC-DC conversion circuit and a power supply, which are used for solving the contradiction between light load high efficiency and low ripple, and reducing output ripple while the light load is high efficiency.
In a first aspect, an embodiment of the present application provides a DC-DC conversion circuit, including: current sampling module, current limit module, peak current limit circuit, logic module, biasing module and oscillator slope compensation module, wherein:
the logic module is used for outputting a segmented frequency control logic signal under the action of an oscillator signal output by the oscillator slope compensation module, a peak current limiting signal output by the current limiting module and a minimum current peak signal output by the peak current limiting circuit, and the segmented frequency control logic signal is used for segmented frequency modulation of different phase intervals;
the oscillator slope compensation module is used for outputting an oscillator signal and slope compensation current under the action of the segmented frequency control logic signal, and the duty ratios of the oscillator signal in different phase regions are different;
and the peak current limiting circuit is used for outputting a minimum current peak value signal under the action of the slope compensation current, the sampling current output by the current sampling module and the bias current output by the bias module, and is used for controlling the minimum current peak value during light load.
In a second aspect, an embodiment of the present application provides a power supply, including: a filter circuit, a load and a DC-DC converter circuit as described in the first aspect, wherein the DC-DC converter circuit is connected to the load via the filter circuit.
In a DC-DC conversion circuit and a power supply provided by the present application, the DC-DC conversion circuit includes: the circuit comprises a current sampling module, a current limiting module, a peak current limiting circuit, a logic module, a bias module and an oscillator slope compensation module, wherein the logic module is used for outputting a segmented frequency control logic signal under the action of an oscillator signal output by the oscillator slope compensation module, a peak current limiting signal output by the current limiting module and a minimum current peak signal output by the peak current limiting circuit, and the segmented frequency control logic signal is used for segmented frequency modulation of different phase intervals; the oscillator slope compensation module is used for outputting an oscillator signal and slope compensation current under the action of the segmented frequency control logic signal, and the duty ratios of the oscillator signal in different phase regions are different; and the peak current limiting circuit is used for outputting a minimum current peak value signal under the action of the slope compensation current, the sampling current output by the current sampling module and the bias current output by the bias module, and is used for controlling the minimum current peak value during light load. In the application, on one hand, the minimum current peak value under the light load condition is controlled through the peak current limiting circuit, so that the aim of high efficiency under the light load is fulfilled; on the other hand, the light-load ripple can be reduced under the condition of light load through the segmented frequency modulation of the segmented frequency control logic signals in different phase intervals, and the low ripple is realized.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1a shows a schematic block diagram of a common peak current mode DC-DC conversion circuit;
FIG. 1b shows a schematic diagram of an application of a DC-DC converter circuit;
FIG. 2 is a schematic diagram of waveforms of inductive current and capacitive ripple;
fig. 3 is a schematic block diagram of a DC-DC conversion circuit provided in an embodiment of the present application;
FIG. 4 is a block diagram of a slope compensation module of the oscillator of FIG. 3;
FIG. 5 is a schematic diagram of internal waveforms of the logic block of FIG. 3;
FIG. 6 is a block diagram of the logic module of FIG. 5;
FIG. 7 is a schematic diagram of a peak current limiting circuit of FIG. 3;
FIG. 8 is a waveform diagram corresponding to the slope compensation module of the oscillator shown in FIG. 4;
fig. 9 is a schematic block diagram of a DC-DC conversion circuit according to another embodiment of the present application;
fig. 10 is a schematic block diagram of a power supply provided in an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application. In the description of the present application, "a plurality" means two or more unless specifically stated otherwise.
In the description of the present application, it should be noted that unless otherwise specifically stated or limited, the terms "connected," "communicating," and "connected" are to be construed broadly, e.g., as meaning a fixed connection, a connection through an intervening medium, a connection between two elements, or an interaction between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as the case may be.
The terms "first," "second," and the like in the description and claims of this application and in the above-described figures, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Moreover, the terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a system, product, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other elements not expressly listed or inherent to such product or apparatus.
The description includes reference to the accompanying drawings, which form a part hereof. The figures show diagrams in accordance with exemplary embodiments. These embodiments, which may also be referred to herein as "examples," are described in sufficient detail to enable those skilled in the art to practice the embodiments of the claimed subject matter described herein. The embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the claimed subject matter. It should be appreciated that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable any person skilled in the art to practice, make, and/or use the subject matter.
First, the idea of the present application is derived by explaining the prior art to which the present application relates.
As shown in FIG. 1a, in a common peak current mode DC-DC conversion circuit, a current I is sampledSENSEAnd slope compensation current ISLOPEVia a resistance RPAfter the superposition, the input signal is input to the reverse input end of the peak current limiting circuit 11, and the input signal and the reference voltage COMP are input to the same-direction input end of the peak current limiting circuit 11, and the comparison is performed between the input signal and the reverse input end to generate a target modulation signal for controlling the connection and disconnection of the upper tube and the lower tube, so as to adjust the output ripple.
The circuit structure has the following defects:
1. under the condition of light (load) load, the minimum on-time peak current is influenced by the slope compensation current under different duty ratios.
Under light load conditions (R)LSmaller) when VCOMP(VCOMP＝(k1ISLOPE+k2ISENSE)R1，k1And k2Respectively, transimpedance amplification factor) at a constant time, at different duty cyclesSlope compensation current ISLOPEDifferent in size, so that the minimum on-time peak current iLCorresponding sampling current ISENSEThe size will vary accordingly.
2. The light-load ripple is affected by the minimum on-time peak current.
Referring to both fig. 1a and fig. 1b, during the minimum on-time, if the inductor current i flows through the inductor LLWhen the peak current reaches a value matching the reference voltage COMP, the peak current limiting circuit 11 outputs a low level, and the upper tube M is turned offP. Wherein:
the ripple on the capacitor C is:
Figure BDA0002995350970000041
in the above formula, t1Denotes the charging start time, t, of the capacitor C2Denotes the end of charge of the capacitor C, D denotes the duty cycle, T denotes the clock period, Δ ILRepresenting the inductor current, fSWRepresenting the clock frequency, ICRepresenting the charging current of the capacitor C.
Resistance RESRThe ripple on the filter is as follows:
ΔVOUT(ESR)＝ΔILRESR
therefore, the output ripple of the DC-DC conversion circuit is:
Figure BDA0002995350970000051
at a minimum on-time tonminThe inductor current at different duty cycles is:
Figure BDA0002995350970000052
at a minimum on-time tonminUnder a certain condition, the larger the duty ratio D is, the larger the inductive current Delta ILThe smaller the output ripple Δ VOUTThe smaller.
When nT in FIG. 2<t<nT + DT, DC-DC, power switch tube is opened, down tube is closed, inductive current iLIncrease, the rising slope of the inductor current is m1When nT + DT<t<nT + DT, the upper tube of the power switch tube is turned off, the lower tube is turned on, and the inductive current iLReduced inductance current falling gradient of m2。
When t is1<t<t2Time, capacitor ripple Δ VOUT(C)Increase when t is2<t<T+t1Capacitor ripple Δ VOUT(C)And decreases.
In view of the above problems, the present application provides a DC-DC conversion circuit and a power supply, which are an improvement on the existing DC-DC conversion circuit in the peak current mode to obtain a light-load high-efficiency control circuit, which can perform a PSM (pulse skipping) mode in the light-load mode, and solve the contradiction between the output ripple and the light-load high efficiency by limiting the peak current with the minimum on-time and modulating the segment frequency. Specifically, the BUCK converter is used as a main circuit structure of the light-load high-efficiency DC-DC conversion circuit, and under the light-load condition with different duty ratios, the minimum current peak value under the light-load condition can be controlled by minimum on-time peak current limitation, so that the purpose of high efficiency under the light load is achieved; the step frequency modulation can reduce light-load output ripple under the condition of light load.
The DC-DC conversion circuit provided in the present application is explained below with reference to specific embodiments.
Fig. 3 is a schematic block diagram of a DC-DC conversion circuit according to an embodiment of the present application. As shown in fig. 3, the DC-DC conversion circuit 30 includes: current sampling module 31, current limiting module 32, peak current limiting circuit 33, logic module 34, bias module 35, and oscillator slope compensation module 36. Wherein:
the logic block 34 is used for generating the oscillator signal OSC output by the oscillator ramp compensation block 36 and the peak current limit signal I output by the current limit block 32LIMITAnd the minimum current peak value signal PWM output by the peak current limiting circuit 33 outputs a segment frequency control logic signal, which is used for segment frequency modulation of different phase intervals;
the oscillator slope compensation module 36 is configured to output an oscillator signal OSC and a slope compensation current under the action of the segmented frequency control logic signal, where duty ratios of the oscillator signal OSC in different phase regions are different;
the peak current limiting circuit 33 is configured to output a minimum current peak signal PWM under the actions of the slope compensation current, the sampling current output by the current sampling module 31, and the bias current output by the bias module 35, and the peak current limiting circuit is configured to control a minimum current peak value during light load.
According to the embodiment of the application, the minimum current peak value under the light load condition is controlled through the peak current limiting circuit, so that the aim of high efficiency under the light load is fulfilled; the light-load ripple can be reduced under the light-load condition through the sectional frequency modulation of the sectional frequency control logic signal in different phase intervals, so that the low ripple is realized.
Based on the foregoing, in some embodiments, the segmented frequency control logic signal includes a first segmented frequency control logic signal, a second segmented frequency control logic signal, a third segmented frequency control logic signal, and a fourth segmented frequency control logic signal. Referring to fig. 4, oscillator slope compensation module 36 may include: first transmission gate TG1The input terminal of the oscillator slope compensation module 36 is used as a first input terminal of the oscillator slope compensation module 36, and is used for inputting a first section frequency control logic signal phi 0; first inverter INV0The input terminal of the first inverter INV is used as the second input terminal of the oscillator slope compensation module 36, and is used for inputting the second section frequency control logic signal phi 10And the output terminal of the second transmission gate TG2Is connected with the input end of the power supply; first transmission gate TG1For inputting SKIPA signal; first transmission gate TG1Second control terminal and second transmission gate TG2Is connected to the first control terminal for inputting XSKIPSignal, second transmission gate TG2Is used for inputting SKIPA signal; first transmission gate TG1And a second transmission gate TG2And a common output terminal and a first MOS transistor M0Is connected with the grid; first MOS transistor M0The source electrode of the first current mirror and the common source end of the first current mirror are used for being connected into a chipInput voltage VINFirst MOS transistor M0And a first terminal of the first current mirror (connected to the BIAS module) for receiving a first BIAS current BIAS 2; the second end of the first current mirror and the eighth MOS transistor M7Is connected to the source of (a); eighth MOS transistor M7Drain electrode of and the first capacitor C1And an operational amplifier OP1Is connected to the same phase terminal of a first capacitor C1The other end of the first and second electrodes is grounded; operational amplifier OP1Is connected with the first reference voltage V in the reverse phase terminalREF2(ii) a Operational amplifier OP1And the output end of the first MOS transistor M and the ninth MOS transistor M8Drain electrode of (1), ninth MOS tube M8Grid electrode of (1), tenth MOS tube M9The gate of (1) is connected; operational amplifier OP1The control end of the first current mirror is connected with the third end of the first current mirror; ninth MOS transistor M8Source and tenth MOS transistor M9The source of (2) is grounded; tenth MOS transistor M9Drain of (3) and thirteenth MOS tube M12Is connected to the source of (a); thirteenth MOS tube M12And the second inverter INV1Is connected to serve as a fourth input terminal of the oscillator slope compensation module 36, and is configured to input a fourth section frequency control logic signal phi 3; second inverter INV1And the output end of the eighth MOS transistor M7The gate of (1) is connected; thirteenth MOS transistor M12Drain electrode of (1), thirty-fifth MOS tube MX3Drain electrode of (1), thirty-fifth MOS tube MX3Gate of (1), thirty-sixth MOS tube MX4The gate of (1) is connected; the fifteenth MOS transistor MX3Source and thirty-sixth MOS transistor MX4Source electrode of the transistor is connected with chip input voltage VIN(ii) a Thirty-sixth MOS transistor MX4Drain electrode of (1), fourteenth MOS tube M13The drain electrode of (1), the fifteenth MOS tube M14Grid of (1), sixteenth MOS tube M15Is connected with the grid; fourth end of first current mirror, eleventh MOS pipe M10Drain electrode of (1), eleventh MOS transistor M10The grid of (1), the twelfth MOS tube M11The gate of (1) is connected; fifteenth MOS transistor M14The drain electrode of the first current mirror is connected with the fifth end of the first current mirror; eleventh MOS transistor M10Source electrode of (1) and twelfth MOS tube M11The source of (2) is grounded; twelfth MOS transistor M11Drain electrode of and fourteenth MOS tube M13OfConnecting the poles; fourteenth MOS transistor M13The gate of the second sub-band is used as a fourth input end of the oscillator slope compensation module 36, and is used for inputting a third sub-band frequency control logic signal phi 2; fifteenth MOS transistor M14Source electrode of and the second capacitor C2One end of (1), a seventeenth MOS tube M16Is connected to the non-inverting terminal of the comparator CMP1, a second capacitor C2The other end of the first switch is grounded; sixteenth MOS transistor M15Through a first resistor RY1Grounding; seventeenth MOS transistor M16Grid of (1), eighteenth MOS tube M17Grid and eighteenth MOS tube M17Drain electrode of the first current mirror, sixth end of the first current mirror, and nineteenth MOS transistor M18Is connected with the drain electrode of the transistor; seventeenth MOS transistor M16Source electrode of and eighteenth MOS tube M17The source of (2) is grounded; the inverting terminal of the comparator CMP1 (connected to the reference block) is connected to a second reference voltage VREF3The output terminal of the comparator CMP1 and the third inverter INV2Is connected to the input terminal of the third inverter INV2As a first output terminal of the oscillator slope compensation module 36, for outputting an oscillator signal OSC, and a third inverter INV2Output end of the transistor and a nineteenth MOS tube M18Is connected with the grid; sixteenth MOS transistor M15The drain of the first current mirror is connected with the first end of the second current mirror; common source of the second current mirror is connected with chip input voltage VIN(ii) a A second terminal of the second current mirror is used as a second output terminal of the oscillator slope compensation module 36 for outputting the first slope compensation current ISLOPE1(ii) a The third terminal of the second current mirror is used as the third output terminal of the oscillator slope compensation module 36 for outputting the second slope compensation current ISLOPE2(ii) a The fourth terminal of the second current mirror is used as the fourth output terminal of the oscillator slope compensation module 36 for outputting the third slope compensation current ISLOPE3。
In the oscillator slope compensation module 36, ENOSC is the first segment frequency control logic signal phi0And a second section frequency control logic signal phi1The strobe signal of (1).
Optionally, the first current mirror is a cascode current mirror. As shown in fig. 4, the first current mirror may include a second MOS transistor M1The first stepThree MOS tube M2And a fourth MOS transistor M3The fifth MOS transistor M4And a sixth MOS transistor M5And a seventh MOS transistor M6. Wherein, the second MOS transistor M1Drain electrode of the second MOS transistor M1Grid of (1), third MOS tube M2Grid of (1), fourth MOS tube M3Grid of (1), fifth MOS tube M4Grid of (1), sixth MOS tube M5Grid of (1), seventh MOS tube M6As a first terminal of the first current mirror; second MOS transistor M1Source electrode of (3), third MOS tube M2Source electrode of and fourth MOS tube M3Source electrode of the fifth MOS transistor M4Source electrode of (1), sixth MOS tube M5Source electrode of (1), seventh MOS tube M6Is connected as a common source terminal of the first current mirror; third MOS transistor M2The drain of the first current mirror is used as a second end of the first current mirror; fourth MOS transistor M3The drain electrode of the first current mirror is used as a third end of the first current mirror; fifth MOS transistor M4The drain of the first current mirror is used as the fourth end of the first current mirror; sixth MOS transistor M5The drain of which is used as the fifth end of the first current mirror; seventh MOS transistor M6As the sixth terminal of the first current mirror.
In some embodiments, the second current mirror is a cascode current mirror. As shown in fig. 4, the second current mirror may include: twentieth MOS transistor M19Twenty-first MOS transistor M20Twenty-second MOS transistor M21And a twenty-third MOS transistor M22. Wherein: twentieth MOS transistor M19Source electrode of the transistor, twenty-first MOS transistor M20Source electrode of the transistor, twenty-second MOS tube M21Source electrode of the transistor M, and a twenty-third MOS transistor M22Is connected as the common source terminal of the second current mirror; twentieth MOS transistor M19Drain electrode of the twentieth MOS transistor M19Grid and twenty-first MOS transistor M20Grid and twenty-second MOS tube M21Gate of (1), twenty-third MOS tube M22As a first terminal of the second current mirror; twenty-first MOS transistor M20The drain of the first current mirror is used as a second end of the second current mirror; second twelve MOS transistor M21The drain of the first current mirror is used as a third end of the second current mirror; twenty-third MOS tube M22As a fourth of the second current mirrorAnd (4) end.
In addition, the eleventh MOS transistor M10And a twelfth MOS transistor M11Forming a current mirror, a seventeenth MOS transistor M16And eighteenth MOS tube M17A current mirror is constructed.
As a possible implementation, referring to fig. 5, the logic module 34 may include: a first count logic unit 341, a second count logic unit 342, and a flip-flop unit 343. Wherein the content of the first and second substances,
the first input terminal of the first count logic unit 341 is used for inputting the minimum current peak signal PWM, and the second input terminal of the first count logic unit 341 is used for inputting the peak current limit signal ILIMITA third input end of the first counting logic unit 341 is configured to input an oscillator signal OSC, an output end of the first counting logic unit 341 is connected to an input end of the flip-flop unit 343, and the first counting logic unit 341 is configured to perform frequency division processing on an input signal to obtain a signal opposite to the fifth segment frequency control logic signal Φ a and output the signal to the flip-flop unit 343; the flip-flop unit 343 is configured to perform logic processing on the input signal and output a fifth segment frequency control logic signal phiAAnd the sixth sectional frequency control logic signal phiBSeventh section frequency control logic signal phiCAnd the eighth segment frequency control logic signal phiD(ii) a The second count logic unit 342 is used for controlling the logic signal phi in the fifth segment frequencyAAnd the sixth segment frequency control logic signal phiBSeventh section frequency control logic signal phiCAnd the eighth segment frequency control logic signal phiDUnder the action of the control signal, the segmented frequency control logic signal is output. The segmented frequency control logic signal is input to an oscillator ramp compensation module for controlling the clock frequency. Wherein the segmented frequency control logic signal may include: the first section frequency control logic signal phi 0, the second section frequency control logic signal phi 1, the third section frequency control logic signal phi 2 and the fourth section frequency control logic signal phi 3.
Alternatively, as shown in fig. 5, the flip-flop unit 343 may include a first nand gate 51, a second nand gate 52, a third nand gate 53, a fourth nand gate 54, and a fifth nand gate 54Inverter 55, sixth inverter 56, seventh inverter 57, eighth inverter 58, ninth inverter 59, and 9D flip-flops, respectively identified as: first D flip-flop 0, second D flip-flop 1, … …, ninth D flip-flop 8. Wherein, the input terminal of the fifth inverter 55 and the trigger terminal D of the first D flip-flop 00Connected as a first input of flip-flop cell 343; an output end of the fifth inverter 55 is connected to a first input end of the first nand gate 51, a second input end of the first nand gate 51 is used for inputting an ENABLE signal ENABLE, an output end of the first nand gate 51 is connected to an input end of the sixth inverter 56, an output end of the sixth inverter 56 is used as a first output end of the flip-flop unit 343, and is configured to output the fifth section frequency control logic signal phiA(ii) a In-phase output Q of first D flip-flop 00A first input terminal of the second NAND gate 52 and a trigger terminal D of the second D flip-flop 11Connecting; non-inverting output Q of second D flip-flop 11A first input terminal of the third nand gate 53 and a trigger terminal D of the third D flip-flop 22Connecting; inverted output XQ of second D flip-flop 11The output end of the second nand gate 52 is connected to the input end of the seventh inverter 57, and the output end of the seventh inverter 57 is used as the second output end of the flip-flop unit 343 and is configured to output the sixth section frequency control logic signal phiB(ii) a In-phase output Q of third D flip-flop 22A first input terminal of the fourth nand gate 54 and a trigger terminal D of the fourth D flip-flop 33Connecting; inverted output XQ of third D flip-flop 22The output end of the third nand gate 53 is connected to the input end of the eighth inverter 58, and the output end of the eighth inverter 58 is used as the third output end of the flip-flop unit 343 and is configured to output the seventh section frequency control logic signal phiC(ii) a Inverted output terminal XQ of fourth D flip-flop 33The output end of the fourth nand gate 54 is connected to the input end of the ninth inverter 59, and the output end of the ninth inverter 59 is used as the fourth output end of the flip-flop unit 343 and is configured to output the eighth section frequency control logic signal phiD(ii) a First D flip-flop 0 clockA clock terminal CLK, a clock terminal CLK of the second D flip-flop 1, a clock terminal CLK of the third D flip-flop 2, a clock terminal CLK of the fourth D flip-flop 3, and an inverted output terminal XQ of the ninth D flip-flop 88And a trigger end D of a ninth D trigger 88And the in-phase output end Q of the eighth D trigger 77Connecting; clock terminal CLK of ninth D flip-flop 8, inverted output XQ of eighth D flip-flop 77Trigger end D of eighth D trigger 77And a non-inverting output end Q of a seventh D flip-flop 66Connecting; the clock terminal CLK of the eighth D flip-flop 7, the inverted output XQ of the seventh D flip-flop 66Trigger end D of seventh D trigger 66And a same-phase output end Q of a sixth D trigger 55Connecting; the clock terminal CLK of the seventh D flip-flop 6, the inverted output terminal XQ of the sixth D flip-flop 55And a trigger end D of a sixth D trigger 55And a non-inverting output end Q of a fifth D flip-flop 44Connecting; the clock terminal CLK of the sixth D flip-flop 5, the inverted output XQ of the fifth D flip-flop 44Trigger end D of the fifth D trigger 44Connecting; the clock terminal CLK of the fifth D flip-flop 4 is used as a second input terminal of the flip-flop cell 343, and is connected to a third input terminal of the first counting logic unit 341.
Wherein the fifth D flip-flop 4, the sixth D flip-flop 5, the seventh D flip-flop 6, the eighth D flip-flop 7 and the ninth D flip-flop 8 constitute a frequency divider to which the oscillator signal OSC is input, the output of which frequency divider (i.e. the XQ of the ninth D flip-flop 8)8End) is connected with the input end of the shift register (i.e. the CLK end of the first D flip-flop 0, the second D flip-flop 1, the third D flip-flop 2 and the fourth D flip-flop 3), wherein the first D flip-flop 0, the second D flip-flop 1, the third D flip-flop 2 and the fourth D flip-flop 3 form the shift register and pass through the in-phase output end Q of the shift register respectively0In-phase output terminal Q1In-phase output terminal Q2And an inverted output terminal XQ2And an inverted output XQ3The output signal is processed by logic to output a fifth segment frequency control logic signal phiAAnd the sixth segment frequency control logic signal phiBSeventh section frequency control logic signal phiCAnd the eighth segment frequency control logic signal phiD。
For example, fig. 6 shows that the fifth-segment frequency control logic signal phi in a single signal periodAAnd the sixth sectional frequency control logic signal phiBThe seventh segment frequency control logic signal phiCAnd the eighth segment frequency control logic signal phiDSchematic diagram of waveforms.
It should be noted that, in the embodiment of the present application, the number of flip-flops included in the flip-flop unit 343 is not limited, and the embodiment of the present application does not limit the type of the flip-flop, and fig. 5 only takes a D flip-flop as an example for description, and specifically, the type of the flip-flop and the increase or decrease of the number of the flip-flops may be set according to actual requirements.
Further, referring to fig. 7, the peak current limiting circuit 33 may include:
a summing circuit 331 for summing the input first bias current IDC1First slope compensation current ISLOPE1A second bias current IDC2A second sampling current ISENSE2A second slope compensation current ISLOPE2Performs a summing process to output a first voltage V via a first output terminal of the summing circuit 331SIGMA1A second voltage V is output through a second output terminal of the summing circuit 331SIGMA2；
Twenty-fourth MOS transistor M24Grid and twenty-fourth MOS tube M24The drain electrode of the transistor M, a twenty-fifth MOS transistor M25For switching in a second BIAS current BIAS1 (from the BIAS module);
twenty-fourth MOS transistor M24Source electrode of the transistor, twenty-fifth MOS transistor M25Source electrode of the transistor M, twenty sixth MOS transistor M26Source electrode of the transistor M and a twenty-seventh MOS transistor M27Source electrode of the transistor is connected with chip input voltage VIN；
Twenty-sixth MOS transistor M26The drain electrode of the transistor M, a twenty sixth MOS transistor M26Grid and twenty-seventh MOS tube M27The gate of (1) is connected;
twenty-fifth MOS transistor M25Drain electrode of (1), twenty-eighth MOS tube M28Source electrode of and twenty-ninth MOS transistor M29Is connected to the source of (a);
eighteenth MOS tube M28The grid electrode of the transistor is connected with a reference voltage COMP and a twenty-eight MOS tube M28Drain of (1) and thirtieth MOS tube M30Is connected with the source electrode of the transistor;
twenty-ninth MOS transistor M29Is connected to a second output of the summing circuit 331;
thirtieth MOS transistor M30Is connected to a first output of the summing circuit 331;
thirtieth MOS transistor M30Drain electrode of (1), and a thirty-first MOS tube M31Drain electrode of (1), and a thirty-first MOS tube M31Gate of (1), thirty-second MOS transistor M32The gate of (1) is connected;
the third twelve MOS transistors M32Drain electrode of (1) and twenty-sixth MOS transistor M26Is connected with the drain electrode of the transistor;
twenty-ninth MOS transistor M29Drain electrode of (1), thirty-third MOS tube M33Drain electrode of (1), thirty-third MOS tube M33Gate of (1) and thirty-fourth MOS transistor M34The gate of (1) is connected;
thirty-one MOS transistor M31Source electrode of (1), thirty-second MOS tube M32Source electrode of (1), thirty-third MOS tube M33Source electrode of (1), thirty-fourth MOS tube M34The source of (2) is grounded;
thirty-fourth MOS transistor M34And twenty-seventh MOS tube M27Common drain electrode, and fourth inverter INV3Is connected to the input end of the fourth inverter INV3As the output of the peak current limiting circuit 33.
In the peak current limiting circuit 33, a twenty-four MOS transistor M24And twenty-fifth MOS transistor M25Form a current mirror, a thirty-first MOS transistor M31And thirty-second MOS transistor M32Form a current mirror, a twenty-sixth MOS transistor M26And twenty-seventh MOS tube M27Constituting a current mirror, a thirty-third MOS transistor M33And a thirty-fourth MOS transistor M34Constituting a current mirror.
The above examples illustrate specific structures of the modules, and next, the operation principle of each module is described.
For the oscillator slope compensation module 36 shown in fig. 4, with simultaneous reference to fig. 6 and 8, the operating principle is as follows:
(1)“фAfor a period of 1 ″, the DC-DC converter circuit enters a periodic switching mode, SKIPThe signal is '0', ENOSC gating phi0，ф0＝“1”，ф1＝“0”，ф2＝“0”,ф3When equal to "0", oscillator slope compensation module 36 normally generates a clock signal, IC2Is a second capacitor C2A first bias current IBIAS2Is the current generated by the bias module, T is the clock period, fswIs the clock frequency, the second reference voltage VREF3Is a reference voltage generated by a reference module, ICH:IBIAS2＝k 91, wherein:
ICH＝k9IBIAS2
IC2＝ICH＝k9IBIAS2
IC2T＝C2VREF3
Figure BDA0002995350970000121
(2)“фB1' period, the DC-DC conversion circuit enters a sleep mode of operation, SKIPThe signal is '1', ENOSC gating phi1，ф0＝“1”，ф1＝“1”，ф2＝“0”，ф3When "0", oscillator ramp compensation module 36 turns off oscillator signal OSC. At this time, fsw＝0。
(3)“фCThe DC-DC conversion circuit exits the sleep mode of operation S for a period of 1 ″KIPThe signal is '0', ENOSC gating phi0，ф0＝“1”，ф1＝“0”，ф2＝“1”,ф3When equal to "0", the oscillator slope compensation module 36 reduces the clock frequency fsw，IFOLDIs the current that is down converted.
IFOLD::IBIAS2＝k 8:1
ICH＝k9IBIAS2
IFLOD＝k8IBIAS2
IC2＝ICH-IFOLD＝k9IBIAS2-k8IBIAS2
Figure BDA0002995350970000122
(4)“ф D1 "period, SKIPThe signal is '0', and ENOSC gating phi0，ф0＝“1”，ф1＝“0”，ф2＝“1”，ф3＝“1”，gmIs an operational amplifier OP1Transconductance of, VC1Is a first capacitor C1Upper capacitor when the fourth segment frequency controls the logic signal phi3When changing from "0" to "1", the first capacitance C1Starting to charge the first capacitor C1Voltage V onC1Gradually increases from 0 when VC1≥VREF2At the end of the down-conversion process, the clock frequency fswAnd (6) linear recovery. Wherein, IgmIs the clock frequency fswAnd (3) recovering the gradual current:
Igm＝IM8＝gm(VC1-VREF2)
IC2＝ICH+Igm-IFOLD＝k9IBIAS2+gm(VC1-VREF2)-k8IBIAS2
Figure BDA0002995350970000131
as described above, oscillator slope compensation module 36 is divided into four phase periods: phiA1' time interval, the oscillator is continuously switched on and off; phi B1 "period, oscillator sleep phase; phiC1' time interval, oscillator frequency reduction stage; phi D1 "time period, vibrationAnd an oscillator linear recovery stage.
For the peak current limiting circuit 33 as shown in fig. 7, the operation principle is as follows:
a first bias current IDC1And a first slope compensation current ISLOPE1The voltage is input to a summing circuit 331 for summing to obtain a first voltage VSIGMA1(ii) a Second bias current IDC2A second sampling current ISENSE2The second slope compensation current ISLOPE2The voltage is input to a summing circuit 331 for summing to obtain a second voltage VSIGMA2. Wherein k is1、k2、k3、k4、k5、k6Respectively, transimpedance amplification factor:
VSIGMA1＝k1IDC1+k2ISLOPE1+k3IREF1
VSIGMA2＝k4IDC2+k5ISLOPE2+k6ISENSE2
when V isSIGMA1>COMP time, VSIGMA1And VSIGMA2And comparing and outputting a minimum current peak value signal PWM. At this time, k1IDC1+k2ISLOPE1+k3IREF1＝k4IDC2+k5ISLOPE2+k6ISENSE2。
By a summing circuit 331 so that k1IDC1+k2ISLOPE1＝k4IDC2+k5ISLOPE2Then:
Figure BDA0002995350970000132
inductor current iLAnd a second sampling current ISENSE2Has a sampling ratio of A1:1, minimum on-time inductor current iLHas a peak value of ILMIN，
Figure BDA0002995350970000133
Therefore, the minimum peak value of the inductor current under the light load condition can be made not to be affected by the slope compensation current by the peak current limiting circuit 33.
When V isSIGMA1<COMP, COMP and VSIGMA2And comparing and outputting a minimum current peak value signal PWM.
Fig. 9 is a schematic block diagram of a DC-DC conversion circuit according to another embodiment of the present application. As shown in fig. 9, the DC-DC conversion circuit 90 may further include, on the basis of the structure shown in fig. 3: upper pipe MPALower tube MNAAn enable module 37, a reference module 38, an error amplifier module 39, and a drive module 40. Wherein:
the enable module 37 is configured to generate a first enable signal ENB and a second enable signal ENO according to a signal input by an enable terminal (i.e., an enable pin) EN, output the first enable signal ENB to the bias module 35, and output the second enable signal ENO to the oscillator slope compensation module 36. The bias module 35 is configured to output a first bias current I under the action of the first enable signal ENBDC1And a second bias current IDC2To the peak current limiting circuit 33. The oscillator slope compensation module 36 is further configured to output a first slope compensation current I under the action of the second enable signal ENOSLOPE1And a second slope compensation current ISLOPE2To the peak current limiting circuit 33. Reference module 38 is used to provide a reference voltage, e.g., a first reference voltage VREF2A second reference voltage VREF3. Error amplifier module 39 is used to generate a reference voltage VREFAnd the feedback voltage signal FB, outputs an error amplification signal (reference voltage) COMP to the peak current limiting circuit 33. The logic module 34 is also used to limit the signal I at peak currentLIMITAnd outputting an upper tube driving logic signal LOGICP and a lower tube driving logic signal LOGICN under the action of the minimum current peak value signal PWM. The driving module 40 is used for outputting a top-tube driving signal DRVP and a bottom-tube driving signal DRVN under the actions of the top-tube driving logic signal logic and the bottom-tube driving logic signal logic, the top-tube driving signal DRVP is used for controlling the top-tube MPATurn on and off, lower tube driveSignal DRVN is used to control lower tube MNAOn and off.
In addition, the upper pipe MPAAnd a lower pipe MNAOne end of the common leakage outputs a voltage value LX which passes through a sampling tube MPAS1And a sampling tube MPAS2Output signal LXSSignal LXSIs input into the current sampling module 31, so that the current sampling module 31 outputs a first sampled current ISENSE1And a second sampling current ISENSE2(ii) a The undervoltage detection signal UVLO from the undervoltage detection module 41, the overvoltage protection signal OVP from the overvoltage protection module 42, and the zero current detection signal IZL from the zero current detection module 43 are also input to the logic module 34, and the functions thereof are similar to those of the related art, and are not described herein again.
Note that the DC-DC conversion circuit 90 is a BUCK DC-DC conversion circuit.
In summary, the DC-DC conversion circuit provided by the present application has at least the following advantages:
1. the light-load high-efficiency low ripple realizes the minimum output ripple under different duty ratios;
2. the minimum on-time does not vary with the duty cycle;
3. the frequency segmented modulation widens the minimum duty ratio and reduces output ripples;
4. and the transition load points from the light load DCM to the heavy load CCM are distributed in a concentrated manner.
Fig. 10 is a schematic block diagram of a power supply provided in an embodiment of the present application. As shown in fig. 10, the power supply 100 includes: a filter circuit 110, a load 120 and a DC-DC conversion circuit 130 as described in any of the embodiments above. The DC-DC converter circuit 130 is connected to the load 120 via the filter circuit 110.
Optionally, the power supply 100 further comprises: and an external power supply source (not shown) of the DC-DC conversion circuit 130.
It should be noted that the division of the modules of the above apparatus is only a logical division, and the actual implementation may be wholly or partially integrated into one physical entity, or may be physically separated. And these modules can all be implemented in the form of software invoked by a processing element; or may be implemented entirely in hardware; and part of the modules can be realized in the form of calling software by the processing element, and part of the modules can be realized in the form of hardware. For example, the processing module may be a processing element separately set up, or may be implemented by being integrated in a chip of the apparatus, or may be stored in a memory of the apparatus in the form of program code, and a function of the processing module may be called and executed by a processing element of the apparatus. Other modules are implemented similarly. In addition, all or part of the modules can be integrated together or can be independently realized. The processing element here may be an integrated circuit with signal processing capabilities. In implementation, each step of the above method or each module above may be implemented by an integrated logic circuit of hardware in a processor element or an instruction in the form of software.
While only certain components and embodiments of the present application have been illustrated and described, many modifications and changes may occur to those skilled in the art (e.g., variations in sizes, dimensions, structures, shapes and proportions of the various elements, mounting arrangements, use of materials, colors, orientations, etc.) without materially departing from the scope and spirit of the invention in the claims. Moreover, in an effort to provide a concise description of the exemplary embodiments, all features of an actual implementation may not have been described. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions may be made. Such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure, without undue experimentation.
It is to be understood that the various numerical references referred to in the embodiments of the present application are merely for descriptive convenience and are not intended to limit the scope of the embodiments of the present application. In the embodiment of the present application, the sequence numbers of the above-mentioned processes do not mean the sequence of execution, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiment of the present application.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims (10)

1. A DC-DC conversion circuit, comprising: current sampling module, current limit module, peak current limit circuit, logic module, biasing module and oscillator slope compensation module, wherein:
the logic module is used for outputting a segmented frequency control logic signal under the action of an oscillator signal output by the oscillator slope compensation module, a peak current limiting signal output by the current limiting module and a minimum current peak signal output by the peak current limiting circuit, and the segmented frequency control logic signal is used for segmented frequency modulation of different phase intervals;
the oscillator slope compensation module is used for outputting the oscillator signal and slope compensation current under the action of the segmented frequency control logic signal, and the duty ratios of the oscillator signal in different phase regions are different;
the peak current limiting circuit is used for outputting the minimum current peak value signal under the action of the slope compensation current, the sampling current output by the current sampling module and the bias current output by the bias module, and the peak current limiting circuit is used for controlling the minimum current peak value during light load.
2. The DC-DC conversion circuit of claim 1, wherein the segmented frequency control logic signal comprises a first segmented frequency control logic signal, a second segmented frequency control logic signal, a third segmented frequency control logic signal, and a fourth segmented frequency control logic signal, and wherein the oscillator slope compensation module comprises:
the input end of the first transmission is used as the first input end of the oscillator slope compensation module and is used for inputting a first section frequency control logic signal;
the input end of the first inverter is used as the second input end of the oscillator slope compensation module and is used for inputting a second segmented frequency control logic signal, and the output end of the first inverter is connected with the input end of the second transmission gate;
a first control terminal of the first transmission gate for inputting SKIPA signal; the second control end of the first transmission gate is connected with the first control end of the second transmission gate and used for inputting XSKIPA second control terminal of the second transmission gate is used for inputting SKIPA signal; the common output end of the first transmission gate and the second transmission gate is connected with the grid electrode of the first MOS tube;
the source electrode of the first MOS tube and the common source end of the first current mirror are used for accessing a chip input voltage, and the drain electrode of the first MOS tube and the first end of the first current mirror are used for accessing a first bias current;
the second end of the first current mirror is connected with the source electrode of the eighth MOS tube;
the drain electrode of the eighth MOS tube is connected with one end of the first capacitor and the in-phase end of the operational amplifier, and the other end of the first capacitor is grounded;
the inverting terminal of the operational amplifier is connected with a first reference voltage;
the output end of the operational amplifier is connected with the drain electrode of a ninth MOS tube, the grid electrode of the ninth MOS tube and the grid electrode of a tenth MOS tube;
the control end of the operational amplifier is connected with the third end of the first current mirror;
the source electrode of the ninth MOS tube and the source electrode of the tenth MOS tube are grounded;
the drain electrode of the tenth MOS tube is connected with the source electrode of the thirteenth MOS tube;
the grid electrode of the thirteenth MOS tube is connected with the input end of the second phase inverter, and the grid electrode of the thirteenth MOS tube is used as the fourth input end of the oscillator slope compensation module and used for inputting a fourth segment frequency control logic signal;
the output end of the second phase inverter is connected with the grid electrode of the eighth MOS tube;
the drain electrode of the thirteenth MOS tube, the drain electrode of the thirty-fifth MOS tube, the gate electrode of the thirty-fifth MOS tube and the gate electrode of the thirty-sixth MOS tube are connected;
the source electrode of the thirty-fifth MOS tube and the source electrode of the thirty-sixth MOS tube are connected with a chip input voltage;
the drain electrode of the thirty-sixth MOS tube, the drain electrode of the fourteenth MOS tube, the grid electrode of the fifteenth MOS tube and the grid electrode of the sixteenth MOS tube are connected;
the fourth end of the first current mirror, the drain electrode of the eleventh MOS tube, the grid electrode of the eleventh MOS tube and the grid electrode of the twelfth MOS tube are connected;
a fifth end of the first current mirror is connected with a drain electrode of the fifteenth MOS tube;
the source electrode of the eleventh MOS tube and the source electrode of the twelfth MOS tube are grounded;
the drain electrode of the twelfth MOS tube is connected with the source electrode of the fourteenth MOS tube;
a grid electrode of the fourteenth MOS tube is used as a third input end of the oscillator slope compensation module and is used for inputting a third segment frequency control logic signal;
the source electrode of the fifteenth MOS tube is connected with one end of a second capacitor, the drain electrode of the seventeenth MOS tube and the in-phase end of the comparator, and the other end of the second capacitor is grounded;
the source electrode of the sixteenth MOS tube is grounded through a first resistor;
the grid electrode of the seventeenth MOS tube, the grid electrode of the eighteenth MOS tube, the drain electrode of the eighteenth MOS tube, the sixth end of the first current mirror and the drain electrode of the nineteenth MOS tube are connected;
the source electrode of the seventeenth MOS tube, the source electrode of the eighteenth MOS tube and the source electrode of the nineteenth MOS tube are grounded;
the inverting terminal of the comparator is connected with a second reference voltage, the output terminal of the comparator is connected with the input terminal of a third inverter, the output terminal of the third inverter is used as the first output terminal of the oscillator slope compensation module and is used for outputting the oscillator signal, and the output terminal of the third inverter is connected with the gate of the nineteenth MOS transistor;
the drain electrode of the sixteenth MOS tube is connected with the first end of the second current mirror;
a common source of the second current mirror is connected with the chip input voltage;
a second end of the second current mirror is used as a second output end of the oscillator slope compensation module and used for outputting a first slope compensation current;
a third end of the second current mirror is used as a third output end of the oscillator slope compensation module and is used for outputting a second slope compensation current;
and the fourth end of the second current mirror is used as the fourth output end of the oscillator slope compensation module and used for outputting a third slope compensation current.
3. The DC-DC conversion circuit of claim 2, wherein the first current mirror comprises a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor, wherein:
the drain electrode of the second MOS tube, the grid electrode of the third MOS tube, the grid electrode of the fourth MOS tube, the grid electrode of the fifth MOS tube, the grid electrode of the sixth MOS tube and the grid electrode of the seventh MOS tube are connected and used as the first end of the first current mirror;
the source electrode of the second MOS tube, the source electrode of the third MOS tube, the source electrode of the fourth MOS tube, the source electrode of the fifth MOS tube, the source electrode of the sixth MOS tube and the source electrode of the seventh MOS tube are connected and used as a common source end of the first current mirror;
the drain electrode of the third MOS tube is used as the second end of the first current mirror;
the drain electrode of the fourth MOS tube is used as a third end of the first current mirror;
the drain electrode of the fifth MOS tube is used as the fourth end of the first current mirror;
the drain electrode of the sixth MOS tube is used as the fifth end of the first current mirror;
and the drain electrode of the seventh MOS tube is used as the sixth end of the first current mirror.
4. The DC-DC conversion circuit of claim 2, wherein the second current mirror comprises: twentieth MOS pipe, twenty-first MOS pipe, twenty-second MOS pipe and twenty-third MOS pipe, wherein:
the source electrode of the twentieth MOS transistor, the source electrode of the twenty-first MOS transistor, the source electrode of the twenty-second MOS transistor and the source electrode of the twenty-third MOS transistor are connected and serve as common source ends of the second current mirror;
the drain electrode of the twentieth MOS transistor, the grid electrode of the twenty-first MOS transistor, the grid electrode of the twenty-second MOS transistor and the grid electrode of the twenty-third MOS transistor are connected and serve as the first end of the second current mirror;
the drain electrode of the twenty-first MOS transistor is used as the second end of the second current mirror;
the drain electrode of the second twelfth MOS tube is used as the third end of the second current mirror;
and the drain electrode of the twenty-third MOS tube is used as the fourth end of the second current mirror.
5. The DC-DC conversion circuit of claim 1, wherein the logic module comprises:
a first counting logic unit, a first input end of which is used for inputting the minimum current peak signal, a second input end of which is used for inputting the peak current limiting signal, a third input end of which is used for inputting the oscillator signal, an output end of which is connected with an input end of a trigger unit, and which is used for performing frequency division processing on the input signal to obtain a signal opposite to a fifth-segment frequency control logic signal and outputting the signal to the trigger unit;
the trigger unit is used for carrying out logic processing on the input signals and outputting a fifth section frequency control logic signal, a sixth section frequency control logic signal, a seventh section frequency control logic signal and an eighth section frequency control logic signal;
and the second counting logic unit is used for outputting the segmented frequency control logic signal under the action of a fifth segmented frequency control logic signal, a sixth segmented frequency control logic signal, a seventh segmented frequency control logic signal and an eighth segmented frequency control logic signal.
6. The DC-DC conversion circuit according to claim 5, wherein the flip-flop unit comprises: a first nand gate, a second nand gate, a third nand gate, a fourth nand gate, a fifth inverter, a sixth inverter, a seventh inverter, an eighth inverter, a ninth inverter, and a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a fifth D flip-flop, a sixth D flip-flop, a seventh D flip-flop, an eighth D flip-flop, and a ninth D flip-flop, wherein:
the input end of the fifth inverter is connected with the trigger end of the first D flip-flop and is used as the first input end of the flip-flop unit; the output end of the fifth inverter is connected to the first input end of the first nand gate, the second input end of the first nand gate is used for inputting an enable signal, the output end of the first nand gate is connected to the input end of the sixth inverter, and the output end of the sixth inverter is used as the first output end of the flip-flop unit and is used for outputting a fifth segment frequency control logic signal;
the non-inverting output end of the first D flip-flop and the first input end of the second NAND gate are connected with the trigger end of the second D flip-flop; the in-phase output end of the second D flip-flop and the first input end of the third NAND gate are connected with the trigger end of the third D flip-flop; an inverting output end of the second D flip-flop is connected to a second input end of the second nand gate, an output end of the second nand gate is connected to an input end of the seventh inverter, and an output end of the seventh inverter serves as a second output end of the flip-flop unit, and is configured to output a sixth segmented frequency control logic signal;
the non-inverting output end of the third D flip-flop and the first input end of the fourth NAND gate are connected with the trigger end of the fourth D flip-flop; the inverting output end of the third D flip-flop is connected to the second input end of the third nand gate, the output end of the third nand gate is connected to the input end of the eighth inverter, and the output end of the eighth inverter is used as the third output end of the flip-flop unit and is configured to output a seventh segmented frequency control logic signal;
an inverting output end of the fourth D flip-flop is connected to a second input end of the fourth nand gate, an output end of the fourth nand gate is connected to an input end of the ninth inverter, and an output end of the ninth inverter serves as a fourth output end of the flip-flop unit, and is configured to output an eighth segmented frequency control logic signal;
a clock end of the first D flip-flop, a clock end of the second D flip-flop, a clock end of the third D flip-flop, a clock end of the fourth D flip-flop, an inverted output end of the ninth D flip-flop, a trigger end of the ninth D flip-flop, and an in-phase output end of the eighth D flip-flop are connected;
the clock end of the ninth D flip-flop, the inverted output end of the eighth D flip-flop, the trigger end of the eighth D flip-flop and the in-phase output end of the seventh D flip-flop are connected;
the clock end of the eighth D flip-flop, the inverted output end of the seventh D flip-flop, the trigger end of the seventh D flip-flop and the in-phase output end of the sixth D flip-flop are connected;
a clock end of the seventh D flip-flop, an inverted output end of the sixth D flip-flop, a trigger end of the sixth D flip-flop, and an in-phase output end of the fifth D flip-flop are connected; the clock end of the sixth D trigger and the inverted output end of the fifth D trigger are connected with the trigger end of the fifth D trigger;
and the clock end of the fifth D trigger is used as the second input end of the trigger unit and is connected with the third input end of the first counting logic unit.
7. The DC-DC conversion circuit according to claim 1, wherein the peak current limiting circuit comprises:
the summing circuit is used for summing the input first bias current, the first slope compensation current, the second bias current, the second sampling current and the second slope compensation current, outputting a first voltage through a first output end and outputting a second voltage through a second output end;
the grid electrode of the twenty-fourth MOS tube, the drain electrode of the twenty-fourth MOS tube and the grid electrode of the twenty-fifth MOS tube are connected and used for connecting a second bias current;
the source electrode of the twenty-fourth MOS tube, the source electrode of the twenty-fifth MOS tube, the source electrode of the twenty-sixth MOS tube and the source electrode of the twenty-seventh MOS tube are connected with a chip input voltage;
the drain electrode of the twenty-sixth MOS tube, the grid electrode of the twenty-sixth MOS tube and the grid electrode of the twenty-seventh MOS tube are connected;
the drain electrode of the twenty-fifth MOS transistor, the source electrode of the twenty-eighth MOS transistor and the source electrode of the twenty-ninth MOS transistor are connected;
the grid electrode of the twenty-eighth MOS tube is connected with a reference voltage, and the drain electrode of the twenty-eighth MOS tube is connected with the source electrode of the thirty-eighth MOS tube;
the grid electrode of the twenty-ninth MOS tube is connected with the second output end of the summing circuit;
the gate of the thirtieth MOS tube is connected with the first output end of the summing circuit;
the drain electrode of the thirty-first MOS tube, the grid electrode of the thirty-first MOS tube and the grid electrode of the thirty-second MOS tube are connected;
the drain electrode of the thirty-second MOS transistor is connected with the drain electrode of the twenty-sixth MOS transistor;
the drain electrode of the twenty-ninth MOS transistor, the drain electrode of the thirty-third MOS transistor, the gate electrode of the thirty-third MOS transistor and the gate electrode of the thirty-fourth MOS transistor are connected;
a source electrode of the thirty-first MOS transistor, a source electrode of the thirty-second MOS transistor, a source electrode of the thirty-third MOS transistor and a source electrode of the thirty-fourth MOS transistor are grounded;
and the thirty-fourth MOS transistor and the twenty-seventh MOS transistor share a drain electrode and are connected with the input end of a fourth phase inverter, and the output end of the fourth phase inverter is used as the output end of the peak current limiting circuit.
8. The DC-DC conversion circuit according to any one of claims 1 to 7, further comprising: upper tube, low tube, enable module, benchmark module, error amplifier module, comparison module and drive module, wherein:
the enabling module is used for generating a first enabling signal and a second enabling signal according to a signal input by an enabling end, outputting the first enabling signal to the biasing module, and outputting the second enabling signal to the oscillator slope compensation module;
the bias module is used for outputting a first bias current and a second bias current to the peak current limiting circuit under the action of the first enabling signal;
the oscillator slope compensation module is further configured to output a first slope compensation current and a second slope compensation current to the peak current limiting circuit under the action of the second enable signal;
the reference module is used for providing a reference voltage;
the error amplifier module is used for outputting an error amplification signal to the peak current limiting circuit under the action of the reference voltage and the feedback voltage signal;
the logic module is further configured to output an upper tube driving logic signal and a lower tube driving logic signal under the action of the peak current limiting signal and the minimum current peak signal;
the driving module is used for outputting an upper tube driving signal and a lower tube driving signal under the action of the upper tube driving logic signal and the lower tube driving logic signal, the upper tube driving signal is used for controlling the connection and disconnection of an upper tube, and the lower tube driving signal is used for controlling the connection and disconnection of a lower tube.
9. A power supply, comprising: a filter circuit, a load and a DC-DC conversion circuit according to any one of claims 1 to 8, wherein the DC-DC conversion circuit is connected to the load via the filter circuit.
10. The power supply of claim 9, further comprising: and an external power supply source for the DC-DC conversion circuit.
CN202110328037.7A 2021-03-26 2021-03-26 DC-DC conversion circuit and power supply Active CN112953224B (en)

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