CN112953197B - Power supply device - Google Patents

Abstract

The invention provides a power supply device, which is provided with an enable terminal capable of externally connecting LDOs arranged outside the power supply device, and the starting and stopping control of the LDOs is performed by an enable signal output from the enable terminal.

Description

Power supply device

Technical Field

The present invention relates to a power supply device.

Background

A power supply circuit called LDO (Low Drop Out Low dropout) is currently known. LDOs are linear regulators that can operate even with a low inter-input-output potential difference.

Further, a PMIC (power management IC) including a plurality of DC/DC converters is known, and LDOs are incorporated in some PMICs. The output voltage of the LDO is supplied to a load such as a sensor disposed outside the PMIC.

However, if the LDO is incorporated in the PMIC, the wiring length between the LDO and the load such as the sensor becomes long. This increases the impedance of the wiring, and is susceptible to external noise.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a power supply device capable of effectively realizing a structure that suppresses an influence of external noise on an LDO and a load.

A power supply device according to an embodiment of the present invention has an enable terminal capable of externally connecting LDO (Low Drop Out) disposed outside the power supply device, and is configured to perform start/stop control of the LDO by an enable signal output from the enable terminal (first configuration).

In the first configuration, a feedback terminal may be provided, which is capable of inputting an output voltage of the LDO; and an overvoltage/low voltage detection unit that compares a voltage based on the voltage of the feedback terminal with a first reference voltage and outputs a first overvoltage detection signal, and a second comparator (second configuration) that compares a voltage based on the voltage of the feedback terminal with a second reference voltage and outputs a first low voltage detection signal.

In the second configuration, the power supply unit may include an or circuit to which a signal based on the first overvoltage detection signal and a signal based on the first low voltage detection signal are input, and the flag signal may be output based on an output of the or circuit (third configuration).

In the third configuration, a masking unit may be provided that determines whether or not to mask the first overvoltage detection signal and the first low voltage detection signal based on a combination of levels of the first overvoltage detection signal before and after the rising of the enable signal (fourth configuration).

In the third or fourth configuration, at least one power supply circuit may be provided, and the or circuit may be supplied with a second overvoltage detection signal and a second low voltage detection signal generated by the power supply circuit (fifth configuration).

In any one of the second to fifth configurations, the overvoltage/low voltage detection unit may have a mode setting terminal, and the overvoltage/low voltage detection unit may switch a resistance voltage dividing ratio for dividing the voltage of the feedback terminal according to the setting of the mode setting terminal, and may input the divided voltage to the first comparator and the second comparator (sixth configuration).

In addition, in any one of the first to sixth configurations, there may be at least 2 power supply circuits; and a logic unit including a nor circuit to which a third low voltage detection signal generated by the power supply circuit is input, a first and circuit to which a soft start detection signal indicating whether or not a soft start signal reaches a final voltage in the power supply circuit is input, and a second and circuit to which an output of the nor circuit and an output of the first and circuit are input, the power supply apparatus generating the enable signal based on the output of the second and circuit (seventh configuration).

In any one of the first to seventh configurations, the power supply device has a rectangular shape in plan view, and includes a first side, a second side opposite to the first side, a third side, and a fourth side opposite to the third side, the enable terminal is disposed at an end portion of the fourth side, and a power supply terminal capable of applying a power supply voltage of the power supply device is disposed at the third side of the second side (eighth configuration).

In any one of the second to sixth configurations, the power supply device has a rectangular shape in plan view, and includes a first side, a second side opposite to the first side, a third side, and a fourth side opposite to the third side, the enable terminal is disposed on the fourth side, and the feedback terminal is disposed on the third side (ninth configuration).

In any one of the first to ninth configurations, the power supply device includes a DC/DC converter having a first side, a second side opposite to the first side, a third side, and a fourth side opposite to the third side, and a power supply terminal, a ground terminal, a switch terminal connected to a node connecting an upper transistor and a lower transistor included in the DC/DC converter, a feedback voltage terminal for inputting a feedback voltage, a VREG terminal for outputting an internal voltage, and a terminal included in a first terminal group capable of connecting a start terminal of a bootstrap capacitor are disposed on the first side, the second side, and the third side, respectively.

Drawings

Fig. 1 shows an external terminal structure of a PMIC.

Fig. 2 is a block diagram showing the internal structure of the PMIC.

Fig. 3 shows a CMOS sensor supplied with power from the PMIC.

Fig. 4 mainly shows a configuration example of an oscillator in the PMIC.

Fig. 5 is a timing chart showing the start-up operation of the oscillator in the case where the capacitor is externally connected to the SSCG terminal.

Fig. 6 mainly shows the structure of the first DC/DC converter in the PMIC.

Fig. 7 mainly shows the structure of the second DC/DC converter or the third DC/DC converter in the PMIC.

Fig. 8 mainly shows a structure in a PMIC associated with an LDO outside the IC.

Fig. 9 is a timing chart showing an example of the rising sequence.

Fig. 10 is a timing chart showing a falling sequence corresponding to the rising sequence shown in fig. 9.

Fig. 11 shows a case where no external LDO is used in the structure of the PMIC of fig. 8.

Fig. 12 shows a modification of the structure of the PMIC shown in fig. 8.

Fig. 13 is a table showing a masking determination of an overvoltage/low voltage detection signal.

Fig. 14 is a timing chart showing a rising sequence in the structure of fig. 12.

Fig. 15 shows an example of the usage of LDO.

Fig. 16 shows another example of the usage of LDO.

Fig. 17 is a table showing an example of setting contents corresponding to the MODE setting of the MODE (MODE) 0 to MODE (MODE) 2 terminals.

Fig. 18 is a plan view of the PMIC as viewed from above.

Fig. 19 is a plan view schematically showing an example of layout on a substrate.

Detailed Description

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. A PMIC (power management IC) will be described as an example of a power supply device.

< 1, overall structure of PMIC >

Fig. 1 shows an external terminal structure of a PMIC1 according to an exemplary embodiment of the present invention. Fig. 2 is a block diagram showing the internal structure of the PMIC 1. The PMIC1 is an IC that supplies power to a CMOS sensor (CMOS camera) for vehicle.

The PMIC1 includes, as external terminals for establishing electrical connection with the outside, a VCC terminal, an EN terminal, an SSCG terminal, an RT terminal, a MODE (MODE) 0 terminal, a MODE 1 terminal, a MODE 2 terminal, an fb_ldo terminal, a VO1 terminal, a VO2 terminal, a VO3 terminal, a VS2 terminal, a VS3 terminal, a SW1 terminal, a SW2 terminal, a SW3 terminal, a PGND23 terminal, a GND terminal, a PGND1 terminal, a start (BOOT) terminal, a PVCC terminal, a PGOOD terminal, an en_ldo terminal, and a VREG terminal.

The PMIC1 includes, as internal structures, a UVLO unit 2, an internal voltage generation unit 3, a reference voltage generation unit 4, a reference voltage generation unit 5, a TSD unit 6, a UVLO unit 7, a UVLO unit 8, an oscillator (clock generation circuit) 9, a control logic unit 10, a first DC/DC converter 11, a second DC/DC converter 12, a third DC/DC converter 13, an overvoltage/low voltage detection unit 14, a driver 15, and an NMOS transistor 16, which are integrated into one chip.

A power supply voltage VCC is externally applied to the VCC terminal, and a capacitor C1 as a Bypass capacitor (Bypass capacitor) is externally connected between the VCC terminal and ground.

The UVLO (Under Voltage Lock Out under-voltage lockout) unit 2 is a circuit for detecting that the power supply voltage Vcc is equal to or lower than a predetermined detection voltage. The UVLO unit 2 sets the detection signal uvlo_vcc to the UVLO detection state when the power supply voltage Vcc is equal to or lower than the detection voltage, and sets the detection signal uvlo_vcc to the UVLO release state when the power supply voltage Vcc is equal to or higher than a predetermined recovery voltage. The control logic unit 10 performs control corresponding to the detection signal uvlo_vcc.

The internal voltage generating section 3 generates an internal voltage Vreg based on the power supply voltage Vcc. The internal voltage Vreg is used as a power supply voltage inside the IC, and is output from the Vreg terminal. A capacitor C2 as a bypass capacitor is connected between the VREG terminal and ground.

The enable signal En is externally input to the En terminal. The enable signal En is input to the internal voltage generation section 3 and the control logic section 10 via the En terminal.

The reference voltage generating units 4 and 5 generate reference voltages Vref1 and Vreg2 based on the internal voltage Vreg, respectively.

When detecting that the junction temperature of the IC is equal to or higher than a predetermined temperature, the TSD (thermal shutdown) unit 6 outputs an overheat detection signal TSD indicating the fact to the control logic unit 10. Thereby, the control logic unit 10 turns off the IC.

The UVLO unit 7 is a circuit that performs UVLO detection on the internal voltage Vreg, and outputs a detection signal uvlo_vreg to the control logic unit 10. The UVLO portion 8 is a circuit for UVLO detection of the output voltage Vo1 applied to the VS2 terminal, and outputs a detection signal uvlo_vs to the control logic portion 10. The output voltage Vo1 is a voltage output by the first DC/DC converter 11.

The oscillator 9 is a circuit that generates a clock signal, and outputs the generated clock signal to the control logic unit 10, the first DC/DC converter 11, the second DC/DC converter 12, and the third DC/CD converter 13 (clock signal CLKi (i=1 to 3)). The oscillator 9 has a spread spectrum function of varying the frequency of the clock signal with time. The modulation frequency of the spread spectrum is set by a capacitor C3 externally connected to the SSCG terminal. As described later, in the present embodiment, the control of switching the activation/deactivation of the spread spectrum function can be performed by one terminal of the SSCG terminal. The detailed structure of the oscillator 9 will be described later. In addition, the oscillation frequency of the clock signal generated by the oscillator 9 can be set by a resistor R1 externally connected to the RT terminal.

The control logic unit 10 receives various protection signals of the UVLO detection signal uvlo_vcc, the UVLO detection signal uvlo_vreg, the UVLO detection signal uvlo_vs, the overvoltage detection signal VSOVP, the low voltage detection signal LVDi (i=1 to 4), the overvoltage detection signal OVDi (i=1 to 4), the overcurrent detection signal OCP, and the overheat detection signal Tsd, and performs protection control based on the protection signals. The control logic unit 10 can also perform a rising/falling sequence control of the power supply circuit as described below.

The high level or the low level is set at the mode 0 to mode 2 terminals (fig. 1 is an example in which the low level (ground) is set at all terminals). The control logic unit 10 performs mode switching control corresponding to the level setting of the mode 0 to mode 3 terminals.

The first DC/DC converter 11 is a power supply circuit that DC/DC converts a power supply voltage Vcc applied to the PVCC terminals into an output voltage Vo1 and outputs the output voltage. The control logic unit 10 receives the control signal CTL1 from the first DC/DC converter 11, and receives the clock signal CLK1 from the oscillator 9.

The second DC/DC converter 12 is a power supply circuit that DC/DC converts an output voltage Vo1 applied to the VS2 terminal as an input voltage into an output voltage Vo2 and outputs the output voltage. The control logic unit 10 receives the control signal CTL2 from the second DC/DC converter 12, and receives the clock signal CLK2 from the oscillator 9.

The third DC/DC converter 13 is a power supply circuit that DC/DC converts the output voltage Vo1 applied to the VS3 terminal as an input voltage into an output voltage Vo3 and outputs the output voltage. The control logic unit 10 receives the control signal CTL3 from the third DC/DC converter 13, and receives the clock signal CLK3 from the oscillator 9.

Detailed structures related to the first DC/DC converter 11, the second DC/DC converter 12, and the third DC/DC converter 13 will be described later.

The LDO (Low drop out) 20 shown in fig. 1 is a linear regulator (power supply circuit) that converts the output voltage Vo1 into the output voltage Vo4, and is disposed outside the PMIC 1. The output voltage Vo4 is feedback-input to the fb_ldo terminal. The overvoltage/low voltage detection section 14 monitors the output voltage Vo4 input from the fb_ldo terminal, and outputs an overvoltage detection signal OVD4 and a low voltage detection signal LVD4 to the control logic section 10. The detailed configuration of the overvoltage/low voltage detection unit 14 will be described later.

In addition, the LDO20 performs start/stop control based on the enable signal en_ldo output from the en_ldo terminal by the control logic portion 10.

The driver 15 and the NMOS transistor 16 are structures related to a power good function. The power supply good function is a function of outputting a flag at a timing when the output of the power supply circuit reaches a set voltage value. The flag signal PG is externally output from the PGOOD terminal. Details of the structure related to the good function of the power supply will be described later.

Fig. 3 shows a CMOS sensor 30 to which power is supplied from the PMIC 1. The CMOS sensor 30 has a digital terminal, an I/O terminal, an LVDS terminal, an analog terminal, and a reset terminal. The output voltage Vo2 is applied to the digital terminal, the output voltage Vo3 is applied to the I/O terminal and the LVDS terminal, and the output voltage Vo4 is applied to the analog terminal. In addition, a flag signal PG is input to the reset terminal.

< 2, structure of Oscillator >

Next, the details of the structure of the oscillator 9 will be described. Fig. 4 mainly shows a configuration example of the oscillator 9 in the PMIC 1. As shown in fig. 4, the oscillator 9 has a constant current circuit 91, a constant current circuit 92, a comparator 93, a comparator 94, a switch 95, a constant current circuit 96, a PNP transistor 97, a PNP transistor 98, and a VCO99.

A constant current circuit 91 and a constant current circuit 92 are arranged between the application terminal of the power supply voltage (internal voltage) Vreg and ground. A non-inverting input terminal (+) of the comparator 93 is connected to a connection node N91 between the constant current circuit 91 and the constant current circuit 92. The application terminals of the reference voltages V2, V3 are switchably connected to the inverting input terminal (-) of the comparator 93. The constant current circuits 91, 92 are controlled to be turned on and off according to the output of the comparator 93.

The non-inverting input (+) connecting node N91 and comparator 94 is connected to the SSCG terminal. The application terminals of the reference voltages V2, V4 are switchably connected to the inverting input (-) of the comparator 94.

The switch 95 selects the terminal voltage Vsscg or the power supply voltage Vreg generated at the SSCG terminal to be output as the voltage V91 in accordance with the enable signal En9 output from the comparator 94.

The voltage V91 output from the switch 95 is applied to the base of the PNP transistor 97. The collector of PNP transistor 97 is grounded. The reference voltage V1 is applied to the base of the PNP transistor 98, and the collector is grounded. A constant current circuit 96 is arranged between the application terminal of the power supply voltage Vreg and the emitters of the PNP transistors 97, 98.

VCO (Voltage-controlled oscillator: voltage-controlled oscillator) 99 is a circuit that outputs clock signal CLK having an oscillation frequency corresponding to Voltage V92 generated at connection node N92 connecting the emitters of PNP transistors 97 and 98 and constant current circuit 96. VCO99 has NPN transistor 99B, current mirror 99C, capacitor 99D, comparator 99E, and switch 99F.

A voltage V92 is applied to the base of NPN transistor 99B. A first end of the resistor R1 is connected to an emitter of the NPN transistor 99B via the RT terminal. The second terminal of resistor R1 is grounded. The current mirror 99C is formed of a PMOS transistor, and causes a current having the same current value as the current flowing through the resistor R1 to flow into the capacitor 99D. A first terminal of the capacitor 99D is connected to the non-inverting input terminal (+) of the comparator 99E. The reference voltage Ref9 is applied to the inverting input terminal (-) of the comparator 99E. The switch 99F is a switch for discharging the capacitor 99D.

The lower of the voltage V91 and the reference voltage V1 is selected, and the voltage V92 is generated by adding the base-emitter voltages of the PNP transistors 97 and 98 to the selected voltage. The constant current I99 is generated by a voltage obtained by subtracting the base-emitter voltage of the NPN transistor 99B from the voltage V92 and the resistor R1. If the selected voltage of the voltage V91 and the reference voltage V1 is Vs, the current value of the constant current I99 becomes Vs/R1 (R1: the resistance value of the resistor R1). Such constant current I99 is mirrored by the current mirror 99C toward the capacitor 99D side.

When the switch 99F is turned off and the capacitor 99D is charged with a constant current, the voltage V93 generated in the capacitor 99D increases from 0V, and when the reference voltage Ref9 is exceeded, the clock signal CLK, which is the output of the comparator 99E, becomes high. Then, the switch 99F is turned on, the capacitor 99D is discharged, the voltage V93 drops to 0V, and the clock signal CLK is set to a low level. Then, the switch 99F is turned off again, and charging of the capacitor 99D is started. Thus, the clock signal CLK which repeats the high level and the low level is generated.

The frequency f of the clock signal CLK is represented as follows.

f＝1/t

Wherein t= (c×ref9)/(Vs/R1) C: capacitance of capacitor 99D

That is, the clock signal CLK having a frequency corresponding to the selected voltage Vs of the voltage V91 and the reference voltage V1 is generated. In addition, the frequency f of the clock signal CLK can be set by the resistance value of the resistor R1.

The operation of the oscillator 9 having such a configuration will be described. Fig. 5 is a timing chart showing the start-up operation of the oscillator 9 when the capacitor C3 (fig. 4) is externally connected to the SSCG terminal. As shown in FIG. 5, the magnitude of each voltage is Vreg > V1 > V2 > V3 > V4.

First, at time t0, the terminal voltage Vsscg is 0V, the output of the comparator 93 is low by comparison with the reference voltage V2, the constant current circuit 91 is turned on, and the constant current circuit 92 is turned off. Thereby, the constant current circuit 91 starts charging the capacitor C3, and the terminal voltage Vsscg starts rising. At this time, the comparator 94 sets the enable signal En9 to a low level by comparison with the reference voltage V2, and selects the power supply voltage Vreg by the switch 95. Thus, the voltage V91 becomes Vreg, and the lower one V1 of Vreg and V1 is selected. Accordingly, the clock signal CLK having a constant frequency corresponding to the reference voltage V1 is generated.

Then, when the terminal voltage Vsscg exceeds the reference voltage V2 at the timing t1, the enable signal En9 goes high, and the terminal voltage Vsscg is selected by the switch 95. Thus, the voltage V91 is the terminal voltage Vsscg (=v2), and the lower Vsscg of Vsscg and V1 is selected. Accordingly, the clock signal CLK having a frequency corresponding to Vsscg is generated.

At this time, the output of the comparator 93 goes high, the constant current circuit 91 is turned off, the constant current circuit 92 is turned on, the capacitor C3 starts discharging, and the terminal voltage Vsscg starts decreasing. When the terminal voltage Vsscg becomes lower than the reference voltage V3, the output of the comparator 93 becomes low, the constant current circuit 91 is turned on, the constant current circuit 92 is turned off, and the capacitor C3 starts to be charged. Thus, the terminal voltage Vsscg becomes a triangular wave that rises and falls between the reference voltages V2 and V3. Therefore, the terminal voltage Vsscg of the terminal voltages Vsscg and V1 is always low and selected, and the clock signal CLK having a frequency corresponding to the terminal voltage Vsscg as a triangular wave is generated.

The comparator 94 switches the reference voltage to V4 at the timing t1, but the terminal voltage Vsscg is a triangular wave between V2 and V3, and therefore is not lower than V4, and the enable signal En9 is maintained at a high level.

Accordingly, the frequency of the clock signal CLK changes with time, and therefore, the spread spectrum function of suppressing the peak of the power of the spectrum by dispersing the frequency of the spectrum becomes effective. The frequency of the terminal voltage Vsscg, which is a triangular wave, is determined based on the capacitance of the capacitor C3 externally connected to the SSCG terminal, and thus the modulation frequency of the spread spectrum is also determined. Specifically, the larger the capacitance of the capacitor C3, the lower the modulation frequency of the spread spectrum.

The lower the modulation frequency of the spread spectrum is, the lower the peak value of the power can be, but in the present embodiment, the capacitor C3 is disposed externally by providing the SSCG terminal, and therefore the capacitance of the capacitor C3 is easily increased.

In the case of disabling the spread function, the ground may be connected to the SSCG terminal externally. In this case, the enable signal En9, which is the output of the comparator 94, is maintained at a low level, and the selection of Vreg is maintained by the switch 95. Thus, the clock signal CLK having a constant frequency corresponding to the lower V1 of Vreg and V1 is generated, and the spread function becomes ineffective.

As described above, in the present embodiment, the setting of the modulation frequency of the spread spectrum and the active/inactive control of the spread spectrum function can be realized by one terminal of the SSCG terminal, and therefore, the effect of reducing the number of terminals can be realized.

Structure of 3 DC/DC converter

Next, a structure of the DC/DC converter incorporated in the PMIC1 will be described.

Fig. 6 mainly shows the structure of the first DC/DC converter 11 in the PMIC 1. The first DC/DC converter 11 is a step-down DC/DC converter that steps down and converts the power supply voltage Vcc into the output voltage Vo 1.

The first DC/DC converter 11 includes an error amplifier 11A, a soft start section 11B, PWM comparator 11C, a ramp generation section 11D, a current detection section 11E, a drive logic section 11F, a comparator 11G, an upper driver 11H, a lower driver 11I, and a driver 11J. Further, the first DC/DC converter 11 has resistors R11 to R20, comparators CP11 to CP13, a detection resistor Rs11, an upper side MOS transistor M11, a lower side MOS transistor M12, an NMOS transistor M13, and a PMOS transistor M14.

The inductor L1, the start capacitor Cb, the input capacitor Cin1, and the output capacitor Co1 are disposed outside the PMIC 1.

The output voltage Vo1 is applied to the Vo1 terminal as a feedback voltage, and divided by the resistors R11 and R12. The divided voltage is input to the inverting input terminal (-) of the error amplifier 11A. The soft start voltage ss1 generated by the soft start unit 11B is applied to the first non-inverting input terminal (+) of the error amplifier 11A. A voltage obtained by dividing the reference voltage Vref1 by the resistors R13 and R14 is applied to the second non-inverting input terminal (+) of the error amplifier 11A.

Error amplifier 11A is a transconductance amplifier that outputs a current corresponding to an error between the lower of the voltages applied to the first and second non-inverting inputs and the voltage applied to the inverting input. An inverting input terminal (-) of the PWM comparator 11C and a first terminal of the resistor R15 are connected to the output terminal of the error amplifier 11A. The second terminal of resistor R15 is connected to the first terminal of capacitor C11. The second terminal of the capacitor C11 is grounded.

A signal based on the ramp voltage generated by the ramp generating section 11D is input to the non-inverting input terminal (+) of the PWM comparator 11C. The PWM comparator 11C outputs a PWM signal as a comparison result to the driving logic section 11F. The drive logic unit 11F outputs an upper control signal HSC1 and a lower control signal LSC1 based on the PWM signal.

The drain of the upper MOS transistor M11 as an NMOS transistor is connected to the PVCC terminal. The power supply voltage Vcc is applied to the PVCC terminal. The source of the upper MOS transistor M11 is connected to the drain of the lower MOS transistor M12 as an NMOS transistor through a connection node Nsw 1. The source of the lower MOS transistor M12 is connected to the PGND1 terminal. The PGND1 terminal is grounded. An input capacitor Cin1 is connected between the power supply voltage Vcc and ground.

The connection node Nsw1 is connected to the SW1 terminal. The SW1 terminal is externally connected to the first end of the inductor L1. An output capacitor Co1 is connected between the second end of the inductor L1 and ground.

The upper driver 11H drives the gate of the upper MOS transistor M11 based on the upper control signal HSC1 output from the drive logic portion 11F. The upper driver 11H applies a start-up voltage Vboot generated at a start-up (BOOT) terminal or a switching voltage Vsw1 of the SW1 terminal to the gate of the upper MOS transistor M11.

The lower driver 11I drives the gate of the lower MOS transistor M12 based on the lower control signal LSC1 output from the drive logic portion 11F. The lower driver 11I applies the ground potential of the terminal of the internal voltage Vreg or PGND1 to the gate of the lower MOS transistor M12.

Thus, PWM control is performed such that the voltage obtained by dividing the output voltage Vo1 by the resistors R11 and R12 matches the reference voltage based on the reference voltage Vref1, and the upper MOS transistor M11 and the lower MOS transistor M12, which are switching elements, are complementarily switched by the driving logic unit 11F. Thereby, the output voltage Vo1 is controlled to a voltage corresponding to the reference voltage and the voltage division ratio of the resistors R11, R12.

In addition, in order to drive the upper MOS transistor M11, bootstrap (Boot Strap) is configured. A start capacitor Cb is connected between the start (BOOT) terminal and the SW1 terminal. When the upper MOS transistor M11 is turned off, the drive logic unit 11F outputs the switching voltage Vsw1 from the driver 11J to the PMOS transistor M14 by the start control signal boot_c. Thus, PMOSM14 is turned on, the VREG terminal and the start terminal are turned on, and start capacitor Cb is charged with internal voltage VREG.

Accordingly, when the upper MOS transistor M11 is turned on, the start-up voltage Vboot higher than the switching voltage Vsw1 can be applied to the gate of the upper MOS transistor M11 by the upper driver 11H. At this time, the PMOS transistor 14 is turned off by the start control signal boot_c, and the start capacitor Cb is discharged.

Further, a first end of the detection resistor Rs11 is connected to the PVCC terminal. The second terminal of the detection resistor Rs11 is connected to the drain of the NMOS transistor M13. The source of the NMOS transistor M13 is connected to the connection node Nsw 1.

The node connecting the detection resistor Rs11 and the NMOS transistor M13 is connected to the inverting input terminal (-) of the comparator 11G. A voltage lower than the PVCC terminal voltage by the reference voltage REF11 is applied to the non-inverting input terminal (+) of the comparator 11G.

The gate of the NMOS transistor M13 is driven by the upper side driver 11H. That is, the NMOS transistor M13 is turned on and off in synchronization with the upper side MOS transistor M11. When the upper MOS transistor M11 is turned on, that is, the NMOS transistor M13 is turned on, a voltage generated due to a current flowing through the upper MOS transistor M11 and an on-resistance of the upper MOS transistor M11 is approximately applied between both ends of the detection resistor Rs 11. When the voltage lower than the PVCC terminal voltage by the voltage between both ends of the detection resistor Rs11 is lower than the voltage lower than the PVCC terminal voltage by the reference voltage REF11, the comparator 11G detects an overcurrent and outputs the high-level overcurrent detection signal OCP1 to the driving logic section 11F. Thereby, the drive logic unit 11F can perform overcurrent protection.

The current detection unit 11E outputs a current detection signal based on the voltage across the detection resistor Rs 11. The current detection signal is added to the ramp voltage, and is input to the PWM comparator 11C.

The voltage obtained by dividing the output voltage Vo1 applied to the VS2 terminal by the resistors R19 and R20 is applied to the non-inverting input terminal (+) of the comparator CP11, and the reference voltage Vref2 is applied to the inverting input terminal (-) of the comparator CP 11. The comparator CP11 is a hysteresis comparator, and outputs an overvoltage detection signal VSOVP.

The voltage obtained by dividing the output voltage Vo1 by the resistors R11 and R12 is applied to the non-inverting input terminal (+) of the comparator CP12, and the voltage obtained by dividing the reference voltage Vref2 by the combined resistance of the resistor R16 and the resistors R17 and R18 is applied to the inverting input terminal (-) of the comparator CP 12. The comparator CP12 is a hysteresis comparator, and outputs an overvoltage detection signal OVD1.

The voltage obtained by dividing the output voltage Vo1 by the resistors R11 and R12 is applied to the inverting input terminal (-) of the comparator CP13, and the voltage obtained by dividing the reference voltage Vref2 by the combined resistor of the resistors R16 and R17 and the resistor R18 is applied to the non-inverting input terminal (+) of the comparator CP 13. The comparator CP13 is a hysteresis comparator, and outputs a low voltage detection signal LVD1.

Next, the configuration of the second DC/DC converter 12 and the third DC/DC converter 13 will be described. Fig. 7 mainly shows the structure of the second DC/DC converter 12 or the third DC/DC converter 13 in the PMIC 1. In addition, with respect to the subscript i of the symbol in the drawing, i=2 denotes the second DC/DC converter 12, and i=3 denotes the third converter DC/DC13. Hereinafter, description will be made using subscripts.

The second DC/DC converter 12 and the third DC/DC converter are step-down DC/DC converters that step down the output voltage Vo1 to convert the output voltage Voi.

The second DC/DC converter 12 and the third DC/DC converter 13 include an error amplifier 21A, a soft start unit 21B, PWM, a comparator 21C, a ramp generation unit 21D, a current detection unit 21E, a drive logic unit 21F, a comparator 21G, an upper driver 21H, a lower driver 21I, and a comparator 21J. Further, the second DC/DC converter 12 and the third DC/DC converter 13 include resistors R21 to R28, comparators CP21 and CP22, detection resistors Rs21 and Rs22, an upper side MOS transistor M21, a lower side MOS transistor M22, a PMOS transistor M23, an NMOS transistor M24, and an NMOS transistor M25.

The inductor Li and the output capacitor Coi are disposed outside the PMIC 1.

The structures of the second DC/DC converter 12 and the third DC/DC converter 13 are similar to those of the first DC/DC converter 11 described above, and thus detailed description thereof is appropriately omitted. The output voltage Voi applied to the Voi terminal as a feedback voltage is divided by the resistors R21, R22 and applied to the inverting input terminal (-) of the error amplifier 21A. The error amplifier 21A outputs a current corresponding to an error between the lower one of the voltage obtained by dividing the reference voltage Vref1 by the resistors R23 and R24 and the soft start voltage ssi of the soft start unit 21B and the divided voltage of the output voltage Voi.

The source of the upper MOS transistor M21 as a PMOS transistor is connected to the VSi terminal to which the output voltage Vo1 is applied. The drain of the upper MOS transistor M21 is connected to the drain of the lower MOS transistor M22 as an NMOS transistor through a connection node Nswi. The source of the lower MOS transistor M22 is connected to the PGND23 terminal. The PGND terminal 23 is grounded.

The connection node Nswi is connected to the SWi terminal. The SWi terminal is connected to a first end of the inductor Li. The second terminal of the inductor Li is connected to the first terminal of the output capacitor Coi.

The upper side MOS transistor M21 is driven by the upper side driver 21H switching the VSi terminal voltage and SWi terminal voltage and applying to the gate of the upper side MOS transistor M21. The lower MOS transistor M22 is driven by the lower driver 21I switching between the VSi terminal voltage and the SWi terminal voltage and applying to the gate of the lower MOS transistor M22. The upper side MOS transistor M21 and the lower side MOS transistor M22 are complementarily switched.

The PMOS transistor M23, the detection resistor Rs21, and the comparator 21G are configured to detect an overcurrent flowing through the upper MOS transistor M21 when the upper MOS transistor M21 is turned on, and the upper overcurrent detection signal OCPHi is output from the comparator 21G.

The NMOS transistor M24, the detection resistor Rs22, and the comparator 21J are configured to detect an overcurrent flowing through the lower MOS transistor M22 when the lower MOS transistor M22 is turned on, and the lower overcurrent detection signal OCPLi is output from the comparator 21J.

When the control signal CTLi is low (inactive), the NMOS transistor M25 turns on to discharge the output capacitor Coi.

The comparator CP21 compares a voltage obtained by dividing the output voltage Voi by the resistors R21 and R22 with a voltage obtained by dividing the reference voltage Vref2 by a combined resistor of the resistor R26 and the resistors R27 and R28, and outputs an overvoltage detection signal OVDi.

The comparator CP22 compares a voltage obtained by dividing the output voltage Voi by the resistors R21 and R22 with a voltage obtained by dividing the reference voltage Vref2 by the combined resistor of the resistors R26 and R27 and the resistor R28, and outputs a low-voltage detection signal LVDi.

The resistance voltage dividing ratio of the resistors R11 and R12 in the first DC/DC converter 11 and the resistance voltage dividing ratio of the resistors R21 and R22 in the second DC/DC converter 12 can be switched by a mode set by the mode 0 to mode 2 terminals, which will be described later.

< 4 Structure relating to external LDO >

As described in fig. 1, in the present embodiment, LDO20 is disposed outside PMIC 1. The structure of PMIC1 in which LDO20 is disposed outside the IC in this way will be described.

Fig. 8 mainly shows the structure of PMIC1 associated with LDO20 outside the IC. The LDO20 is a linear regulator that steps down the output voltage Vo1 generated by the first DC/DC converter 11 to an output voltage Vo 4. By disposing the LDO20 outside the PMIC1, the LDO20 can be disposed in the vicinity of the CMOS sensor 30 shown in fig. 3, and the wiring length between the LDO20 and the CMOS sensor 30 can be shortened, so that the impedance of the wiring can be reduced, and thus countermeasures against external noise can be easily taken. In addition, by disposing LDO outside the IC, the heat generation source can be dispersed.

In the present embodiment, as shown in fig. 8, the en_ldo terminal provided in PMIC1 is connected to the enable terminal 20A of LDO 20. Thus, the start/stop control (on/off control) of the LDO20 can be performed using the enable signal en_ldo output from the en_ldo terminal.

In addition, as shown in fig. 8, when the LDO20 is used, the output voltage Vo1 is applied to the input terminal 20B of the LDO20, and the output terminal 20C of the output voltage Vo4 of the LDO20 and the fb_ldo terminal are short-circuited through wiring outside the IC. Thus, the output voltage Vo4 is feedback-input to the fb_ldo terminal.

Here, as shown in fig. 8, the overvoltage/low voltage detection unit 14 includes resistors 14A to 14C, a switch 14D, resistors 14E to 14G, and comparators 14H and 14I. Resistors 14A, 14B, 14C are connected in series between the fb_ldo terminal and ground.

The switch 14D selects either one of the node N141 to which the resistors 14A and 14B are connected or the node N142 to which the resistors 14B and 14C are connected, according to the mode set by the mode 0 to mode 2 terminals. The potential of the selected node is applied to the non-inverting input (+) of the comparator 14H and the inverting input (-) of the comparator 14I. That is, the fb_ldo terminal voltage is divided by a voltage division ratio of resistance according to the mode switching. The mode setting will be described later.

The voltage obtained by dividing the power supply voltage Vreg by the resistor 14E and the combined resistor based on the resistors 14F and 14G is applied to the inverting input terminal (-) of the comparator 14H. The voltage obtained by dividing the power supply voltage Vreg by the combined resistor of the resistors 14E and 14F and the resistor 14G is applied to the non-inverting input terminal (+) of the comparator 14I. The comparators 14H, 14I are hysteresis comparators.

Thereby, the overvoltage detection signal OVD4 for detecting the overvoltage of the output voltage Vo4 is output from the comparator 14H, and the low voltage detection signal LVD4 for detecting the low voltage of the output voltage Vo4 is output from the comparator 14I. The overvoltage detection signal OVD4 and the low voltage detection signal LVD4 are input to the control logic unit 10. The control logic unit 10 can perform protection control by the overvoltage detection signal OVD4 and the low voltage detection signal LVD4.

In addition, fig. 8 also shows a structure related to a good function of the power supply. The PMIC1 has an OR (OR) circuit 10A, a counter 10B, a driver 15 (fig. 2), and an NMOS transistor 16 (fig. 2) as structures related to good functions of a power supply. In addition, the or circuit 10A and the counter 10B are included in the control logic section 10.

The or circuit 10A receives input of other overvoltage detection signals OVD1 to OVD3 and low voltage detection signals LVD1 to LVD3 in addition to OVD4 and LVD 4. The driver 15 performs on-off driving of the NMOS transistor 16. The source of NMOS transistor 16 is grounded. The drain of the NMOS transistor 16 is connected to the PGOOD terminal. The PGOOD terminal is externally connected to the first end of the resistor R2. The output voltage Vo3 is applied to the second terminal of the resistor R2. The operation of such a structure related to a good function of the power supply will be described later.

< 5, up/Down sequence >)

Next, a control of the rising sequence of PMIC1 based on the configuration shown in fig. 8 will be described. Fig. 9 is a timing chart showing an example of the rising sequence.

First, the power supply voltage Vcc starts to rise, and thereafter, the enable signal En starts to rise. When the enable signal En reaches the threshold voltage vth_en, the internal voltage generation unit 3 starts the rise of the internal voltage Vreg. When detecting that the internal voltage Vreg reaches the recovery voltage (release voltage) vth_uvlovreg_off, UVLO7 outputs a detection signal uvlo_vreg indicating release of UVLO to the control logic unit 10.

Then, after a predetermined period T1 (for example, 200 μs) has elapsed, the control logic unit 10 instructs the first DC/DC converter 11 to raise the soft start signal ss1. Specifically, the soft start unit 11B (fig. 6) in the first DC/DC converter 11 includes a DAC (DA converter) and outputs a soft start signal ss1, which is an analog output corresponding to a digital instruction from the control logic unit 10. The soft start unit 21B (fig. 7) includes a DAC as well.

Before the soft start signal ss1 rises to reach the reference voltage obtained by dividing the reference voltage Vref1 by the resistors R13 and R14, the soft start signal ss1 is selected as the reference voltage by the error amplifier 11A, and if the soft start signal ss1 exceeds the reference voltage based on the reference voltage Vref1, the reference voltage is selected later by the error amplifier 11A. As a result, as shown in fig. 9, the output voltage Vo1 rises simultaneously with the rising of the soft start signal ss1, and the output voltage Vo1 becomes a constant voltage in the middle of the rising of the soft start signal ss1.

When the soft start signal ss1 rises and reaches the final voltage ss1_finish, the control logic unit 10 instructs the second DC/DC converter 12 to rise the soft start signal ss 2. The output voltage Vo2 rises simultaneously with the rising of the soft start signal ss2, and becomes a constant voltage in the middle of the rising of the soft start signal ss 2.

When the soft start signal ss2 rises and reaches the final voltage ss2_finish, the control logic unit 10 instructs the third DC/DC converter 13 to rise the soft start signal ss 3. The output voltage Vo3 rises simultaneously with the rising of the soft start signal ss3, and becomes a constant voltage in the middle of the rising of the soft start signal ss 3.

Here, as shown in fig. 8, the control logic section 10 has a NOR (NOR) circuit 10C, an AND (AND) circuit 10D, AND a AND circuit 10E as a configuration related to the rising sequence. The nor circuit 10C receives the overvoltage detection signals LVD1 to LVD3. A soft start detection signal SS1H indicating whether or not the soft start signal SS1 reaches the final voltage ss1_finish, a soft start detection signal SS2H indicating whether or not the soft start signal SS2 reaches the final voltage ss2_finish, and a soft start detection signal SS3H indicating whether or not the soft start signal SS3 reaches the final voltage ss3_finish are input to the and circuit 10D. The output to the and circuit 10E or the nor circuit 10C and the output to the and circuit 10D. The AND circuit 10E outputs an enable signal En_LDO to the LDO20 via an EN_LDO terminal. The output voltage Vo1 is applied as a power supply voltage to the and circuit 10E via the VS2 terminal.

Returning to the description of fig. 9, at the timing when the soft start signal ss3 rises to reach the final voltage ss3_finish, the output voltages Vo1 to Vo3 respectively exceed the low voltage threshold voltages vth_lvd12 to vth_lvd32 of the hysteresis comparator, the low voltage detection signals LVD1 to LVD3 are all low levels, and further, the soft start detection signals SSH1 to SSH3 are all high levels, so the enable signal en_ldo is switched from low level to high level.

Thus, LDO20 is enabled and output voltage Vo4 begins to rise. When the output voltage Vo4 exceeds the low voltage threshold voltage vth_lvd42 of the hysteresis comparator, the low voltage detection signal LVD4 becomes a low level. At this time, the overvoltage detection signals OVD1 to OVD4 are all low, and the low voltage detection signals LVD1 to LVD4 are all low, so that the output of the or circuit 10A is switched from high to low. Then, the counter 10B starts counting, and when a predetermined period T2 (for example, 10 ms) passes, the driver 15 switches the NMOS transistor 16 from on to off by the control of the counter 10B. Thereby, the flag signal PG generated at the PGOOD terminal is switched from the low level to the high level.

As described above, in the present embodiment, after the first DC/DC converter 11, the second DC/DC converter 12, the third DC/DC converter 13, and the LDO20 are started in this order by the up-sequence, the flag signal PG based on the power supply good function is set to the start-up state.

Next, a falling sequence corresponding to the rising sequence shown in fig. 9 will be described with reference to the timing chart of fig. 10.

In fig. 10, when the enable signal En falls to reach the threshold voltage vth_en, the control logic section 10 switches the enable signal en_ldo from a high level to a low level, and switches the flag signal PG from a high level to a low level. Thus, LDO20 is stopped and output voltage Vo4 drops.

When the output voltage Vo4 falls to reach the low voltage threshold voltage vth_lvd41 of the hysteresis comparator, the low voltage detection signal LVD4 becomes a high level. Then, the control logic unit 10 instructs the third DC/DC converter 13 on the soft start signal ss3 and the drop of the output voltage Vo 3.

When the output voltage Vo3 falls to reach the low voltage threshold voltage vth_lvd31 of the hysteresis comparator, the low voltage detection signal LVD3 becomes a high level. Then, the control logic unit 10 instructs the second DC/DC converter 12 on the soft start signal ss2 and the drop of the output voltage Vo 2.

When the output voltage Vo2 falls to reach the low voltage threshold voltage vth_lvd21 of the hysteresis comparator, the low voltage detection signal LVD2 becomes a high level. Then, the control logic unit 10 instructs the first DC/DC converter 11 to decrease the soft start signal ss1 and the output voltage Vo1, and instructs the internal voltage generating unit 3 to decrease the internal voltage Vreg.

In this way, the power supply circuit can be stopped in the reverse order of the rising sequence shown in fig. 9.

< 6, LDO overvoltage/Low Voltage detection mask function >)

Fig. 11 shows a case where the external LDO20 is temporarily not used in the structure of the PMIC1 of fig. 8. In this case, as shown in fig. 11, the fb_ldo terminal becomes an open circuit. Then, the signal input to the inverting input terminal (-) of the comparator 14I becomes a low level (ground potential). Thus, the low voltage detection signal LVD4 maintains a high level. Therefore, the low voltage protection is performed, and the flag signal PG output from the PGOOD terminal does not go high, and does not shift to the next sequence.

Accordingly, the PMIC1 of the present embodiment may also employ the configuration shown in fig. 12. In the configuration shown in fig. 12, a shield 10F is added to the control logic 10. The shielding section 10F has a function of shielding the overvoltage detection signal OVD4 and the low voltage detection signal LVD 4.

More specifically, as shown in the table of fig. 13, the masking section 10F determines whether to perform masking processing of the overvoltage detection signal OVD4 and the low voltage detection signal LVD4 or normal processing without masking processing, based on a combination of the levels of the overvoltage detection signals OVD4 before and after the rising of the enable signal en_ldo.

In addition, as shown in fig. 12, the en_ldo terminal and the fb_ldo terminal are short-circuited by wiring outside the IC without using the external LDO 20. In addition, the output voltage Vo1 is applied to the VS2 terminal.

The rising sequence in the structure of fig. 12 is described using the timing chart of fig. 14. In the timing chart of fig. 14, the same as in fig. 9 described above is applied until the enable signal en_ldo rises. However, in fig. 14, the level (high) of the enable signal en_ldo after rising is a level of the output voltage Vo1 by being supplied to the output voltage Vo1 of the and circuit 10E through the VS2 terminal.

In addition, the enable signal en_ldo rises due to a short circuit between the en_ldo terminal and the fb_ldo terminal, and the fb_ldo terminal voltage also rises to the level of the output voltage Vo 1. Thus, the fb_ldo terminal voltage exceeds the overvoltage threshold voltage vth_ovd42 of the hysteresis comparator, and thus the overvoltage detection signal OVD4 switches from a low level to a high level.

Then, since the overvoltage detection signal OVD4 is at a low level before the enable signal en_ldo rises and the overvoltage detection signal OVD4 is at a high level after the enable signal en_ldo rises, the shielding section 10F shields the overvoltage detection signal OVD4 and the low voltage detection signal LVD4 from each other as shown in fig. 13. The masked overvoltage detection signal OVD4 and the low voltage detection signal LVD4 are set to low levels.

As a result, as shown in fig. 14, since the masked overvoltage detection signal OVD4 (broken line) is at a low level, the output of the circuit 10A is switched to a low level at this timing, and therefore the NMOS transistor 16 is turned off and the flag signal PG rises to a high level at a timing when the predetermined period T2 has elapsed from the timing by the counter 10B. In this way, if the configuration of fig. 12 is adopted, the flag signal PG of the power supply good function can be raised to high (the start-up state) even when the LDO20 is not used.

In the case of using the LDO20, the structure of the PMIC1 of fig. 12 is connected to the LDO20 in the same manner as in fig. 8. That is, the en_ldo terminal is connected to the enable terminal 20A of the LDO20, and the output terminal 20C of the output voltage Vo4 is applied to the fb_ldo terminal. Accordingly, in the rising sequence, the level of the overvoltage detection signal OVD4 is low before and after the rising of the enable signal en_ldo, so that the shielding section 10F does not perform the shielding of the overvoltage detection signal OVD4 and the low voltage detection signal LVD4 thereafter as shown in fig. 13. Therefore, when the low voltage detection signal LVD4 is switched to a low level due to the rising of the output voltage Vo4, the flag signal PG rises to a high level. The protection functions of the overvoltage detection signal OVD4 and the low voltage detection signal LVD4 are enabled.

In addition, as another mode of using the LDO20, the structure shown in fig. 15 may be used. That is, the en_ldo terminal is connected to the enable terminal 20A of the LDO20, and is short-circuited to the fb_ldo terminal. Thus, in the rising sequence, when the enable signal en_ldo rises, the fb_ldo terminal voltage also rises to the level of the output voltage Vo1, and the overvoltage detection signal OVD4 rises from the low level to the high level, so that the shielding function of the shielding section 10F is effective. That is, an embodiment in the case where the LDO20 is used but the overvoltage/low voltage protection function of the output voltage Vo4 is not required is presented.

In addition, fig. 16 shows another embodiment in the case of using the LDO 20. In the structure shown in fig. 16, the en_ldo terminal is open, the application terminal of the output voltage Vo1 is connected to the enable terminal 20A of the LDO20, and the output terminal 20C, from which the output voltage Vo4 is output, is connected to the fb_ldo terminal. Thus, in the rising sequence, the LDO20 is started by the rising of the output voltage Vo1, and the output voltage Vo4 rises. In addition, since the level of the overvoltage detection signal OVD4 is low before and after the rising of the enable signal en_ldo, the overvoltage detection signal OVD4 and the low voltage detection signal LVD4 are not masked as shown in fig. 13. Therefore, the overvoltage/low voltage protection function of the output voltage Vo4 is effective.

< 7, mode switching control >

Here, MODE switching using the MODE (MODE) 0 terminal, the MODE 1 terminal, and the MODE 2 terminal (fig. 1 and 2) will be described using the table of fig. 17. Fig. 17 shows setting contents corresponding to the mode setting of the mode 0 to mode 2 terminals.

As shown in fig. 17, 8 modes from a to H can be set according to the combination of signal levels (high or low) set at the mode 0 to mode 2 terminals. In fig. 1, all of the mode 0 to mode 2 terminals are low, and the mode a is set. As shown in fig. 17, mode setting is performed according to the type (a to F) of the CMOS sensor 30 (fig. 3) used.

As shown in fig. 17, the output voltage Vo4 of the LDO20 varies depending on the kind of the CMOS sensor 30 used. Here, the LDO defines a differential voltage, which is the lowest potential difference between the input and output that can be operated stably, and the input voltage of the LDO is preferably a voltage higher than the output voltage by a voltage equal to or higher than the differential voltage. In fig. 17, the output voltage Vo1 of the first DC/DC converter 11 is set to a voltage higher than the output voltage Vo4, which is different according to the mode setting, by 0.6V, which is an example of the predetermined voltage. This is because the output voltage Vo1 is the input voltage of the LDO 20.

In the configuration of the first DC/DC converter 11 (fig. 6), the resistance-voltage dividing ratio at which the output voltage VO1 fed back to the VO1 terminal is divided by the resistors R11 and R12 is changed according to the mode setting. The change of the resistance division ratio is performed in response to a command from the control logic unit 10. The change of the resistance voltage dividing ratio can be achieved by the same configuration as the switching configuration using the switch 14D shown in fig. 8, for example. By such a configuration of changing the resistance voltage dividing ratio in the first DC/DC converter 11, switching of the output voltage Vo1 according to the mode setting can be performed. Further, as shown in fig. 6, since the structure for changing the resistance-voltage division ratio is provided inside the IC, the number of components outside the IC can be reduced, or the reliability can be improved by manufacturing inside the IC.

As shown in fig. 17, the output voltage Vo2 of the second DC/DC converter 12 can be switched by setting the mode according to the type of the CMOS sensor 30. In the example shown in fig. 17, the output voltage vo2=1.2v is set in the a to D mode, and the output voltage vo2=1.1v is set in the E, F mode.

Such switching of the output voltage Vo2 is achieved by changing the resistance-voltage-dividing ratio by which the output voltage Vo2 fed back to the Vo2 terminal in the configuration of the second DC/DC converter 12 shown in fig. 7 is divided by the resistors R21 and R22, according to the mode setting.

In the example of fig. 17, the output voltage Vo3 of the third DC/DC converter 13 is set to the same voltage (1.8V, as an example) regardless of the mode setting corresponding to the CMOS sensor 30 used. In this case, the third DC/DC converter 13 does not need to change the resistance-voltage division ratio. However, in the third DC/DC converter 13 (fig. 7), the output voltage VO3 may be changed by changing the resistance division ratio by which the output voltage VO3 fed back to the VO3 terminal is divided by the resistors R21 and R22 through the mode setting.

In addition, as shown in fig. 17, the ascending order of the output voltages Vo2, vo3, vo4 in the ascending sequence and the descending order of the output voltages Vo2, vo3, vo4 in the descending order are changed by the mode setting corresponding to the CMOS sensor 30 used. In fig. 17, as an example, in the A, C to F modes, the ascending in the order of vo2→vo3→vo4, the descending in the order of vo4→vo3→vo2, and in the B mode, the ascending in the order of vo4→vo3→vo2, the descending in the order of vo2→vo3→vo4 are set. Thus, an appropriate rising sequence and falling sequence can be set according to the type of CMOS sensor 30 used.

The timing chart of fig. 9 shows the ascending in the order of vo2→vo3→vo4, and the timing chart of fig. 10 shows the descending in the order of vo4→vo3→vo2. The sequence in the up/down sequence is controlled by the control logic 10.

As shown in fig. 17, the protection operation (protection) of the PMIC1 is set to be variable by the mode setting corresponding to the CMOS sensor 30 used. As a protection operation, self-recovery (Self-restart) and Timer-Latch (Timer off Latch) can be switched.

In the self-recovery, when the abnormality detection state based on the overvoltage detection (OVD), the Low Voltage Detection (LVD), the overcurrent detection (OCP), and the like is maintained for a predetermined period (for example, 10 ms), the control logic section 10 stops all of the first DC/DC converter 11, the second DC/DC converter 12, the third DC/DC converter 13, and the LDO 20. Then, when a predetermined period (for example, 10 ms) elapses, the control logic unit 10 activates all of the first DC/DC converter 11, the second DC/DC converter 12, the third DC/DC converter 13, and the LDO 20. If the abnormal state continues, stopping and starting are repeated.

On the other hand, in the timer latch, if the abnormality detection state based on the overvoltage detection (OVD), the Low Voltage Detection (LVD), the overcurrent detection (OCP), or the like is maintained for a predetermined period (for example, 10 ms), the control logic unit 10 stops all of the first DC/DC converter 11, the second DC/DC converter 12, the third DC/DC converter 13, and the LDO20. The stopped state is maintained until reset by the enable signal EN or UVLO.

In the example shown in fig. 17, the self-recovery is set in the a to E mode, and the timer latch is set in the F mode.

< 8, external terminal configuration of IC >

Next, the characteristics of the external terminal arrangement (pin arrangement) of the PMIC1 will be described. Fig. 18 is a plan view of the PMIC1 (package) as viewed from above. In addition, in fig. 18, peripheral elements of PMIC1 and LDO20 are illustrated in addition to PMIC 1.

As shown in fig. 18, 24 external terminals (the numbers indicate pin numbers) are arranged on the back side (the back side of the paper surface) of the PMIC 1. The PMIC1 has a rectangular shape when viewed from above, and has a first side S1, a second side S2, a third side S3, and a fourth side S4. The first side S1 is opposite to the second side S2, and the third side S3 is opposite to the fourth side S4.

Along the first side S1, a SW3 terminal, a VS3 terminal, a PGND23 terminal, a VS2 terminal, a SW2 terminal, and a VO2 terminal are arranged in this order from the third side S3. Along the second side S2, a PVCC terminal, a VCC terminal, an EN terminal, a GND terminal, a VREG terminal, and a mode 0 terminal are arranged in this order from the third side S3. Along the third side S3, a VO3 terminal, fb_ldo terminal, VO1 terminal, start terminal, SW1 terminal, and PGND1 terminal are arranged in this order from the first side S1 side. Along the fourth side S4, an en_ldo terminal, a PGOOD terminal, an SSCG terminal, an RT terminal, a mode 2 terminal, and a mode 1 terminal are arranged in order from the first side S1 side.

The en_ldo terminal is disposed at the end of the fourth side S4 on the first side S1 side, and the PVCC terminal and the VCC terminal are disposed at the end of the second side S2 on the third side S3 side. Thus, the en_ldo terminal with low withstand voltage can be arranged at a position away from the PVCC terminal and Vcc terminal to which the power supply voltage Vcc is applied.

The en_ldo terminal is disposed on the fourth side S4, and the fb_ldo terminal is disposed on the third side S3 opposite to the fourth side S4. Thus, when the external LDO20 is used for the PMIC1 having the structure shown in fig. 12, it is possible to avoid a situation in which the en_ldo terminal is erroneously short-circuited to the fb_ldo terminal and the overvoltage detection signal OVD4 and the low voltage detection signal LVD4 are erroneously masked.

The mode 0 terminal, the mode 1 terminal, and the mode 2 terminal are disposed adjacently. In fig. 18, the mode 0 terminal, the mode 1 terminal, and the mode 2 terminal are adjacent to each other on different sides (the second side S2 and the fourth side S4), but may be adjacent to each other on the same side (for example, the fourth side S4).

As shown in fig. 18, at least one of the power supply terminal (VS 2 terminal, VS3 terminal, PVCC terminal, VCC terminal), the ground terminal (PGND 23 terminal, PGND1 terminal, GND terminal), the switch terminal (SW 1 terminal, SW2 terminal, SW3 terminal), the feedback voltage terminal (VO 1 terminal, VO2 terminal, VO3 terminal), the VREG terminal, and the terminal included in the first terminal group of the start terminal is arranged on each of the first side S1, the second side S2, and the third side S3, and the terminal arranged on the fourth side S4 is only the terminal (second terminal group) other than the first terminal group.

As shown in fig. 18, the wiring (thick line of fig. 18) electrically connected to the first terminal group outside the IC needs to be reduced in impedance. Therefore, each element (input capacitor, output capacitor, inductor, bypass capacitor, start capacitor) connected to the wiring needs to be disposed in the vicinity of the PMIC1 in a region surrounding the first side S1 to the third side S3 from the outside.

Fig. 19 is a plan view schematically showing an example of a layout on the substrate 40. As shown in fig. 19, the input capacitors Cin1 to Cin3, the output capacitors Co1 to Co3, the inductors L1 to L3, the bypass capacitors C1, C2, and the start capacitor Cb are arranged in the vicinity of the PMIC1 in a region surrounding the first side S1 to the third side S3 from the outside.

However, since the second terminal group is disposed on the fourth side S4 and the wiring electrically connected to the second terminal group outside the IC is required to have low necessity of reducing impedance, the elements (LDO 20, resistor R2, capacitor C3, and resistor R1) connected to the wiring may not be disposed in the IC vicinity region R on the fourth side S4 as shown in fig. 19. Thus, dead space (dead space) is not generated due to the arrangement of the elements.

< 9, others >

While various embodiments of the present invention have been described above, the embodiments may be variously modified within the scope of the gist of the present invention.

Claims (7)

1. A power supply device is characterized in that,

the power supply device has an enable terminal capable of externally connecting LDOs arranged outside the power supply device,

the start and stop control of the LDO is performed by an enable signal output from the enable terminal,

the power supply device is provided with:

a feedback terminal capable of inputting an output voltage of the LDO;

an overvoltage/low voltage detection unit having a first comparator that compares a first voltage based on the voltage of the feedback terminal with a first reference voltage and outputs a first overvoltage detection signal, and a second comparator that compares a second voltage based on the voltage of the feedback terminal with a second reference voltage and outputs a first low voltage detection signal;

a control logic unit that performs protection control by the first overvoltage detection signal and the first low voltage detection signal;

a power source good section including an or circuit to which a signal based on the first overvoltage detection signal and a signal based on the first low voltage detection signal are input, and outputting a flag signal based on an output of the or circuit; and

and a masking unit that determines whether or not to mask the first overvoltage detection signal and the first low voltage detection signal based on a combination of levels of the first overvoltage detection signal before and after the rising of the enable signal.

2. The power supply device according to claim 1, wherein,

the power supply device has at least one power supply circuit,

the second overvoltage detection signal and the second low voltage detection signal generated by the power supply circuit are also input to the or circuit.

3. The power supply device according to claim 1, wherein,

the power supply device has a mode setting terminal,

the overvoltage/low voltage detection unit switches a resistance voltage division ratio for dividing the voltage of the feedback terminal according to the setting of the mode setting terminal, and inputs the divided voltage to the first comparator and the second comparator.

4. The power supply device according to claim 1, wherein,

the power supply device includes:

at least 2 power supply circuits; and

a logic section including an NOR circuit to which at least 2 third low voltage detection signals generated by detecting output voltages outputted from the power supply circuits are inputted in each of the at least 2 power supply circuits, a first AND circuit to which at least 2 soft start detection signals indicating whether or not a soft start signal reaches a final voltage in each of the at least 2 power supply circuits are inputted, and a second AND circuit to which an output of the NOR circuit and an output of the first AND circuit are inputted,

The power supply device generates the enable signal based on the output of the second and circuit.

5. The power supply device according to claim 1, wherein,

the power supply device is rectangular in plan view,

the power supply device has a first side, a second side opposite to the first side, a third side, and a fourth side opposite to the third side,

the enable terminal is disposed at an end portion of the fourth side,

a power supply terminal to which a power supply voltage of the power supply device can be applied is arranged on the third side of the second side.

6. The power supply device according to claim 1, wherein,

the power supply device is rectangular in plan view,

the power supply device has a first side, a second side opposite to the first side, a third side, and a fourth side opposite to the third side,

the enable terminal is arranged on the fourth side,

the feedback terminal is disposed on the third side.

7. The power supply device according to claim 1, wherein,

the power supply device is rectangular in plan view,

the power supply device comprises a DC/DC converter,

the power supply device has a first side, a second side opposite to the first side, a third side, and a fourth side opposite to the third side,

At least one of a power supply terminal for inputting a power supply voltage, a ground terminal, a switch terminal connected to a node connecting an upper transistor and a lower transistor included in the DC/DC converter, a feedback voltage terminal for inputting a feedback voltage, a VREG terminal for outputting an internal voltage, and a terminal included in a first terminal group capable of connecting a start terminal of a start capacitor for bootstrap are arranged on the first side, the second side, and the third side, respectively,

the terminals arranged on the fourth side are only terminals other than the first terminal group.