CN112951789A - Wire bonding structure, wire bonding method, and semiconductor device - Google Patents

Wire bonding structure, wire bonding method, and semiconductor device Download PDF

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Publication number
CN112951789A
CN112951789A CN201911269007.2A CN201911269007A CN112951789A CN 112951789 A CN112951789 A CN 112951789A CN 201911269007 A CN201911269007 A CN 201911269007A CN 112951789 A CN112951789 A CN 112951789A
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window
barrier layer
wire bonding
preset area
width
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吴秉桓
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN201911269007.2A priority Critical patent/CN112951789A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8536—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/85375—Bonding interfaces of the semiconductor or solid state body having an external coating, e.g. protective bond-through coating

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

The present application relates to a wire bonding structure, a wire bonding method based on the wire bonding structure, and a semiconductor device formed by the wire bonding method. The lead welding structure comprises a circuit layer formed in a substrate, and a welding pad, a barrier layer and a passivation layer which are sequentially stacked on the circuit layer, wherein the hardness of the barrier layer is greater than that of the welding pad, a first window which exposes the welding pad is arranged in a preset area of the barrier layer, the first window does not exceed the preset area, and the width of the preset area is smaller than that of a welding ball after routing; and the passivation layer is provided with a second window with the width larger than that of the preset area, and all the second windows of the preset area are exposed through the second window. The blocking layer is arranged between the passivation layer and the welding pad, the first windows can be arranged on the blocking layer, the window opening range of the blocking layer is limited, and the welding balls after routing can cover all the first windows, so that the welding balls and the welding pad can be welded, and meanwhile, the welding pad can be prevented from overflowing.

Description

Wire bonding structure, wire bonding method, and semiconductor device
Technical Field
The invention relates to the field of semiconductors, in particular to a lead welding structure, a lead welding method and a semiconductor device.
Background
In back-end processing of semiconductor devices, wire bonding is involved to draw electrical connection terminals from circuit layers within the substrate. In order to protect the circuit layer, a soft metal layer is usually disposed on the circuit layer as a bonding pad, and the solder ball is specifically bonded to the bonding pad. Because the texture of the welding pad is relatively soft, when the welding ball is pressed on the welding pad, on one hand, the metal of the extruded welding pad can be discharged to two sides, so that the welding pad between the welding ball and the circuit layer becomes thin or the welding ball directly acts on the circuit layer, and the circuit layer is broken due to larger impact force; on the other hand, when the squeezed pad metal is discharged to both sides, conductive particles are formed on both sides, which affects the electrical performance of the device.
Disclosure of Invention
Based on the above, the application provides a lead welding structure, a lead welding method and a semiconductor device, which can avoid the influence of the lead welding process on the device performance.
In order to solve the above technical problem, a first technical solution proposed by the present application is:
a wire bonding structure comprising:
a substrate;
a circuit layer formed in the substrate;
the welding pad is formed on the circuit layer and is electrically connected with the circuit layer;
the barrier layer is formed on the welding pad, the hardness of the barrier layer is greater than that of the welding pad, a first window exposing the welding pad is formed in a preset area of the barrier layer, the first window does not exceed the preset area, and the width of the preset area is smaller than that of a welded ball after routing; and
and the passivation layer is formed on the barrier layer, a second window with the width larger than that of the preset region is formed in the passivation layer, and all the preset region is exposed through the second window.
In one embodiment, a first window is formed in a preset area of the barrier layer, and the projection of the first window coincides with the projection of the preset area.
In one embodiment, a first window is formed in a preset area of the barrier layer, the first window is annular, and the outer edge of the first window is overlapped with the edge of the preset area.
In one embodiment, the predetermined area includes an island-shaped area surrounded by the first window, and a width of the island-shaped area is smaller than a width of the solder ball before wire bonding.
In one embodiment, a plurality of first windows arranged at intervals are formed in a preset area of the barrier layer, the first windows are strip-shaped, and the first windows are arranged in parallel.
In one embodiment, a plurality of first windows arranged at intervals are arranged in a preset area of the barrier layer, and the barrier layer of the preset area is in a grid shape.
In one embodiment, the opening width of the second window is larger than the width of the solder ball after routing.
In one embodiment, the width of the preset area is 8-12 μm smaller than that of the solder ball after routing.
The lead welding structure is used for welding the lead on the lead welding structure through a gold wire ball welding process. Firstly, the passivation layer is provided with a second window, and the width of the second window is larger than that of the solder ball after routing, so that the solder ball can smoothly move down to the preset area of the barrier layer and the solder ball is prevented from being welded on the passivation layer by mistake. And secondly, arranging a barrier layer between the passivation layer and the welding pad, arranging a first window in a preset area of the barrier layer, and when the welding ball reaches the barrier layer and presses the welding ball, the welding ball can be welded with the welding pad below through the first window of the barrier layer. Meanwhile, the width of the blocking layer preset area is smaller than that of the welded ball after routing, and the welded ball after routing covers the whole preset area, namely all the first windows, so that the welding pad metal is prevented from overflowing outwards, the welding pad with a certain thickness below the welded ball can be ensured, the circuit layer is prevented from being broken, and the formation of redundant conductive particles can be avoided. Therefore, by forming the above-described wire bonding structure, the influence of the wire bonding process on the electrical properties of the device can be eliminated.
In order to solve the above technical problem, a second technical solution proposed by the present application is:
a method of wire bonding comprising:
obtaining a lead bonding structure, wherein the lead bonding structure is any one of the lead bonding structures;
and aligning the solder balls to the preset area, pressing and routing, so that the routed solder balls cover the preset area to form a lead welded on the solder pads.
According to the lead welding method, the barrier layer is formed inside the lead welding structure, and in the lead welding process, the welded balls after routing can cover all the first windows, so that the welding pad metal is prevented from overflowing outwards, the circuit layer can be prevented from being broken, redundant conductive particles can be prevented from being formed, and the influence of the lead welding process on the electrical property of the device is eliminated.
In order to solve the above technical problem, a third technical solution proposed by the present application is:
a semiconductor device, comprising:
a substrate;
a circuit layer formed in the substrate;
the welding pad is formed on the circuit layer and is electrically connected with the circuit layer;
the barrier layer is formed on the welding pad, the hardness of the barrier layer is greater than that of the welding pad, a first window exposing the welding pad is formed in a preset area of the barrier layer, the first window does not exceed the preset area, and the width of the preset area is smaller than that of a welded ball after routing;
the passivation layer is formed on the barrier layer, a second window with the width larger than that of the preset area is formed in the passivation layer, and all the preset area is exposed through the second window;
the welded ball after routing covers the preset area and is embedded into the welding pad to be welded with the welding pad;
and the lead is connected with the welded ball after routing.
In one embodiment, a preset area of the barrier layer is provided with a first annular window and an island-shaped area surrounded by the first window, and part of the bottom surface of the bonded solder ball is in contact with the island-shaped area.
In one embodiment, a plurality of first windows arranged at intervals are formed in a preset area of the barrier layer, the first windows are strip-shaped, and the first windows are arranged in parallel.
In one embodiment, a plurality of first windows arranged at intervals are arranged in a preset area of the barrier layer, and the barrier layer of the preset area is in a grid shape.
The semiconductor device forms the lead by the lead welding method, wherein a barrier layer is formed between the passivation layer and the welding pad, the welded ball after routing covers the barrier layer and is welded with the welding pad below through the first window, and the metal of the welding pad does not overflow out of the barrier layer, so that the thickness of the welding pad at the bottom of the welded ball is ensured, and redundant conductive particles are not formed, therefore, the semiconductor device welded with the lead still has better electrical property.
Drawings
FIG. 1 is a schematic view illustrating a conventional structure after bonding a lead to a lead bonding structure;
FIG. 2a is a cross-sectional side view of a wire bonding structure according to an embodiment of the present invention;
FIG. 2b is a top view of a wire bonding structure according to an embodiment of the present invention;
fig. 2c is a schematic structural diagram of a semiconductor device formed based on a wire bonding structure according to the first embodiment of the present application;
FIG. 3a is a cross-sectional side view of a wire bonding structure according to a second embodiment of the present application;
FIG. 3b is a top view of a wire bonding structure according to a second embodiment of the present application;
fig. 3c is a schematic structural diagram of a semiconductor device formed based on the wire bonding structure in the second embodiment;
FIG. 4a is a cross-sectional side view of a wire bonding structure in accordance with a third embodiment of the present application;
FIG. 4b is a top view of a wire bonding structure according to a third embodiment of the present application;
fig. 4c is a schematic structural view of a semiconductor device formed based on the wire bonding structure in the third embodiment;
FIG. 5a is a cross-sectional side view of a wire bonding structure according to a fourth embodiment of the present application;
FIG. 5b is a top view of a wire bonding structure according to a fourth embodiment of the present application;
fig. 5c is a schematic structural view of a semiconductor device according to the present application, which is formed based on the wire bonding structure in the fourth embodiment;
fig. 6 is a flowchart illustrating steps corresponding to a wire bonding method according to an embodiment of the present invention.
Description of the reference symbols
110 a circuit layer; 120 pads; 130 a barrier layer; 131 a first window; 132 island-like regions; 140 a passivation layer; 141 a second window; 210 bonding balls after routing; 220 lead wires; a is a preset area.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Fig. 1 is a schematic diagram illustrating a lead soldered on a lead soldering structure in the conventional technology, in which the lead soldering structure includes a circuit layer 110 ', a pad 120 ' and a passivation layer 130 ' stacked in sequence, the passivation layer 130 ' is provided with a window exposing the pad 120 ', the solder ball 210 ' contacts the pad 120 ' through the window, and since the pad 120 ' is soft, the pressed pad 120 ' flows to both sides and overflows outward from a gap between the passivation layer 130 ' and the solder ball 210 ' (as shown by an arrow in fig. 1), so that the thickness of the pad 120 ' at the bottom of the solder ball is thin, the circuit layer 110 ' is likely to break due to a large impact force, and conductive particles are easily formed on the pad overflowing outward, which affects device performance.
To this end, the present application proposes a new wire bonding structure on which the influence of the bonding process on the device performance can be avoided when bonding a wire.
As shown in fig. 2a, the wire bonding structure includes a substrate (not shown) and a circuit layer 110 formed in the substrate, wherein the circuit layer 110 is sequentially stacked with a bonding pad 120, a barrier layer 130 and a passivation layer 140.
The substrate may be a semiconductor substrate, and specifically, may be a silicon substrate. The circuit layer 110 is an electrical device such as a MOS transistor, a diode, a resistor, or a capacitor. The pad 120 is electrically connected to the circuit layer 110 in the lead-out region, and specifically, the pad 120 may be provided only on the circuit layer in the lead-out region. The pad 120 is made of a relatively soft conductive material, such as a metal material, e.g., copper, aluminum, tungsten, etc.
The barrier layer 130 has a hardness greater than that of the pad 120, and can bear the impact of the pad 120 and prevent the pad 120 from overflowing during wire bonding, and the barrier layer 130 may be made of an insulating material or a conductive material, such as one or more of hard materials, such as silicon dioxide, silicon nitride, silicon oxynitride, silicon carbonitride, and metal nitride. A predetermined area a is defined on the barrier layer 130, and the width of the predetermined area a is smaller than the width of the solder ball after Bonding (Bonding), so that the solder ball after Bonding can cover the predetermined area a. When the lead is soldered, the metal wire is heated to form a hot-melt metal sphere, then the metal sphere is pressed on the pad and wire bonding is performed to form the lead, and the metal sphere is pressed to form a flat sphere, so that the coverage area of the solder ball after wire bonding is larger than that of the solder ball before wire bonding. A first window 131 exposing the pad 120 is formed in the predetermined area a of the blocking layer 130, and the first window 131 does not exceed the predetermined area a, i.e., the opening of the first window 131 does not extend out of the predetermined area a. Therefore, when the wire-bonded solder ball covers the predetermined area a, the first window 131 is also covered by the wire-bonded solder ball, and there is no gap between the first window 131 and the wire-bonded solder ball, which can make the pad 120 overflow.
The passivation layer 140 is formed on the barrier layer 130, but does not cover the predetermined region a, that is, the passivation layer 140 is also provided with a second window 141, an opening width of the second window 141 is greater than a width of the predetermined region a, all of the predetermined region a can be exposed through the second window 141, and at this time, all of the first windows 131 and the second windows 141 are communicated. Furthermore, the opening width of the second window 141 is greater than the width of the solder ball after wire bonding, so as to avoid the limitation of the pressing wire bonding of the solder ball, and facilitate the solder ball to smoothly avoid the passivation layer 140 and move down to the barrier layer 130 during the soldering process, thereby avoiding the solder ball from being erroneously soldered on the passivation layer 140.
According to the lead welding structure, the barrier layer is arranged between the welding pad and the passivation layer, the preset area is defined on the barrier layer, the width of the preset area is limited to be smaller than that of the welded ball after routing, the first window is arranged in the preset area and does not exceed the preset area, and all the preset area is exposed through the second window of the passivation layer. In this application, carry out above-mentioned improvement to lead wire welding structure, when carrying out the lead wire welding through gold ball welding process, the solder ball passes through the second window and moves down to the predetermined area of barrier layer, presses the routing to the solder ball, and the solder ball after the routing is the platykurtic and covers whole predetermined area. Because the first window is arranged in the preset area, the welded ball after routing can be welded with the welding pad below through the first window, and because the first window does not exceed the preset area, the welded ball after routing covers the preset area and simultaneously covers all the first windows, and no gap exists between the first window and the welded ball. At the moment, even if the welding pad below the barrier layer is extruded, the welding pad cannot overflow out of the barrier layer, the thickness of the welding pad between the welding ball and the circuit layer is ensured, redundant conductive particles can be prevented from being generated, and the circuit layer can also be prevented from being broken. Therefore, when the welding structure is subjected to lead welding, the electrical property of the device can be ensured not to be influenced by a welding process.
Specifically, the width of the preset area a is smaller than the width of the solder ball after wire bonding, which means that when the solder ball after wire bonding covers the preset area a, the width of the preset area a is smaller than the width of the solder ball after wire bonding on any side section, so that the preset area a is completely covered by the solder ball after wire bonding. Usually, the area covered by the solder balls after wire bonding is circular, the preset area a can also be designed to be circular, and the diameter of the preset area a is smaller than that of the area covered by the solder balls after wire bonding. The width of the solder ball after routing can be known in advance according to a plurality of welding tests, and can also be estimated according to experience. In one embodiment, the width of the predetermined area a is smaller than the width of the solder ball after wire bonding, and the difference between the width of the predetermined area a and the width of the solder ball after wire bonding is in a range of 8 μm to 12 μm, for example, the width of the solder ball after wire bonding is in a range of 30 μm to 50 μm, and the width of the predetermined area a is in a range of 20 μm to 40 μm. Furthermore, the width of the preset area A is larger than or equal to the width of the solder ball before routing, the area of the preset area A is increased as much as possible on the premise that the preset area A can be covered by the solder ball after routing, the windowing area in the preset area A can be increased, and the welding effect of the solder ball and the solder pad is ensured.
Specifically, there are various embodiments for designing the first window 131 in the preset area a, and four embodiments are described in detail below.
Example one
As shown in fig. 2a and 2b, a first window 131 is opened in the preset region a of the barrier layer 130, and a projection of the first window 131 coincides with a projection of the preset region a, that is, the preset region a is completely opened with the first window 131, on the premise that the first window 131 can be completely covered by the wire-bonded bonding pad, the window-opening range of the barrier layer 130 is enlarged as much as possible, and more bonding pads 120 are exposed, so as to increase the contact area between the wire-bonded solder ball and the bonding pad 120, and enhance the bonding effect.
Fig. 2c is a schematic structural diagram of the lead soldering structure shown in fig. 2a and 2b after the leads are soldered, wherein the solder balls 210 after wire bonding completely cover the first windows on the barrier layer 130, so that no gap exists between the solder balls 210 after wire bonding and the barrier layer 130, and therefore, when the solder balls contact the solder pads 120 through the first windows and press the solder pads 120, the solder pads 120 do not overflow the barrier layer 130 to form conductive particles, and meanwhile, a solder pad with a certain thickness is ensured between the solder balls 210 after wire bonding and the circuit layer 110, so as to protect the circuit layer 110.
Example two
As shown in fig. 3a and 3b, a first window 131 is formed in the preset area a, the first window 131 is annular, and further, an outer edge of the first window 131 coincides with an edge of the preset area a. At this time, the predetermined area a further includes an island-shaped area 132 surrounded by the first window 131, and the island-shaped area 132 can buffer and disperse the impact force when the solder ball presses the solder pad 120, so that the impact of the solder ball on the circuit layer 110 is weakened, and the circuit layer 110 is further protected.
Fig. 3c is a schematic structural diagram of the lead soldered structure shown in fig. 3a and 3b after the leads are soldered, wherein the solder balls 210 after wire bonding completely cover the first windows on the barrier layer 130, so that no gap exists between the solder balls 210 after wire bonding and the barrier layer 130, therefore, when the solder balls contact the solder pads 120 through the first windows and press the solder pads 120, the solder pads 120 do not overflow the barrier layer 130 to form conductive particles, and meanwhile, the island regions 132 move downward along with the solder balls and are embedded into the solder pads 120 to form island regions 132', which can buffer and disperse the impact force of the solder balls on the solder pads 120, and retain the solder pads 120 under the solder balls, so that the solder pads 120 at the bottoms of the solder balls have a certain thickness, thereby further enhancing the protection of the circuit layer 110. Furthermore, the width of the island region 132 is smaller than the width of the solder ball before wire bonding, when the solder ball before wire bonding moves down and contacts with the island region 132, a part of the solder ball is opposite to the first window 131, and when the solder ball presses the wire bonding, the solder ball can be ensured to be fully contacted with the solder pad 120, so as to ensure the welding effect.
In one embodiment, the solder balls before wire bonding are approximately spherical, the area covered by the solder balls before wire bonding is circular, the island-shaped area can also be designed to be circular, and the diameter of the island-shaped area is smaller than that of the area covered by the solder balls before wire bonding. In one embodiment, the width of the island 132 is smaller than the width of the solder ball before wire bonding, and the difference between the width of the island 132 and the width of the solder ball before wire bonding is in the range of 8 μm to 12 μm, for example, the width of the solder ball before wire bonding is in the range of 18 μm to 42 μm, and the width of the island 132 is in the range of 10 μm to 30 μm.
EXAMPLE III
In an embodiment, as shown in fig. 4a and 4b, a plurality of first windows 131 may also be formed in the predetermined area a of the barrier layer 130 at intervals, each first window 131 is in a strip shape, and all the first windows 131 are arranged in parallel. At this time, the pads 120 are exposed through the first windows 131, and the bonded solder balls can contact the exposed pads 120 through the first windows 131. Meanwhile, when the solder ball is pressed and wire bonded, the barrier layer between the adjacent first windows 131 can also disperse and buffer the impact force of the solder ball on the solder pad 120, so as to protect the solder pad 120 under the solder ball, so that the solder pad 120 at the bottom of the solder ball has a certain thickness to protect the circuit layer 110 below. Specifically, the barrier layer in the preset area a and the barrier layer outside the preset area a are integrally formed to enhance the degree of buffering the impact force.
Fig. 4c is a schematic structural view of the lead soldering structure shown in fig. 4a and 4b after the leads are soldered, wherein the solder balls 210 after wire bonding completely cover the first windows on the barrier layer 130, so that no gap exists between the solder balls 210 and the barrier layer 130, therefore, when the solder balls 210 contact the solder pads 120 through the first windows and press the solder pads 120, the solder pads 120 do not overflow the barrier layer 130 to form conductive particles, and meanwhile, the barrier layer between the adjacent first windows can buffer and disperse the impact force of the solder balls on the solder pads 120, so as to protect the solder pads 120 under the solder balls, so that the solder pads 120 at the bottoms of the solder balls have a certain thickness, thereby further enhancing the protection of the circuit layer 110. When the barrier layer in the predetermined region a and the barrier layer outside the predetermined region a are integrally formed, the barrier layer in the predetermined region a may be deformed and bent into the pad 120 by the impact of the solder ball.
Example four
As shown in fig. 5a and 5b, a plurality of first windows 131 are formed in the predetermined area a of the barrier layer 130, and the first windows 131 are uniformly distributed along the transverse direction and the longitudinal direction, so that the barrier layer of the predetermined area a is in a grid shape. Fig. 5c is a schematic view of the wire bonding structure shown in fig. 5a and 5b after bonding a wire. The effect of the fourth embodiment is the same as that of the third embodiment, and is not described herein again.
In this application, carry out above-mentioned improvement to lead wire welding structure, when carrying out the lead wire welding through gold ball welding process, the solder ball passes through the second window and moves down to the predetermined region of barrier layer, presses the routing to the solder ball, and the solder ball after the routing can pass through first window and the welding pad welding of below, because first window does not surpass predetermined region again, the solder ball after the routing can cover all first windows, does not have the gap between the solder ball after first window and routing. At the moment, even if the welding pad below the barrier layer is extruded, the welding pad does not overflow out of the barrier layer, the thickness of the welding pad between the welding ball and the circuit layer is ensured, redundant conductive particles can be prevented from being generated, and the circuit layer can be prevented from being broken. Therefore, when the welding structure is subjected to lead welding, the electrical property of the device can be ensured not to be influenced by a welding process.
The present application also relates to a wire bonding method, as shown in fig. 6, including the steps of:
step S610: obtaining a wire bond structure, the wire bond structure comprising: a substrate; a circuit layer formed in the substrate; the welding pad is formed on the circuit layer and is electrically connected with the circuit layer in the lead-out area; the barrier layer is formed on the welding pad, the hardness of the barrier layer is greater than that of the welding pad, a first window exposing the welding pad is formed in a preset area of the barrier layer, the first window does not exceed the preset area, and the width of the preset area is smaller than that of a welded ball after routing; and the passivation layer is formed on the barrier layer, a second window with the width larger than that of the preset area is formed in the passivation layer, and all the preset area is exposed through the second window.
Specifically, the specific description of the wire bonding structure can refer to the above description, and is not repeated herein.
Step S620: and aligning the solder balls to the preset area, pressing and routing, so that the routed solder balls cover the preset area to form a lead welded on the solder pads.
Specifically, utilize high voltage melting gold wire in the twinkling of an eye to form the solder ball, send the solder ball into preset area through first window, press the solder ball and the routing, form the lead wire that welds on the solder pad, at this moment, the solder ball area of coverage after the routing increases, can cover whole preset area, make the gap not exist between solder ball after the routing and the barrier layer, the solder ball welds through first window and the solder pad of below, and the solder pad can not spill over outside the barrier layer after receiving the extrusion yet, can avoid forming unnecessary conductive particle, also can guarantee the thickness of solder pad below the solder ball, avoid the circuit layer to suffer the impact and break. Therefore, in the application, the lead welding is carried out by the method, so that the influence of the welding process on the electrical property of the device can be avoided, and the product yield is improved.
The present application further relates to a semiconductor device, as shown in fig. 2c, the semiconductor device includes a substrate (not shown in the figure) and a circuit layer 110 formed in the substrate, wherein a solder pad 120, a barrier layer 130, and a passivation layer 140 are sequentially stacked on the circuit layer 110, the semiconductor device further includes a solder ball 210 after wire bonding and a lead 220 formed by solder ball wire bonding, wherein the solder ball 210 after wire bonding is soldered to the solder pad 120.
The substrate may be a semiconductor substrate, and specifically, may be a silicon substrate. The circuit layer 110 is an electrical device such as a MOS transistor, a diode, a resistor, or a capacitor. The pad 120 is electrically connected to the circuit layer 110 in the lead-out region, and specifically, the pad 120 may be provided only on the circuit layer in the lead-out region. The pad 120 is made of a relatively soft conductive material, such as a metal material, e.g., copper, aluminum, tungsten, etc.
The barrier layer 130 has a hardness greater than that of the pad 120, and can bear the impact of the pad 120 and prevent the pad 120 from overflowing during wire bonding, and the barrier layer 130 may be made of an insulating material or a conductive material, such as one or more of hard materials, such as silicon dioxide, silicon nitride, silicon oxynitride, silicon carbonitride, and metal nitride. Referring to fig. 2a and 2b, a predetermined area a is defined on the barrier layer 130, and the width of the predetermined area a is smaller than the width of the solder ball after wire bonding, so that the solder ball after wire bonding can cover the predetermined area a. A first window 131 exposing the pad 120 is formed in the predetermined area a of the blocking layer 130, and the first window 131 does not exceed the predetermined area a, i.e., the opening of the first window 131 does not extend out of the predetermined area a.
The passivation layer 140 is formed on the barrier layer 130, but does not cover the predetermined region a, that is, the passivation layer 140 is also provided with a second window 141, an opening width of the second window 141 is greater than a width of the predetermined region a, all of the predetermined region a can be exposed through the second window 141, and at this time, all of the first windows 131 and the second windows 141 are communicated. Furthermore, the opening width of the second window 141 is greater than the width of the solder ball after wire bonding, so as to avoid the limitation of the pressing wire bonding of the solder ball, and facilitate the solder ball to smoothly avoid the passivation layer 140 and move down to the barrier layer 130 during the soldering process, thereby avoiding the solder ball from being erroneously soldered on the passivation layer 140.
The ball bonding forms a lead 220, and the bonded ball 210 covers the predetermined area a and is embedded in the pad 120. It should be noted that the solder ball starts from a hot-melt metal sphere formed by heating a metal wire, and becomes a flat sphere when the wire is pressed on the pad, so that the coverage area of the solder ball after wire bonding is larger than that of the solder ball before wire bonding. A first window 131 exposing the pad 120 is formed in the predetermined area a of the blocking layer 130, and the first window 131 does not exceed the predetermined area a, i.e., the opening of the first window 131 does not extend out of the predetermined area a. Therefore, when the bonded solder ball 210 covers the predetermined area a, the first window 131 is also covered by the bonded solder ball 210, and there is no gap between the first window 131 and the solder ball 210, which can make the pad 120 overflow.
The semiconductor device forms the lead by the lead welding method, wherein a barrier layer is formed between the passivation layer and the welding pad, a first window is arranged on the barrier layer, the welded ball after routing covers the first window and is welded with the welding pad below through the first window, the metal of the welding pad does not overflow out of the barrier layer, the thickness of the welding pad at the bottom of the welded ball is ensured, and redundant conductive particles are not formed, so that the semiconductor device welded with the lead still has better electrical property.
Specifically, the width of the preset area a is smaller than the width of the solder ball after wire bonding, which means that when the solder ball after wire bonding covers the preset area a, the width of the preset area a is smaller than the width of the solder ball after wire bonding on any side section, so that the preset area a is completely covered by the solder ball after wire bonding. Usually, the area covered by the solder balls after wire bonding is circular, the preset area a can also be designed to be circular, and the diameter of the preset area a is smaller than that of the area covered by the solder balls after wire bonding. The width of the solder ball after routing can be known in advance according to a plurality of welding tests, and can also be estimated according to experience. In one embodiment, the width of the predetermined area a is smaller than the width of the solder ball after wire bonding, and the difference between the width of the predetermined area a and the width of the solder ball after wire bonding is in a range of 8 μm to 12 μm, for example, the width of the solder ball after wire bonding is in a range of 30 μm to 50 μm, and the width of the predetermined area a is in a range of 20 μm to 40 μm. Furthermore, the width of the preset area A is larger than or equal to the width of the solder ball before routing, the area of the preset area A is increased as much as possible on the premise that the preset area A can be covered by the solder ball after routing, the windowing area in the preset area A can be increased, and the welding effect of the solder ball and the solder pad is ensured.
In one embodiment, the semiconductor device is formed by bonding wires on the wire bonding structure mentioned in the first embodiment. In the above embodiment, the lead bonding structure is described with reference to the first embodiment, and details are not repeated herein, and the semiconductor device is formed by adding a lead bonded to a pad on the basis of the lead bonding structure. As shown in fig. 2c, the first windows of the barrier layer 130 are completely covered by the solder balls 210 after wire bonding, so that no gap exists between the solder balls 210 and the barrier layer 130, and therefore, when the solder balls 210 contact the bonding pads 120 through the first windows and press the bonding pads 120, the bonding pads 120 do not overflow the barrier layer 130 to form conductive particles, and meanwhile, a bonding pad with a certain thickness is ensured between the solder balls 210 and the circuit layer 110, so as to protect the circuit layer 110.
In an embodiment, as shown in fig. 3a and 3b, the predetermined region a of the barrier layer 130 has a first window 131 in a ring shape and an island region 132 surrounded by the first window 131, that is, the semiconductor device may be formed by bonding wires on the wire bonding structure mentioned in the second embodiment. Specifically, the semiconductor device is additionally provided with a lead wire bonded to the pad on the basis of the lead wire bonding structure, wherein the lead wire bonding structure can refer to the description of the third embodiment, and is not repeated herein. Specifically, as shown in fig. 3c, the first windows of the barrier layer 130 are completely covered by the solder balls 210 after wire bonding, so that no gap exists between the solder balls 210 and the barrier layer 130, therefore, when the solder balls 210 contact the solder pads 120 through the first windows and press the solder pads 120, the solder pads 120 do not overflow the barrier layer 130 to form conductive particles, meanwhile, the island regions 132 move downward under the pressing of the solder balls, and may be embedded into the solder pads 120, and a part of the bottoms of the solder balls 210 after wire bonding is located on the island regions 132. The island regions 132 can buffer and disperse the impact force generated by pressing the solder balls on the solder pads 120, and protect the solder pads 120 under the solder balls, so that the solder pads 120 at the bottoms of the solder balls have a certain thickness, thereby further enhancing the protection of the circuit layer 110.
In an embodiment, as shown in fig. 4a and 4b, a plurality of first windows 131 are formed in the predetermined area a of the barrier layer 130 at intervals, each first window 131 is in a shape of a strip, and all the first windows 131 are arranged in parallel, that is, the semiconductor device is formed by bonding wires on the wire bonding structure mentioned in the third embodiment. For the lead bonding structure, reference may be made to the description of the third embodiment, which is not repeated herein, and the semiconductor device is formed by adding a lead bonded to the pad on the basis of the lead bonding structure. Specifically, as shown in fig. 4c, the solder balls 210 after wire bonding completely cover each first window on the barrier layer 130, so that no gap exists between the solder balls 210 and the barrier layer 130, and therefore, when the solder balls 210 contact the solder pads 120 through the first windows and press the solder pads 120, the solder pads 120 do not overflow the barrier layer 130 to form conductive particles, and meanwhile, the barrier layer between the adjacent first windows can buffer and disperse the impact force of the solder balls on the solder pads 120, so as to protect the solder pads 120 under the solder balls, so that the solder pads 120 at the bottoms of the solder balls have a certain thickness, and further enhance the protection of the circuit layer 110. When the barrier layer in the predetermined region a and the barrier layer outside the predetermined region a are integrally formed, the barrier layer in the predetermined region a may be deformed and bent into the pad 120 by the impact of the solder ball.
In an embodiment, as shown in fig. 5a and 5b, a plurality of first windows 131 are formed in the predetermined area a of the barrier layer 130 at intervals, so that the barrier layer in the predetermined area a is in a grid shape, that is, the semiconductor device is formed by bonding wires on the wire bonding structure mentioned in the fourth embodiment. For the lead bonding structure, reference may be made to the description of the fourth embodiment, which is not repeated herein, and the semiconductor device is formed by adding a lead bonded to the pad on the basis of the lead bonding structure. Specifically, as shown in fig. 5c, the solder balls 210 after wire bonding completely cover each first window on the barrier layer 130, so that no gap exists between the solder balls 210 and the barrier layer 130, and therefore, when the solder balls 210 contact the solder pads 120 through the first windows and press the solder pads 120, the solder pads 120 do not overflow the barrier layer 130 to form conductive particles, and meanwhile, the barrier layer between the adjacent first windows can buffer and disperse the impact force of the solder balls on the solder pads 120, so as to protect the solder pads 120 under the solder balls, so that the solder pads 120 at the bottoms of the solder balls have a certain thickness, and further enhance the protection of the circuit layer 110. When the barrier layer in the predetermined region a and the barrier layer outside the predetermined region a are integrally formed, the barrier layer in the predetermined region a may be deformed and bent into the pad 120 by the impact of the solder ball.
According to the semiconductor device, the barrier layer is formed between the passivation layer and the welding pad, the welded ball after routing covers the barrier layer and is welded with the welding pad below through the first window, the welding pad metal does not overflow out of the barrier layer, the thickness of the welding pad at the bottom of the welded ball is guaranteed, and redundant conductive particles are not formed, so that the semiconductor device welded with the lead still has good electrical performance.
The above examples only show some embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (13)

1. A wire bonding structure, comprising:
a substrate;
a circuit layer formed in the substrate;
the welding pad is formed on the circuit layer and is electrically connected with the circuit layer;
the barrier layer is formed on the welding pad, the hardness of the barrier layer is greater than that of the welding pad, a first window exposing the welding pad is formed in a preset area of the barrier layer, the first window does not exceed the preset area, and the width of the preset area is smaller than that of a welded ball after routing; and
and the passivation layer is formed on the barrier layer, a second window with the width larger than that of the preset region is formed in the passivation layer, and all the preset region is exposed through the second window.
2. The wire bonding structure of claim 1 wherein a first window is defined in a predetermined area of the barrier layer, and a projection of the first window coincides with a projection of the predetermined area.
3. The wire bonding structure of claim 1 wherein a first window is formed in a predetermined area of the barrier layer, the first window having an annular shape and an outer edge of the first window coinciding with an edge of the predetermined area.
4. The wire bonding structure of claim 3 wherein said predetermined area comprises an island surrounded by said first window, said island having a width less than the width of the solder ball prior to wire bonding.
5. The wire bonding structure of claim 1 wherein a predetermined area of the barrier layer has a plurality of first windows spaced apart from each other, the first windows being in the form of strips and the first windows being juxtaposed.
6. The wire bonding structure of claim 1 wherein the barrier layer has a plurality of first windows spaced apart in a predetermined area, and the barrier layer in the predetermined area is in the form of a grid.
7. The wire bonding structure of any one of claims 1 to 6, wherein the opening width of the second window is greater than the width of the bonded solder ball.
8. The wire bonding structure of claim 1 wherein the predetermined area has a width 8 μm to 12 μm less than the width of the ball after wire bonding.
9. A method of wire bonding, comprising:
obtaining a wire bonding structure according to any one of claims 1 to 8;
and aligning the solder balls to the preset area, pressing and routing, so that the routed solder balls cover the preset area to form a lead welded on the solder pads.
10. A semiconductor device, comprising:
a substrate;
a circuit layer formed in the substrate;
the welding pad is formed on the circuit layer and is electrically connected with the circuit layer;
the barrier layer is formed on the welding pad, the hardness of the barrier layer is greater than that of the welding pad, a first window exposing the welding pad is formed in a preset area of the barrier layer, the first window does not exceed the preset area, and the width of the preset area is smaller than that of a welded ball after routing;
the passivation layer is formed on the barrier layer, a second window with the width larger than that of the preset area is formed in the passivation layer, and all the preset area is exposed through the second window;
the welded ball after routing covers the preset area and is embedded into the welding pad to be welded with the welding pad;
and the lead is connected with the welded ball after routing.
11. The semiconductor device of claim 10, wherein the predetermined region of the barrier layer has a first window in a ring shape and an island region surrounded by the first window, and a portion of the bottom surface of the bonded solder ball contacts the island region.
12. The semiconductor device according to claim 10, wherein a plurality of first windows are formed in the predetermined region of the barrier layer, the first windows are in a shape of a strip and are arranged in parallel.
13. The semiconductor device according to claim 10, wherein a plurality of first windows are formed in a predetermined region of the barrier layer, and the barrier layer in the predetermined region is in a grid shape.
CN201911269007.2A 2019-12-11 2019-12-11 Wire bonding structure, wire bonding method, and semiconductor device Pending CN112951789A (en)

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