CN112949230B - Nonlinear circuit macro model extraction method, system and medium - Google Patents
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Abstract
The invention discloses a nonlinear circuit macro model extraction method, which comprises the following steps: acquiring an output track of a nonlinear circuit system and selecting a plurality of unfolding points; generating a plurality of quadratic systems according to the unfolding points, and generating a piecewise polynomial system of the nonlinear circuit system according to the plurality of quadratic systems; reducing the order of the piecewise polynomial system by using a time domain model order reduction method, and constructing an order reduction matrix; according to the method, simulation accuracy of the nonlinear circuit can be improved to a great extent, and errors possibly caused by conversion between a frequency domain and a time domain are avoided in the process of extracting the macro model.
Description
Technical Field
The invention relates to the technical field of circuit simulation, in particular to a nonlinear circuit macro model extraction method, a nonlinear circuit macro model extraction system and a nonlinear circuit macro model extraction medium.
Background
At present, a nonlinear circuit system consisting of an interconnection line and nonlinear components takes the dominant role in an integrated circuit, as the working frequency of the integrated circuit is higher and higher, the interconnection line cannot be regarded as a simple metal wire, and needs to be processed by using a distribution parameter theory of a transmission line, so that mathematical models describing the circuit system become complex, the number of equations is also increased, and therefore, a great amount of calculation time is consumed for simulation and verification in a circuit design stage, in order to solve the problem, the calculation time is generally reduced by adopting the reduction of a logarithmic model, but due to the complexity of a nonlinear function, the mathematical model reduction method for the nonlinear interconnection line system is slow to develop, and the most common nonlinear circuit system model reduction method is an intrinsic orthogonal decomposition (POD) model reduction method and a track segment line (TPWL) sexual model reduction method;
the method for reducing the order of the intrinsic orthogonal decomposition (POD) model can not reduce the order of nonlinear items in a nonlinear circuit system, the calculated amount of a mathematical model of the nonlinear interconnection line system after the order reduction is relatively large in the simulation process, and the aim of reducing the calculated amount can not be really achieved;
the trace segment line (TPWL) sexualization model reduction method is roughly based on the principle that: firstly, an output track of an original system is obtained, a series of expansion points are selected on the output track, at each expansion point, a nonlinear function is linearized by utilizing Taylor expansion, a series of linearization subsystems can be obtained, the series of linearization subsystems are combined by utilizing a weight function, a piecewise linearization system is obtained, and then a model order reduction method of the linearization system is used for order reduction;
since the trajectory piecewise linear (TPWL) linear model reduction method is linearizing at each expansion point, in some cases, the simulation accuracy may not be required, and in addition, the trajectory piecewise linear system is reduced by using the frequency domain model reduction method, a relatively large error may be introduced in the process of converting to the time domain.
Disclosure of Invention
The invention mainly solves the problems that the simulation precision is insufficient and the reduction in the frequency domain is likely to introduce larger errors when the nonlinear circuit is simulated. .
In order to solve the technical problems, the invention adopts a technical scheme that: the nonlinear circuit macro model extraction method comprises the following steps:
acquiring an output track of a nonlinear circuit system and selecting a plurality of unfolding points;
generating a plurality of quadratic systems according to the unfolding points, and generating a piecewise polynomial system of the nonlinear circuit system according to the plurality of quadratic systems;
reducing the order of the piecewise polynomial system by using a time domain model order reduction method, and constructing an order reduction matrix;
and extracting a macro model of the nonlinear circuit system according to the reduced order matrix.
Further, the step of obtaining the output track of the nonlinear circuit system and selecting a plurality of expansion points further includes: acquiring a mathematical model of a nonlinear circuit system, outputting a track according to the mathematical model of the nonlinear circuit system, and selecting a plurality of unfolding points
Further, the step of generating a plurality of secondary systems according to the unfolding point and combining the plurality of secondary systems further includes:
performing Taylor expansion at the expansion point, and taking the first three items after the Taylor expansion to generate the secondary system;
the piecewise polynomial system of the nonlinear circuitry is generated using a weighting function to the combination of the quadratic systems.
Further, the step of reducing the order of the piecewise polynomial system by using a time domain model order reduction method and constructing an order reduction matrix further comprises the steps of:
extracting a variable coefficient of an expansion point: extracting a first variable coefficient and a second variable coefficient at an expansion point of the secondary system;
acquiring a Taylor expansion coefficient: obtaining a Taylor expansion coefficient according to the first variable coefficient and the second variable coefficient;
orthogonalization of taylor expansion coefficients: orthogonalizing the Taylor expansion coefficient to generate an orthogonalization matrix of the expansion point;
and (3) loop execution: circularly executing the steps, generating an orthogonal matrix set when the orthogonal matrix of a plurality of expansion points of the nonlinear circuit system is generated, and executing the step of constructing a reduced order matrix;
constructing a reduced order matrix: and executing singular value decomposition on the orthogonal matrix set, extracting at least one column of information of the left singular vector matrix, and generating and constructing a reduced-order matrix.
Further, the step of extracting a macro model of the nonlinear circuitry from the reduced order matrix further comprises: and replacing the parameters of the nonlinear circuit system with the reduced order matrix to obtain a macro model of the nonlinear circuit system.
Further, the step of extracting the expansion point variable coefficient further includes: and obtaining the first variable parameter according to the nonlinear circuit system, and obtaining the second variable parameter according to the first variable parameter by using a recurrence formula.
Further, the step of orthogonalizing the taylor expansion coefficients further includes: performing Schmidt orthogonalization on the Taylor expansion coefficient to obtain the orthogonalization matrix.
Further, the step of constructing a reduced order matrix further comprises: and decomposing the orthogonal matrix set into a left singular vector, a right singular vector and a diagonal matrix by using singular value decomposition, extracting at least one front column of the left singular vector, and generating the reduced order matrix.
The invention also provides a nonlinear circuit macro model extraction system, which is characterized by comprising: the system comprises an unfolding point acquisition module, a secondary module and a reduction module;
the expansion point acquisition module is used for acquiring an output track of the nonlinear circuit system and generating a plurality of expansion points;
the secondary module is used for generating a secondary system according to the unfolding point;
the order reduction module is used for performing time domain order reduction on the combined quadratic system, generating an order reduction system according to the orthogonal matrix constructed in the time domain, and extracting a macro model of the nonlinear circuit system according to the order reduction system.
The invention also provides a computer readable storage medium storing a computer program which, when executed by a processor, implements the nonlinear circuit macro model extraction method steps.
The beneficial effects of the invention are as follows:
1. according to the nonlinear circuit macro model extraction method, a plurality of expansion points are selected on the nonlinear circuit system output track, secondary expansion is carried out at each expansion point, the secondary subsystems at each expansion point are combined through a weight function, model reduction is carried out on the combined secondary systems, and simulation precision of the extracted macro model is improved.
2. The invention uses the time domain model order reduction method to extract the macro model of the nonlinear circuit, thereby avoiding errors possibly introduced in the process of converting the frequency domain model order reduction method into the time domain after obtaining the frequency domain macro model.
3. The nonlinear circuit macro model extracted by the invention can effectively approximate to the original nonlinear circuit system in the simulation verification process, and the macro model is obtained.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a non-linear circuit macro model extraction method according to embodiment 1 of the present invention;
FIG. 2 is a nonlinear interconnection system of the nonlinear circuit macro model extraction method according to embodiment 1 of the present invention;
FIG. 3 is a graph showing the comparison of the output of the original system and the reduced order system of the nonlinear circuit macro model extraction method according to the embodiment 1 of the present invention;
FIG. 4 is a graph of output relative error of the nonlinear circuit macro model extraction method according to embodiment 1 of the present invention;
fig. 5 is a nonlinear circuit macro model extraction system according to embodiment 2 of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
Example 1
In the prior art, macro model extraction is performed on a nonlinear circuit system, most of processing methods are to select an unfolding point on a track of a linear function to linearize, generate a plurality of linear subsystems, and use a weight function combination to obtain a piecewise linearization system, for example,
the formula is a mathematical model of a nonlinear circuit system, wherein x (t) epsilon R (n x 1) represents node voltage or branch current in the circuit, f (x (t)) represents a nonlinear function of the nonlinear circuit, b epsilon R (n x 1) represents an input matrix of the circuit system, u (t) represents an input of the circuit system, y represents an output of the circuit, c epsilon R (1 x n) represents an output matrix of the system, E is a coefficient matrix, G is an association matrix formed by capacitance and inductance values, and n represents a connection relation between components in the circuit system.
Selecting a spreading point { a } of a nonlinear circuit system 0 ，a 1 ，……a n-1 Re-use of the weighting function Σ i ω i The method includes the steps of (1) dividing the expansion point into a plurality of linear subsystems, wherein each subsystem contains a respective weight, adding the weights of all the linear subsystems to be 1, namely converting a nonlinear circuit system into a plurality of linear subsystems, converting a nonlinear mathematical model into a linear mathematical model, so that the solution is simple, but the circuit simulation solution precision is influenced by the mode, the information loss is more, and the time domain characteristics of the nonlinear circuit system are important.
Therefore, the present invention proposes a method for extracting a nonlinear circuit macro model according to the above two problems, please refer to fig. 1, comprising the following steps:
to solve nonlinear circuitry line at the point of expansionThe problem of influencing simulation precision is caused by sexualization, the nonlinear function f (x) of a nonlinear circuit system at each expansion point is expanded by using Taylor, the first three terms after the Taylor expansion are taken, the nonlinear circuit system is subjected to secondary operation, and the nonlinear circuit system is expressed as follows
Wherein A is i Jacobian matrix, H, for a nonlinear system at the expansion points i For the Hession matrix of the nonlinear system at the expansion point, obtaining the piecewise polynomial system of the nonlinear circuit system
Thus, the calculation amount of the secondary system is larger than that of the piecewise linearization system, but the calculation accuracy is improved greatly.
In order to solve the problem of nonlinear circuitry time domain characteristic loss caused by nonlinear circuitry reduction in frequency domain, it is proposed to derive its second coefficient of variation g at the expansion point in a quadratic form in nonlinear circuitry k First variable coefficient b k Then constructing a reduced order matrix of the whole circuit system by using an unfolding system, taking an example below, and selecting an unfolding point a 0 In the form of a secondary form of
Wherein the method comprises the steps of
Since we only perform model reduction in the time domain, we choose the value of t of x (t) of the nonlinear circuit system to be 0, and when t=0, the taylor expansion form of the nonlinear circuit system is as follows
Bringing the formula into nonlinear circuitry at the deployment point a 0 In the secondary form of +.>
Wherein g k ,b k Taylor expansion coefficients g for g (x), u (t), respectively k ,b k And b k Can be derived from u (t), so g will be k With b k Expressed because of the reason according to the formula
Therein, wherein
Therefore, when k=0, g 0 ＝0；
When k=1, the number of the groups,
when k is greater than 1 and is equal to,
will g k And b k Is brought into the expression of (2)
The method can obtain the following steps:
according to the recursive formula, a spreading point a set by us is obtained 0 At x (t) when t=0, the first m term coefficients { q for taylor expansion 0 ,q 1 ,…,q m-1 }，The first M term taylor expansion coefficients of x (t) when t=0 are recorded as M, and Schmidt orthogonalization operation is performed on M to obtain an orthogonalization matrix V 0 So that the orthogonal matrix, i.e. the quadratic form of the nonlinear circuitry, is at the expansion point a 0 An orthogonal matrix at;
similarly, we can obtain a series of expansion points { a } of the nonlinear circuit system in the quadratic form by adopting the same method 0 ，a 1 ，……a n-1 An orthogonal matrix set denoted N, a singular value decomposition SVD more conventional to matrix N, denoted [ U ΣL ]]＝svd([V 0 ,V 1 ,…,V n-1 ]) Wherein, the matrix U epsilon R n×n Is the left singular vector of matrix N, Σ ε R n×r Diagonal matrix composed of singular values of matrix N, L.epsilon.R r×r In SVD, the values in Σ are singular values of the matrix N and are arranged in descending order from large to small, so that the front R columns of the left singular vector matrix U contain most of information of the matrix N, and the front R column information is extracted to construct a reduced order matrix V, V epsilon R n×r 。
After obtaining the reduced order matrix of the nonlinear circuit system, executing a reduced order process to make x r ＝V T x，E r ＝V T EV∈R r×r ，
G ir ＝V T G i V∈R r×r ，A ir ＝V T A i V∈R r×r ,b ir ＝V T b i ∈R r×1 ，c r ＝cV∈R 1×r Replacing parameters in the nonlinear circuit system with the above reduced order process to obtain a macro model of the nonlinear circuit system after the reduction of the order, wherein ∈10>
Referring to fig. 2 to 4, the following further description of the embodiments is provided in connection with specific practical situations, and validity verification;
original system model building is performed on a nonlinear interconnection line system in the embodiment, and order reduction is performed on a 1806-order nonlinear circuit system:
this nonlinear circuitry has the form:
wherein x (t) εR (1806×1) represents the time domain relation of node voltage or branch current in the nonlinear circuit, f (x (t)) represents the nonlinear function of the nonlinear circuit, b εR (1806×1) represents the input matrix of the circuit system, u (t) represents the input of the circuit system, y represents the output of the circuit, c εR (1×1806) represents the output matrix of the system, E is a coefficient matrix, consists of capacitance and inductance values, G is an associated matrix, represents the connection relation between components in the circuit system, n is the scale of the circuit system, wherein n=1806, in the design process of the integrated circuit, multiple simulation verification is sometimes needed to meet the design requirement, and the nonlinear circuit needs a long time to be difficult to meet the timeliness requirement of the circuit design when performing multiple simulation verification.
So through the equation, the output track of the nonlinear circuit system is obtained, and a series of expansion points { a } are selected on the track 0 ，a 1 ，……a n-1 The original nonlinear circuitry is arranged at each expansion point { a } 0 ，a 1 ，……a n-1 Taylor expansion is carried out, the quadratic term of the taylor expansion is taken, and then the combination of the quadratic system at each expansion point of the weight function is utilized:
aiming at the problem of error rise caused by time domain-frequency domain conversion, a mode of time domain model reduction is provided to a 0 The example of a quadratic system obtained at the point of expansion:
wherein the method comprises the steps of
At t=0, the original nonlinear circuitry position variable x (t) is obtained using taylor expansion,
bringing this formula to a 0 The secondary system obtained by the expansion point is obtained
Wherein g k ,b k Respectively g (x), u (t) is the taylor expansion coefficient,
the following requirement is g k ,b k . At the position of
u (t) is known, so b k Can be obtained.
The following finds g k Because of
Therein, wherein
Therefore, when k=0, g 0 ＝0；
When k=1, the number of the groups,
when k is greater than 1 and is equal to,
will g k And b k Is brought into the expression of (2)
The method can obtain the following steps:
according to the formula, the first m term Taylor expansion coefficients { q } of the unknown variable x (t) at t=0 in the original nonlinear circuit are obtained 0 ,q 1 ,…,q m-1 Further get matrix M, note M= [ q ] 0 ,q 1 ,…,q m-1 ]Schmidt orthogonalization is carried out on the matrix M to obtain a nonlinear circuit system at the unfolding point a 0 The quadratic system reduced order matrix V 0 The nonlinear circuit system is at the unfolding point a 0 The reduced order matrix at the same time can be used for the nonlinear circuit system at all expansion points { a } 0 ，a 1 ，……a n-1 Generating a reduced order matrix, and setting the reduced order matrix of all the expansion points as a matrix N, wherein the matrix N= [ V ] 0 ,V 1 ,…,V n-1 ]The matrix N is subjected to a more conventional singular value decomposition SVD, expressed as [ U ΣL ]]＝svd([V 0 ,V 1 ,…,V n-1 ]) Wherein, the matrix U epsilon R n ×n Is the left singular vector of matrix N, Σ ε R n×r Diagonal matrix composed of singular values of matrix N, L.epsilon.R r×r In SVD, the values in Σ are singular values of the matrix N and are arranged in descending order from large to small, so that the front R columns of the left singular vector matrix U contain most of information of the matrix N, and the front R column information is extracted to construct a reduced order matrix V, V epsilon R n×r In this embodiment, r=30 is taken to obtain a reduced order matrix V εR 1806×30 After that, the secondary combined system
The coefficient matrix and the variables are replaced,
x r ＝V T x，E r ＝V T EV∈R 30×30 ，
G ir ＝V T G i V∈R 30×30 ，A ir ＝V T A i V∈R 30×30 ,b ir ＝V T b i ∈R 30×1 ，c r ＝cV∈R 1×30 a reduced order system of piecewise polynomial system expansion at the expansion point of the nonlinear circuitry is obtained,
the input in the simulation process of the original nonlinear system and the system obtained after the reduction is pi/4 x (sin (pi x 2*t) +1/3 x sin (3 x pi x 2 x t)), and the output comparison graph of the two systems is fig. 3, where pi is the english abbreviation of the perimeter rate:
in order to consider the approximation degree between the two system outputs, we calculate the relative error between the reduced system and the original system output, and the relative error calculation formula is as follows
Wherein y is the output of the original nonlinear system, y r For reduced system output, the relative error map is shown in fig. 4:
the system after the order reduction can be well approximate to the original nonlinear system by outputting the comparison graph 3 and the relative error graph 4, the order of the system after the order reduction is 30, and compared with 1806 order of the original nonlinear system, the system after the order reduction is greatly reduced in simulation calculation amount. The purpose of reducing the calculated amount under the condition of a certain precision is achieved.
Example 2
An embodiment of the present invention provides a nonlinear circuit macro model extraction system, please refer to fig. 5, including:
the system comprises an unfolding point acquisition module, a secondary module and a reduction module;
the expansion point acquisition module is used for acquiring a nonlinear circuit system, selecting a plurality of expansion points according to the output track of the nonlinear circuit system, dividing the continuous nonlinear circuit system by the expansion point acquisition module, and converting the divided nonlinear circuit system into linear output, wherein the requirement of circuit simulation precision cannot be met, so that the nonlinearity is required to be secondarily converted;
the quadratic module is provided with a Taylor formula unit, because the Taylor formula is a formula which uses the information of a function at a certain point to describe values nearby the certain point, if the function is smooth enough, under the condition that the derivative value of each order of the function at the certain point is known, the Taylor formula can use the derivative values as coefficients to construct a polynomial to approximate the values of the function in the neighborhood of the certain point, the Taylor formula also gives the deviation between the polynomial and the actual function value, so that the more residual terms are obtained after the expansion point is subjected to the Taylor expansion, the more accurate the simulation is, the Taylor quadratic expansion is performed at the expansion point for balancing the simulation precision and the simulation speed, the quadratic module performs the Taylor expansion at the expansion point of the nonlinear circuit according to the expansion point, so as to obtain a quadratic circuit model similar to the nonlinear circuit system, and the Taylor formula after the expansion is brought into the quadratic nonlinear circuit system to obtain a matrix M.
The method comprises the steps that a reduced order module obtains a matrix M, the reduced order module is provided with a Schmidt orthogonalization unit and an SVD unit, the Schmidt orthogonalization unit orthogonalizes the matrix M and generates a reduced order matrix, the Schmidt orthogonalization unit reduces orders of all expansion points and generates a reduced order matrix set N, the SVD unit generates left singular vectors, right singular vectors and diagonal matrixes according to the N, the SVD unit controls front r columns of the left singular vector matrixes to construct a reduced order matrix V according to the diagonal matrixes, and after the reduced order matrix is obtained, the reduced order module replaces a quadratic nonlinear circuit system to obtain a macro model of a reduced order system expanded by a final piecewise polynomial system.
Based on the same inventive concept as the method in the previous embodiments, the present embodiments also provide a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the steps of a nonlinear circuit macro model extraction method as disclosed above.
The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.
It will be appreciated by those of ordinary skill in the art that all or part of the steps of implementing the above embodiments may be implemented by hardware, or a program implemented by a program to instruct related hardware may be stored in a computer readable storage medium, where the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes or direct or indirect application in other related technical fields are included in the scope of the present invention.
Claims (7)
1. The nonlinear circuit macro model extraction method is characterized by comprising the following steps of:
acquiring an output track of a nonlinear circuit system and selecting a plurality of unfolding points;
performing Taylor expansion at the expansion point, and taking the first three items after the Taylor expansion to generate a secondary system; combining the quadratic systems by using a weight function to generate a piecewise polynomial system of the nonlinear circuitry;
reducing the order of the piecewise polynomial system by using a time domain model order reduction method, and constructing an order reduction matrix;
replacing parameters of the nonlinear circuit system with the reduced order matrix to obtain a macro model of the nonlinear circuit system;
the step of reducing the order of the piecewise polynomial system by using a time domain model order reduction method and constructing an order reduction matrix comprises the following steps:
extracting a variable coefficient of an expansion point: extracting a first variable coefficient and a second variable coefficient at an expansion point of the secondary system;
acquiring a Taylor expansion coefficient: obtaining a Taylor expansion coefficient according to the first variable coefficient and the second variable coefficient;
orthogonalization of taylor expansion coefficients: orthogonalizing the Taylor expansion coefficient to generate an orthogonalization matrix of the expansion point;
and (3) loop execution: circularly executing the steps, generating an orthogonal matrix set when the orthogonal matrix of a plurality of expansion points of the nonlinear circuit system is generated, and executing the step of constructing a reduced order matrix;
constructing a reduced order matrix: and executing singular value decomposition on the orthogonal matrix set, extracting at least one column of information of the left singular vector matrix, and generating and constructing a reduced-order matrix.
2. The nonlinear circuit macro model extraction method according to claim 1, wherein: the step of obtaining the output track of the nonlinear circuit system and selecting a plurality of unfolding points further comprises the steps of: and acquiring a mathematical model of the nonlinear circuit system, outputting a track according to the mathematical model of the nonlinear circuit system, and selecting a plurality of unfolding points.
3. The nonlinear circuit macro model extraction method according to claim 1, wherein: the step of extracting the expansion point variable coefficient further comprises the following steps: and obtaining the first variable parameter according to the nonlinear circuit system, and obtaining the second variable parameter according to the first variable parameter by using a recurrence formula.
4. The nonlinear circuit macro model extraction method according to claim 1, wherein: the step of orthogonalizing the taylor expansion coefficients further comprises: performing Schmidt orthogonalization on the Taylor expansion coefficient to obtain the orthogonalization matrix.
5. The nonlinear circuit macro model extraction method according to claim 1, wherein: the step of constructing the reduced order matrix further comprises: decomposing the set of orthogonal matrices into left singular vectors using singular value decomposition, extracting at least one front column of the left singular vectors, and generating the reduced order matrix.
6. A nonlinear circuit macro model extraction system employing the method of claim 1, comprising: the system comprises an unfolding point acquisition module, a secondary module and a reduction module;
the expansion point acquisition module is used for acquiring an output track of the nonlinear circuit system and generating a plurality of expansion points;
the secondary module is used for generating a secondary system according to the unfolding point;
the order reduction module is used for performing time domain order reduction on the combined quadratic system, generating an order reduction system according to the orthogonal matrix constructed in the time domain, and extracting a macro model of the nonlinear circuit system according to the order reduction system.
7. A computer readable storage medium storing a computer program, characterized in that the computer program, when executed by a processor, implements the nonlinear circuit macro model extraction method steps of any one of claims 1-5.
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