CN112948291A

CN112948291A - Data transmission method, electronic device and readable storage medium

Info

Publication number: CN112948291A
Application number: CN201911266783.7A
Authority: CN
Inventors: 不公告发明人
Original assignee: Cambricon Technologies Corp Ltd
Current assignee: Cambricon Technologies Corp Ltd
Priority date: 2019-12-11
Filing date: 2019-12-11
Publication date: 2021-06-11

Abstract

The application relates to a data transmission method, a data transmission device, electronic equipment and a readable storage medium.

Description

Data transmission method, electronic device and readable storage medium

Technical Field

The present application relates to the field of computer technologies, and in particular, to a data transmission method, an electronic device, and a readable storage medium.

Background

With the continuous development of neural networks and big data, more and more special processing chips are gradually appeared, and the special processing chips are involved in large amount of data transmission when processing relevant data.

Generally, because the data volume of the heavy-weight data such as the neural network is large, when the dedicated processing chip performs data transmission, a Direct Memory Access (DMA) method is often adopted to perform data transmission, and when the DMA is adopted to perform data transmission, the DMA controller directly manages the bus to realize data transmission. Before data is transferred, the CPU gives the DMA controller the bus control right, and after the data transfer is finished, the DMA controller immediately gives the bus control right back to the CPU. That is, a complete DMA transfer process must go through 4 steps of DMA request, DMA response, DMA transfer, and DMA end.

However, the data transmission of the dedicated processing chip often involves multiple transmissions of packet data, and the data transmission using the above method is inefficient.

Disclosure of Invention

In view of the foregoing, it is desirable to provide a data transmission method, device, electronic device and readable storage medium with high transmission efficiency.

In a first aspect, a method for data transmission includes:

when the data volume of the data to be transmitted is smaller than a preset transmission threshold value, determining a target base address register BAR for the data to be transmitted;

mapping data to be transmitted to a first address segment of a target memory for storage through a target BAR; the first address segment comprises a target initial address corresponding to the data to be transmitted.

In one embodiment, the mapping, by the target BAR, the data to be transmitted onto the first address segment for storage includes:

determining the data volume of current transmission according to the target BAR and the target initial address corresponding to the data to be transmitted;

mapping the currently transmitted data volume to a first address field for storage;

and updating the corresponding target starting address of the data to be transmitted, and determining the data volume of the current transmission according to the target BAR and the target starting address corresponding to the data to be transmitted until the transmission of the data to be transmitted is completed.

In one embodiment, the determining the currently transmitted data size according to the target BAR and the target start address corresponding to the data to be transmitted includes:

acquiring a current initial address of a target BAR;

determining the transmittable data volume according to the size of the target BAR, the current starting address of the target BAR and the target starting address of the data to be transmitted;

and determining the data volume of the current transmission according to the data volume of the data to be transmitted and the transmittable data volume.

In one embodiment, the method further comprises:

acquiring a second address field of the target BAR mapped on the target memory; the second address field is an address field on the target memory obtained by the target BAR through one-time mapping;

if the second address segment intersects with a target initial address corresponding to the data to be transmitted, mapping the data to be transmitted to the first address segment through the target BAR for storage;

and if the second address segment is not intersected with the target initial address corresponding to the data to be transmitted, controlling the target BAR to slide until the second address segment of the target BAR is intersected with the target initial address corresponding to the data to be transmitted.

In one embodiment, if the second address segment does not intersect with the target start address corresponding to the data to be transmitted, the current start address of the target BAR is determined, and the target BAR is controlled to slide from the current start address.

In one embodiment, the method further comprises:

and after the data to be transmitted is mapped to the first address segment for storage through the target BAR according to the target starting address, executing data synchronization operation to confirm that the currently transmitted data volume is stored in the first address segment.

In one embodiment, the determining the target base address register BAR for the data to be transmitted includes:

acquiring the semaphore of each BAR in the BAR set; the semaphore is used to indicate whether the BAR is in an idle state;

and determining the BAR in the idle state as a target BAR according to the semaphore of each BAR.

In one embodiment, the determining the BAR in the idle state as the target BAR includes:

when there are a plurality of BARs in the idle state, the BARs in the idle state in the previous order are determined as the target BARs according to a preset order.

In one embodiment, if there is no BAR in the BAR set in the idle state, the method further includes:

acquiring the number of waiting tasks of each BAR, and taking the BAR with the minimum number of waiting tasks as a target BAR;

and when the semaphore of the target BAR indicates that the target BAR is in an idle state, mapping the data to be transmitted to the first address segment through the target BAR for storage.

In a second aspect, a data transmission apparatus, the apparatus comprising:

the selection module is used for determining a target base address register BAR for the data to be transmitted when the data volume of the data to be transmitted is smaller than a preset transmission threshold value; the data to be transmitted is transmission data stored in the first processor;

the mapping module is used for mapping the data to be transmitted to a first address segment of the target memory for storage through the target BAR; the first address segment comprises a target initial address corresponding to the data to be transmitted.

In a third aspect, the present application further provides an electronic device, which includes a memory and a processor, where the memory stores a computer program, and the processor implements the steps of the data transmission method when executing the computer program.

In a fourth aspect, the present application also provides a readable storage medium, on which a computer program is stored, which computer program, when being executed by a processor, realizes the steps of the above data transmission method.

According to the data transmission method, the device, the electronic equipment and the readable storage medium, when the data volume of the data to be transmitted is smaller than a preset transmission threshold value, the target base address register BAR is determined for the data to be transmitted, and the data to be transmitted is mapped to the first address segment through the target BAR to be stored, wherein the first address segment is an address segment used for storing the data to be transmitted on the target memory, and the first address segment comprises the target starting address corresponding to the data to be transmitted, so that when packet data transmission is carried out, the output to be transmitted can be directly mapped to the first address segment through the target BAR to be stored, the DMA is not required to be started for carrying out data transmission, complex transmission steps such as DMA request, DMA response, DMA transmission and DMA ending are avoided, and the efficiency of packet data transmission is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a diagram of an exemplary data transmission method;

FIG. 2 is a flow diagram illustrating a method for data transmission according to one embodiment;

FIG. 2a is a schematic diagram of a BAR set in one embodiment;

FIG. 3 is a flow chart illustrating a data transmission method according to another embodiment;

FIG. 3a is a diagram illustrating a mapping relationship between BARs and memory space in an embodiment;

FIG. 4 is a flow chart illustrating a data transmission method according to another embodiment;

FIG. 5 is a flow chart illustrating a data transmission method according to another embodiment;

FIG. 6 is a flow chart illustrating a data transmission method according to another embodiment;

FIG. 7 is a flow diagram illustrating a method for data transmission according to one embodiment;

FIG. 8 is a block diagram showing the structure of a data transmission apparatus according to an embodiment;

FIG. 9 is a block diagram showing the construction of a data transmission apparatus according to another embodiment;

FIG. 10 is a block diagram showing the construction of a data transmission apparatus according to another embodiment;

fig. 11 is a block diagram showing the construction of a data transmission apparatus according to another embodiment;

fig. 12 is a block diagram showing the structure of a data transmission device according to another embodiment.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first," "second," "third," and "fourth," etc. in the description and claims of this application and the accompanying drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The data transmission method provided by the application can be applied to electronic equipment such as a mainboard and computer equipment, and the electronic equipment can be isomorphic electronic equipment and can also be heterogeneous electronic equipment. Alternatively, when the data transmission method is used for a homogeneous electronic device, the data transmission method may be used for data transmission between different memories of the electronic device. For example, the data transmission between the on-chip memory and the off-chip memory of the electronic device may adopt the data transmission method described above.

Optionally, the data transmission method provided by the present application may be applied to heterogeneous electronic devices. As shown with reference to fig. 1, the electronic device may include a first processor 11, a second processor 12, and a first memory 13. Wherein the first processor may be a general purpose processor and the second processor may be a special purpose processor. The first processor 11 and the second processor 12 may be, but are not limited to, one of the following combinations: a CPU (central Processing unit) and an artificial intelligence processor, a CPU and a DSP (Digital Signal Processing), a CPU and a GPU (image processor), and the like, which are not particularly limited herein.

Each processor may be correspondingly provided with a memory, wherein the first processor may be correspondingly provided with a first memory 13, the first memory 13 may be used for storing a computer program, and the first processor 11 may realize the above data transmission method when executing the computer program. Further, the first memory 13 may also be used for storing data, which may be voice data, image data or text data, etc. The data stored in the first memory 13 can be transferred to a second memory 14 correspondingly disposed to the second processor 12, so that the second processor can perform operations such as voice processing, image processing, or natural voice processing using the corresponding data. Further, the second processor 12 may also transmit its processing results back to the first memory 13 through the second memory 14.

In an embodiment, as shown in fig. 2, the present application provides a data transmission method, when the data volume of the data to be transmitted is small, a Base Address Register (BAR) may be used to implement data transmission, and at this time, DMA does not need to be started, so that the data transmission speed and efficiency may be improved. That is to say, when the data volume of the data to be transmitted is small, the first address segment of the memory space corresponding to the data to be transmitted can be determined and obtained through the target BAR for storage. Specifically, taking the example that the method is applied to the electronic device shown in fig. 1 as an example, the method may include the following steps:

s101, when the data volume of the data to be transmitted is smaller than a preset transmission threshold value, determining a target base address register BAR for the data to be transmitted.

The data to be transmitted may be transmission data required for machine learning, and may be input data and/or output data of network layers that can implement the above neural network related operations, including but not limited to convolutional layers, pooling layers, full-link layers, activation layers, and the like. The preset transfer threshold may be a data amount threshold obtained according to a setting instruction input by the user, and for example, when the setting instruction input by the user indicates that the preset transfer threshold is 256KB, the preset transfer threshold may be set to 256 KB. At this time, if the data amount of the data to be transmitted is less than 256KB, a Base Address Register (BAR) may be determined for the data to be transmitted. The target BAR enables address mapping with the target memory such that the target BAR can be mapped to an address segment on the target memory as a target memory address.

Generally, the BAR exists in a BAR set, for example, as shown in fig. 2a, the BAR set includes 12 BARs belonging to 4 virtual function modules (VFs), each VF has 3 BARs, each BAR is 0, BAR2, BAR4, and each BAR has a size of 16MB), that is, as shown in fig. 2a, the BAR set includes 12 BARs, each BAR has a size of 16MB, that is, as shown in fig. 2a, each BAR set includes 12 BARs, namely, VF0_ BAR0, VF0_ BAR2, VF0_ BAR4, VF1_ BAR0, VF1_ BAR2, VF1_ BAR4, VF2_ BAR0, VF2_ BAR2, VF2_ BAR4, VF3_ BAR0, VF3_ BAR2, and VF3_ BAR4, and each BAR may have a size of 16 MB. Each BAR has its corresponding physical address, for example, taking VF0_ BAR0 physical address (phy _ VF0_ BAR0) as an example, the address is the starting physical address of the BAR, and then the starting physical address of the BAR is 16MB × 4 continuous physical address space, that is, the starting physical addresses of VF1_ BAR0, VF2_ BAR0, and VF3_ BAR0 are phy _ VF0_ BAR0+16M, phy _ VF0_ BAR0+32 _ VF 32M, phy _ VF0_ BAR0+48M, respectively. The status information of each BAR may be recorded in sriov _ BAR, and information such as a start virtual address of the BAR, a wait task number wait _ count of the BAR, and a semaphore window _ sem may also be recorded in sriov _ BAR. Continuing with the example that the BAR set includes 12 BARs, the sriov _ BAR records the state information of the 12 BARs through the sriov _ arr [12], and initializes the attribute value of the sriov _ BAR in the sriov _ arr array when the driver is loaded. Determining the target base address register BAR for the data to be transmitted may be a process of selecting a target BAR from the set of BARs.

S102, mapping data to be transmitted to a first address segment of a target memory for storage through a target BAR; the first address segment comprises a target initial address corresponding to the data to be transmitted.

The first address segment may be an address space in which data to be transmitted is stored in a target memory, and the target memory may be the first memory or the second memory in fig. 1. Optionally, the current storage location of the data to be transmitted may be a first memory, the target storage location of the data to be transmitted may be a second memory, and the first address segment may be an address space of the data to be transmitted in the second memory. The first address segment may be determined by an alloc function before data transmission is performed, so that the first address segment includes a target start address dev _ address of the data to be transmitted, and there is sufficient memory space for storing the data to be transmitted.

On the basis of the above S101, when the target BAR is determined, the target BAR may be mapped to an address on the target memory as a target memory address, and then the data to be transmitted may be carried from the source address to the target memory address through a data migration instruction (e.g., MOVE instruction or COPY instruction), so as to map the data to be transmitted to the first address segment of the target memory for storage, thereby implementing transmission of the data to be transmitted between the first memory and the second memory through the target BAR. Optionally, the second memory may be a DDR. Hereinafter, the target memory is exemplified as DDR.

An implementation of the data transmission method is given here by way of example only. In other embodiments, the target memory may also be a first memory, and the current storage location of the data to be transmitted may be a second memory.

According to the data transmission method, when the data volume of the data to be transmitted is smaller than a preset transmission threshold value, a target Base Address Register (BAR) is determined for the data to be transmitted, and the data to be transmitted is mapped to a first address segment of a target memory through the target BAR to be stored; the first address segment comprises a target starting address corresponding to the data to be transmitted, so that when packet data transmission is carried out, the output to be transmitted can be directly mapped to the first address segment through the target BAR for storage, DMA does not need to be started for data transmission, complex transmission steps such as DMA requests, DMA responses, DMA transmission and DMA ending are avoided, and the packet data transmission efficiency is improved.

As can be seen from the above description, a BAR generally exists in a BAR set, as shown in fig. 2a, the BAR may dynamically establish a mapping relationship with a storage address on a target storage, a starting address BAR _ address of a memory space corresponding to the BAR, and a terminating address of the memory space corresponding to the BAR may be an address obtained according to a size BAR _ size of the BAR, for example, the terminating address on the storage corresponding to the BAR may be a sum of the starting address BAR _ address and the size BAR _ size of the BAR. The first address segment of the memory space corresponding to the data to be transmitted may be an address of the target BAR directly mapped on the memory space, or an address obtained through sliding window processing when the storage amount corresponding to the address of the target BAR directly mapped on the memory space is smaller than the data amount of the data to be transmitted.

Fig. 3 is a schematic flow chart of a data transmission method in an embodiment, which relates to a process of how to map data to be transmitted to a first address segment for storage through a target BAR, and as shown in fig. 3, a possible implementation method of S102 "mapping data to be transmitted to the first address segment for storage through the target BAR" includes the following steps:

s201, determining the data volume of the current transmission according to the target BAR and the target initial address corresponding to the data to be transmitted.

The target starting address dev _ address corresponding to the data to be transmitted is determined before the data to be transmitted is transmitted. During the mapping process of the BAR, as shown in fig. 3a, the BAR has a starting address of 0 on the target memory at the first mapping, and has a starting address of BAR _ size on the target memory at the second mapping; at the third mapping, the BAR starts at 2 BAR size … … on the target memory. Usually, the target start address dev _ address corresponding to the data to be transmitted does not coincide with the start address mapped by the BAR, and therefore, when the data to be transmitted is mapped by the target BAR, the current transmission amount needs to be determined according to the target BAR and the target start address corresponding to the data to be transmitted.

Alternatively, this can be explained in detail by the embodiment shown in fig. 4. As shown in fig. 4, one possible implementation method of S201 "determining the currently transmitted data amount according to the target BAR and the target start address corresponding to the data to be transmitted" includes the following steps:

s301, acquiring the current initial address of the target BAR.

On the basis of the above embodiment, after the target BAR is selected for the data to be transmitted, the size of the target BAR can be determined by reading the information in the sriov _ arr array. Optionally, the current start address of the target BAR may be a start address corresponding to the target BAR when there is an intersection between an address segment mapped by the target BAR on the target memory and the target start address of the data to be transmitted. Optionally, in the embodiment of the present application, when data transmission is performed by using the target BAR, the target BAR may be first set to determine a current start address of the target BAR. Further, the present application may also store the current starting address of the target BAR. The BAR setting operation described above may include: and inquiring whether intersection exists between the address of the target BAR mapped on the target memory storage and the target starting address, and determining the current starting address of the target BAR.

Optionally, the BAR may be mapped from a start address 0 of the target memory during mapping, and when the BAR is mapped for the first time, it is queried whether a mapping address segment corresponding to the target BAR intersects with the target start address, and if so (that is, when the target start address of the data to be transmitted is within the range of the mapping address segment corresponding to the target BAR), the start address 0 of the target memory is used as the current start address of the target BAR. If not (namely when the target starting address of the data to be transmitted is out of the range of the mapping address section corresponding to the target BAR), sliding the target BAR, then returning to inquire whether the mapping address section corresponding to the target BAR and the target starting address have intersection until the mapping address section corresponding to the target BAR and the target starting address have intersection, and determining the starting address of the address section of the current target BAR, which is currently mapped on the target memory, as the current starting address of the target BAR. Specific implementations of the target BAR sliding operation can be found in the description below.

S302, determining the data volume to be transmitted according to the size of the target BAR, the current starting address of the target BAR and the target starting address of the data to be transmitted.

On the basis of the above embodiment, the transferable data volume mapped by the target BAR at this time can be determined by the size of the target BAR and the current start address of the target BAR. For example, the size of the target BAR is represented by BAR _ size, the current start address of the target BAR is represented by BAR _ address, the target start address of data to be transmitted is represented by dev _ address, and the amount of data that can be transmitted can be determined by the formula BAR _ address + BAR _ size-dev _ address.

S303, determining the data volume of the current transmission according to the data volume of the data to be transmitted and the transmittable data volume.

On the basis of the above S302, on the basis of determining the transmittable data amount, the smaller value of the pair of the data amount of the data to be transmitted and the transmittable data amount may be taken as the data amount of the current transmission, that is, the data amount of the current transmission is determined by min (len, bar _ address + bar _ size-dev _ address). The len is used to indicate a remaining data amount of the data to be transmitted, which is not stored in the first address segment yet, that is, when the remaining data amount of the data to be transmitted, which is not stored in the first address segment yet, is greater than the transferable data amount, the currently-transmitted data amount of the target BAR is the transferable data amount, that is, the target BAR maps part of the data to be transmitted to the first address segment for storage. When the remaining data volume of the data to be transmitted, which is not stored in the first address segment, is less than or equal to the transmittable data volume, the data volume currently transmitted by the target BAR is the data volume of the data to be transmitted, that is, the target BAR maps all the remaining data volume of the data to be transmitted, which is not stored in the first address segment, to the first address segment for storage.

And S202, mapping the currently transmitted data volume to the first address field for storage.

And S203, updating the corresponding target starting address of the data to be transmitted, and returning to S201 until the transmission of the data to be transmitted is completed.

On the basis of the above embodiment, there is a possible case that the data volume of the data to be transmitted is larger than the transmittable data volume, and the data cannot be stored by mapping the target BAR onto the first address segment once, and the data needs to be stored by mapping the target BAR onto the first address segment multiple times. After the first time of target BAR mapping storage is completed, a target start address corresponding to data to be transmitted may be updated and stored, and optionally, the updated target start address may be equal to the sum of the target start address before updating and the amount of data currently transmitted. Generally, the updated target start address is the start address of the target memory mapped by the target BAR for the second time, and then the currently transmitted data volume is determined according to the updated target start address corresponding to the target BAR and the data to be transmitted, and the currently transmitted data volume is continuously mapped to the first address segment for storage until the transmission of the data to be transmitted is completed.

According to the data transmission method, the currently transmitted data volume is determined according to the target BAR and the target starting address corresponding to the data to be transmitted, the currently transmitted data volume is mapped to the first address segment to be stored, the corresponding target starting address of the data to be transmitted is updated, the currently transmitted data volume is determined according to the target BAR and the target starting address corresponding to the data to be transmitted, and the data to be transmitted is stored in the first address segment through multiple times of mapping of the target BAR until the transmission of the data to be transmitted is completed, so that when the data to be transmitted is larger than the data volume corresponding to the address of the target BAR mapped on the target memory, the flexibility of the data transmission method is improved.

Since the BAR is mapped to the target memory in sequence, and the target start address is not necessarily the start address of the target memory at the position on the target memory, in a possible case, when the target BAR is mapped to the target memory for the first time, it may occur that the target start address is not within the address section mapped by the target BAR, therefore, when the data to be transmitted is stored in the first address section by the target BAR, it is necessary to check whether the target BAR intersects with the target start address in the address section mapped on the target memory, and when the intersection exists, the data to be transmitted can be stored in the first address section by the target BAR by mapping. As will be described in detail below with reference to fig. 5, as shown in fig. 5, the method further includes:

s401, acquiring a second address field of a target BAR mapped on a target memory; the second address field is the address field on the target memory obtained by the target BAR through one mapping.

The second address field may be an address field on the target memory obtained by mapping the target BAR once, as shown in fig. 3a, the address field represented by BAR _ size is the second address field mapped on the target memory by the target BAR. As can be seen from the above description of the embodiments, the target BAR is mapped, usually starting from the starting address 0 of the target memory. The second address field may be an address field of the target BAR mapped on the target memory for the first time, or an address field of the target BAR mapped on the target memory for the nth time, which is not limited in this embodiment of the application.

S402, if the second address segment intersects with a target initial address corresponding to the data to be transmitted, mapping the data to be transmitted to the first address segment through the target BAR for storage.

And if the second address segment has an intersection with the target initial address corresponding to the data to be transmitted, namely the target initial address of the data to be transmitted is in the address interval of the second address segment, performing data mapping through the target BAR. That is, the second address field may be an address field intersecting with the first address field, the first address field may be completely the same as the second address field, and the first address field may also include the second address field, which is not limited in this embodiment of the present application. At this time, the data to be transmitted can be mapped to the first address segment for storage through the target BAR directly.

And S403, if the second address segment does not intersect with the target starting address corresponding to the data to be transmitted, performing at least one sliding window by controlling the target BAR until the current second address segment of the target BAR intersects with the target starting address corresponding to the data to be transmitted. Optionally, the target BAR is controlled to perform sliding window until the second address segment of the target BAR intersects with the target start address corresponding to the data to be transmitted. For the sliding window processing of the target BAR, reference may be specifically made to the embodiment shown in fig. 4, which is not described herein again.

When the BAR is mapped to the target memory, the BAR is usually mapped sequentially from a start address of the target memory, and if a target start address of the data to be transmitted is far from the start address of the target memory, for example, if a target start address of the data to be transmitted is spaced from the start address of the target memory by n × BAR _ size, where n is a positive integer, the BAR needs to be slid multiple times to enable a current second address segment of the target BAR to intersect with a target start address corresponding to the data to be transmitted, which may definitely affect the transmission efficiency of the data. In the embodiment of the application, the current start address of the target BAR can be determined according to the target start address of the data to be transmitted, so that the sliding times of the target BAR are reduced, and the data transmission efficiency is improved.

In an embodiment of the present application, optionally, if the second address segment does not intersect with the target start address corresponding to the data to be transmitted, a current start address of the target BAR is determined according to the target start address of the data to be transmitted, and the target BAR is controlled to start sliding from the current start address.

And when the second address segment does not intersect with the target initial address corresponding to the data to be transmitted, determining the current initial address of the target BAR through the setting operation of the target BAR according to the target initial address of the data to be transmitted. The current start address of the target BAR may be the start address of the BAR closest to the target start address of the data to be transmitted, and typically, the start address of the closest BAR is smaller than or equal to the target start address of the data to be transmitted. Therefore, the target BAR is controlled to slide from the position close to the target starting address of the data to be transmitted, so that the sliding times of the target BAR can be reduced, and the data transmission efficiency is improved. The starting address of the closest BAR may be the starting address of the BAR that intersects the target starting address of the data to be transmitted. For example, the memory space on the DDR can be divided into K address segments according to the size BAR _ size of the target BAR, where K is a positive integer, and meanwhile, the processor can record the starting addresses of the K address segments respectively. Further, the processor may determine, according to the target start address of the data to be transmitted, an address segment closest to the target start address from the K address segments, where the start address of the closest address segment is less than or equal to the target start address of the data to be transmitted, and use the start address of the closest address segment as the current start address of the target BAR, so that the target BAR slides from a position adjacent to the target start address of the data to be transmitted to implement data mapping.

Further, in the embodiment of the present application, each time the target BAR is slid, the location of the target BAR may be recorded, that is, the second address segment of the target BAR mapped on the target memory, for example, the historical location of the BAR mapped on the target memory may be recorded by the above-mentioned array sriov _ arr [12 ]. The historical location of the target BAR may be a historical location recorded the last time data was transmitted using the target BAR.

For example, if the target BAR is first used, the historical location of the target BAR may be zero. If the target BAR is not used for the first time, determining the historical position of the target BAR by reading an array corresponding to the target BAR, and then executing the setting operation of the target BAR: namely, the current start address of the target BAR is updated according to the current position of the target BAR and the target start address of the data to be transmitted.

Specifically, in the embodiment of the present application, the historical position of the target BAR in the last use can be read from the array, and it is determined whether the address segment corresponding to the historical position intersects with the target start address of the current data to be transmitted, and if the address segment corresponding to the historical position of the target BAR intersects with the target start address of the current data to be transmitted, the start address corresponding to the historical position of the target BAR can be directly used as the current start address of the target BAR, so that the sliding and read-write operations of the target BAR are avoided, and the data transmission efficiency is further improved.

Optionally, after the data to be transmitted is mapped to the first address segment by the target BAR for storage, a data synchronization operation may also be performed to confirm that the currently transmitted data amount is already stored in the first address segment.

When data synchronization operation is specifically performed, the data synchronization operation may be implemented by a memory barrier (barrier). A memory barrier, also called a memory barrier, a barrier instruction, is a type of synchronization barrier instruction, which is a synchronization point in operations of a CPU or a compiler in random access to a memory, so that operations after the point can be started to be executed after all read and write operations before the point are executed. That is, whether the instruction that stores the data to be transmitted in the corresponding first address segment has been executed or not can be determined through the memory barrier, and then whether the data to be transmitted is stored in the corresponding first address segment or not can be determined.

The above embodiments describe a process of how to map data to be transmitted onto a first address segment for storage by a target BAR. How to determine the target base address register BAR for the data to be transmitted is explained in detail below with reference to fig. 6 and 7.

Fig. 6 is a schematic flow chart of a data transmission method in another embodiment, which relates to a specific process of how to determine a target base address register BAR for data to be transmitted, and as shown in fig. 6, a possible implementation method of the above-mentioned S101 "determining a target base address register BAR for data to be transmitted" includes the following steps:

s501, acquiring semaphore of each BAR in a BAR set; the semaphore is used to indicate whether the BAR is in an idle state.

As described above, the BARs exist in the BAR set, the status information of each BAR may be recorded in sriov _ BAR, and information such as the start virtual address of the BAR, the number of waiting BARs, and the semaphore window _ sem may also be recorded in sriov _ BAR. Continuing with the example where the BAR set includes 12 BARs, sriov _ BAR records the status information of the 12 BARs via sriov _ arr [12 ]. The semaphore for each BAR is obtained by obtaining sriov _ arr [12 ]. Wherein the semaphore is used to indicate whether the BAR is in an idle state. For example, when the semaphore is 0, the BAR processing idle state is indicated, and when the semaphore is 1, the BAR processing non-idle state is indicated.

S502, determining the BAR in the idle state as a target BAR according to the semaphore of each BAR.

When the BAR in the idle state is acquired, the BAR in the idle state can be determined as a target BAR, and an index number corresponding to the BAR in sriov _ arr is returned. Alternatively, when there are a plurality of BARs in the idle state, a BAR in the idle state sequentially preceding is determined as the target BAR.

As shown in fig. 2a, the BAR set includes 12 BARs belonging to 4 Virtual Function (VFs), each VF has 3 BARs, each of which is BAR0, BAR2 and BAR4, and each BAR has a size of 16MB), that is, as shown in fig. 2a, the BAR set includes 12 BARs, namely, VF0_ BAR0, VF0_ BAR2, VF0_ BAR4, VF1_ BAR0, VF1_ BAR2, VF1_ BAR4, VF2_ BAR0, VF2_ BAR2, VF2_ BAR4, VF3_ BAR0, VF3_ BAR2 and VF3_ BAR4, which are arranged in sequence. When it is determined that the BARs in the idle state are VF0_ BAR4, VF1_ BAR4, and VF2_ BAR0 according to the semaphore of each BAR, VF0_ BAR4 is determined as a target BAR according to the order of each BAR.

When no BAR in an idle state exists in the BAR set, the target BAR can be determined by acquiring the number of waiting tasks of each BAR. This is explained in detail below with reference to fig. 7. As shown in fig. 7, the method further comprises the steps of:

s601, acquiring the number of waiting tasks of each BAR, and taking the BAR with the minimum number of waiting tasks as a target BAR.

S602, when the semaphore of the target BAR indicates that the target BAR is in an idle state, mapping the data to be transmitted to a first address segment through the target BAR for storage.

Wherein, the state information of each BAR is recorded in sriov _ BAR, which includes the waiting task number wait _ count of each BAR. And acquiring the number of waiting tasks of each BAR by acquiring the sriov _ BAR, and taking the BAR with the minimum number of waiting tasks as a target BAR. And when the semaphore of the target BAR indicates that the target BAR is in an idle state, mapping the data to be transmitted to a first address segment through the target BAR for storage.

It should be noted that, in the embodiment of the present application, the number of waiting tasks of each BAR may also be obtained by another method, and a manner of obtaining the number of waiting tasks of each BAR by wait _ count in the embodiment of the present application is only an example.

According to the data transmission method, when no BAR in an idle state exists in a BAR set, the number of waiting tasks of each BAR is acquired, the BAR with the minimum number of waiting tasks is used as a target BAR, and when the semaphore of the target BAR indicates that the target BAR is in the idle state, the data to be transmitted are mapped to a first address segment through the target BAR to be stored. Therefore, when the BAR set does not have the BAR in the idle state, the BAR with the minimum waiting task number can be used as the target BAR, the waiting time when the data to be transmitted is mapped to the memory space for storage is minimum, and the data transmission efficiency is improved.

It should be understood that although the various steps in the flow charts of fig. 2-7 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 2-7 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.

In one embodiment, as shown in fig. 8, there is provided a data transmission apparatus including: a selecting module 10 and a mapping module 20, wherein:

the selection module 10 is configured to determine a target base address register BAR for the data to be transmitted when the data amount of the data to be transmitted is smaller than a preset transmission threshold;

the mapping module 20 is configured to map the data to be transmitted to a first address segment of the target memory through the target BAR for storage, where the first address segment includes a target start address corresponding to the data to be transmitted.

The data transmission device provided in the embodiment of the present application may implement the method embodiments, and the implementation principle and the technical effect are similar, which are not described herein again.

Fig. 9 is a schematic structural diagram of a data transmission apparatus in another embodiment, and based on the embodiment shown in fig. 8, as shown in fig. 9, the mapping module 20 includes: a first determining unit 201, a mapping unit 202 and an updating unit 203, wherein:

a first determining unit 201, configured to determine a currently transmitted data amount according to a target BAR and a target start address corresponding to data to be transmitted;

a mapping unit 202, configured to map a currently transmitted data size onto a first address segment for storage;

the updating unit 203 is configured to update the target start address corresponding to the data to be transmitted, and determine the amount of currently transmitted data according to the target BAR and the target start address corresponding to the data to be transmitted until the transmission of the data to be transmitted is completed.

In one embodiment, the first determining unit 201 is specifically configured to obtain the size and the current start address of the target BAR; determining the transmittable data volume according to the size of the target BAR, the current starting address of the target BAR and the target starting address of the data to be transmitted; and determining the data volume of the current transmission according to the data volume of the data to be transmitted and the transmittable data volume.

Fig. 10 is a schematic structural diagram of a data transmission apparatus in another embodiment, and based on the embodiment shown in fig. 8 or fig. 9, as shown in fig. 10, the data transmission apparatus further includes a determining module 30, where:

the determining module 30 is specifically configured to obtain a second address field mapped on the target memory by the target BAR; the second address field is an address field on the target memory obtained by the target BAR through one-time mapping; if the second address segment intersects with a target initial address corresponding to the data to be transmitted, mapping the data to be transmitted to the first address segment through the target BAR for storage; and if the second address segment is not intersected with the target initial address corresponding to the data to be transmitted, controlling the target BAR to slide until the second address segment of the target BAR is intersected with the target initial address corresponding to the data to be transmitted.

In an embodiment, the determining module 30 is specifically configured to determine a current start address of the target BAR and control the target BAR to start sliding from the current start address if the second address segment does not intersect with the target start address corresponding to the data to be transmitted.

It should be noted that fig. 10 is shown based on fig. 9, but fig. 10 may also be shown based on fig. 8, which is merely an example.

Fig. 11 is a schematic structural diagram of a data transmission apparatus in another embodiment, and based on the embodiment shown in any one of fig. 8 to 10, as shown in fig. 11, the selecting module 10 includes: an acquisition unit 101 and a second determination unit 102, wherein:

the acquiring unit 101 is configured to acquire a semaphore of each BAR in the BAR set; the semaphore is used to indicate whether the BAR is in an idle state;

the second determining unit 102 is configured to determine, as the target BAR, a BAR in an idle state according to a semaphore of each BAR.

In one embodiment, the second determining unit 102 is specifically configured to determine, as the target BAR, a BAR in an idle state that is sequentially previous when there are a plurality of BARs in the idle state.

In one embodiment, the second determining unit 102 is further configured to obtain the number of waiting tasks of each BAR, and take the BAR with the smallest number of waiting tasks as the target BAR; and when the semaphore of the target BAR indicates that the target BAR is in an idle state, establishing and mapping the data to be transmitted to the first address segment for storage through the target BAR.

Fig. 11 is shown based on fig. 10, but fig. 11 may also be shown based on fig. 8 or 9, and this is merely an example.

Fig. 12 is a schematic structural diagram of a data transmission device in another embodiment, and based on the embodiment shown in any one of fig. 8 to 11, as shown in fig. 12, the data transmission device further includes: a synchronization module 40, wherein:

the synchronization module 40 is configured to perform a data synchronization operation after mapping the data to be transmitted onto the first address segment for storage through the target BAR according to the target start address, so as to confirm that the currently transmitted data amount is already stored in the first address segment.

It should be noted that fig. 12 is shown based on fig. 11, but fig. 12 may also be shown based on any one of fig. 8 to 10, and this is merely an example.

Specific limitations regarding the data transmission means can be found in the above limitations regarding the data transmission method, as well. The modules in the data transmission device can be wholly or partially implemented by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent of a processor in the electronic device, or can be stored in a memory in the electronic device in a software form, so that the processor can call and execute operations corresponding to the modules.

In one embodiment, an electronic device is provided, comprising a memory and a processor, the memory having a computer program stored therein, the processor implementing the following steps when executing the computer program:

In one embodiment, the processor, when executing the computer program, performs the steps of: determining the data volume of current transmission according to the target BAR and the target initial address corresponding to the data to be transmitted; mapping the currently transmitted data volume to a first address field for storage; and updating the corresponding target starting address of the data to be transmitted, and determining the data volume of the current transmission according to the target BAR and the target starting address corresponding to the data to be transmitted until the transmission of the data to be transmitted is completed.

In one embodiment, the processor, when executing the computer program, performs the steps of: acquiring the size and the current initial address of a target BAR; determining the transmittable data volume according to the size of the target BAR, the current starting address of the target BAR and the target starting address of the data to be transmitted; and determining the data volume of the current transmission according to the data volume of the data to be transmitted and the transmittable data volume.

In one embodiment, the processor, when executing the computer program, performs the steps of: acquiring a second address field of the target BAR mapped on the target memory; the second address field is an address field on the target memory obtained by the target BAR through one-time mapping; if the second address segment intersects with a target initial address corresponding to the data to be transmitted, mapping the data to be transmitted to the first address segment through the target BAR for storage; and if the second address segment is not intersected with the target initial address corresponding to the data to be transmitted, controlling the target BAR to slide until the second address segment of the target BAR is intersected with the target initial address corresponding to the data to be transmitted.

In one embodiment, the processor, when executing the computer program, performs the steps of: and if the second address segment does not intersect with the target initial address corresponding to the data to be transmitted, determining the current initial address of the target BAR, and controlling the target BAR to slide from the current initial address.

In one embodiment, the processor, when executing the computer program, performs the steps of: and after the data to be transmitted is mapped to the first address segment for storage through the target BAR according to the target starting address, executing data synchronization operation to confirm that the currently transmitted data volume is stored in the first address segment.

In one embodiment, the processor, when executing the computer program, performs the steps of: acquiring the semaphore of each BAR in the BAR set; the semaphore is used to indicate whether the BAR is in an idle state; and determining the BAR in the idle state as a target BAR according to the semaphore of each BAR.

In one embodiment, the processor, when executing the computer program, performs the steps of: when there are a plurality of BARs in the idle state, a BAR in the idle state sequentially preceding is determined as a target BAR.

In one embodiment, the processor, when executing the computer program, performs the steps of: acquiring the number of waiting tasks of each BAR, and taking the BAR with the minimum number of waiting tasks as a target BAR; and when the semaphore of the target BAR indicates that the target BAR is in an idle state, mapping the data to be transmitted to the first address segment through the target BAR for storage.

In one embodiment, the processor, when executing the computer program, performs the steps of: and after the data to be transmitted is mapped to the first address segment for storage through the target BAR according to the target starting address, whether the data to be transmitted is stored in the corresponding memory space is confirmed through the memory barrier.

Optionally, the processor includes a first processor and a second processor, the first processor is an artificial intelligence processor, and the second processor is a general-purpose processor.

The electronic device may be, but is not limited to, a data transmission device, a robot, a computer, a printer, a scanner, a tablet, a smart terminal, a cell phone, a tachograph, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, a headset, a mobile storage, a wearable device, a vehicle, a household appliance, and/or a medical device. The vehicle comprises an airplane, a ship and/or a vehicle; the household appliances comprise a television, an air conditioner, a microwave oven, a refrigerator, an electric cooker, a humidifier, a washing machine, an electric lamp, a gas stove and a range hood; the medical equipment comprises a nuclear magnetic resonance apparatus, a B-ultrasonic apparatus and/or an electrocardiograph.

In one embodiment, a readable storage medium is provided, having stored thereon a computer program which, when executed by a processor, performs the steps of:

and mapping the data to be transmitted to a first address segment of a target memory through the target BAR to store a target initial address corresponding to the data to be transmitted in the first address segment.

In one embodiment, the computer program when executed by the processor implements the steps of: determining the data volume of current transmission according to the target BAR and the target initial address corresponding to the data to be transmitted; mapping the currently transmitted data volume to a first address field for storage; and updating the corresponding target starting address of the data to be transmitted, and determining the data volume of the current transmission according to the target BAR and the target starting address corresponding to the data to be transmitted until the transmission of the data to be transmitted is completed.

In one embodiment, the computer program when executed by the processor implements the steps of: acquiring the size and the current initial address of a target BAR; determining the transmittable data volume according to the size of the target BAR, the current starting address of the target BAR and the target starting address of the data to be transmitted; and determining the data volume of the current transmission according to the data volume of the data to be transmitted and the transmittable data volume.

In one embodiment, the computer program when executed by the processor implements the steps of: acquiring a second address field of the target BAR mapped on the target memory; the second address field is an address field on the target memory obtained by the target BAR through one-time mapping; if the second address segment intersects with a target initial address corresponding to the data to be transmitted, mapping the data to be transmitted to the first address segment through the target BAR for storage; and if the second address segment is not intersected with the target initial address corresponding to the data to be transmitted, controlling the target BAR to slide until the second address segment of the target BAR is intersected with the target initial address corresponding to the data to be transmitted.

In one embodiment, the computer program when executed by the processor implements the steps of: and if the second address segment does not intersect with the target initial address corresponding to the data to be transmitted, determining the current initial address of the target BAR, and controlling the target BAR to slide from the current initial address.

In one embodiment, the computer program when executed by the processor implements the steps of: and after the data to be transmitted is mapped to the first address segment for storage through the target BAR according to the target starting address, executing data synchronization operation to confirm that the currently transmitted data volume is stored in the first address segment.

In one embodiment, the computer program when executed by the processor implements the steps of: acquiring the semaphore of each BAR in the BAR set; the semaphore is used to indicate whether the BAR is in an idle state; and determining the BAR in the idle state as a target BAR according to the semaphore of each BAR.

In one embodiment, the computer program when executed by the processor implements the steps of: when there are a plurality of BARs in the idle state, a BAR in the idle state sequentially preceding is determined as a target BAR.

In one embodiment, the computer program when executed by the processor implements the steps of: acquiring the number of waiting tasks of each BAR, and taking the BAR with the minimum number of waiting tasks as a target BAR; and when the semaphore of the target BAR indicates that the target BAR is in an idle state, mapping the data to be transmitted to the first address segment through the target BAR for storage.

In one embodiment, the computer program when executed by the processor implements the steps of: and after the data to be transmitted is mapped to the first address segment for storage through the target BAR according to the target starting address, whether the data to be transmitted is stored in the corresponding memory space is confirmed through the memory barrier.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A method of data transmission, the method comprising:

mapping the data to be transmitted to a first address segment of a target memory for storage through the target BAR; the first address segment comprises a target starting address corresponding to the data to be transmitted.

2. The method of claim 1, wherein the mapping the data to be transmitted onto a first address segment for storage by the target BAR comprises:

determining the currently transmitted data volume according to the target BAR and the target initial address corresponding to the data to be transmitted;

mapping the currently transmitted data volume to the first address field for storage;

and updating the corresponding target starting address of the data to be transmitted, and determining the currently transmitted data volume according to the target BAR and the target starting address corresponding to the data to be transmitted until the transmission of the data to be transmitted is completed.

3. The method of claim 2, wherein determining the currently transmitted data amount according to the target BAR and the target start address corresponding to the data to be transmitted comprises:

acquiring a current initial address of the target BAR;

and determining the currently transmitted data volume according to the data volume of the data to be transmitted and the transmittable data volume.

4. The method according to any one of claims 1-3, further comprising:

obtaining a second address field of the target BAR mapping on the target memory; the second address field is an address field on the target memory obtained by the target BAR through one-time mapping;

if the second address segment intersects with a target starting address corresponding to the data to be transmitted, mapping the data to be transmitted to a first address segment for storage through the target BAR;

and if the second address segment is not intersected with the target starting address corresponding to the data to be transmitted, controlling the target BAR to slide until the second address segment of the target BAR is intersected with the target starting address corresponding to the data to be transmitted.

5. The method of claim 4, further comprising:

if the second address segment does not intersect with the target starting address corresponding to the data to be transmitted, determining the current starting address of the target BAR according to the target starting address of the data to be transmitted, and controlling the target BAR to start sliding from the current starting address.

6. The method of claim 4, further comprising:

after the data to be transmitted are mapped to a first address segment for storage through the target BAR according to the target starting address, performing data synchronization operation to confirm that the currently transmitted data volume is stored in the first address segment.

7. The method of claim 4, wherein the determining a target Base Address Register (BAR) for the data to be transmitted comprises:

and determining the BAR in an idle state as the target BAR according to the semaphore of each BAR.

8. The method of claim 7, wherein the determining the BAR in the idle state as the target BAR comprises:

when the number of the BARs in the idle state is multiple, determining the BAR in the idle state with the previous sequence as the target BAR according to a preset sequence.

9. The method of claim 7, wherein if there is no BAR in the set of BARs in an idle state, the method further comprises:

and when the semaphore of the target BAR indicates that the target BAR is in an idle state, mapping the data to be transmitted to a first address segment through the target BAR for storage.

10. An electronic device comprising a memory and a processor, the memory storing a computer program, wherein the processor implements the steps of the method of any one of claims 1 to 9 when executing the computer program.

11. A readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 9.