CN112946551A - Method and device for measuring path delay, electronic device and storage medium - Google Patents
Method and device for measuring path delay, electronic device and storage medium Download PDFInfo
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Abstract
The application relates to a method, a device, an electronic device and a storage medium for measuring path delay, wherein the method for measuring the path delay comprises the following steps: acquiring waveform data of a source end of a digital test channel, wherein the digital test channel is used for testing an electronic element, and the waveform data is acquired under the condition that the tail end of the digital test channel is open; acquiring an inflection point of a slope rise in a waveform according to waveform data, wherein the waveform is determined by the waveform data; and determining the delay of the test path according to the time corresponding to the inflection point. By the method and the device, the problems of long time consumption and low efficiency caused by the fact that the testing path is calibrated through the calibration system of the digital testing machine in the related art are solved, and the efficiency and the precision of calibrating the testing path are improved.
Description
Technical Field
The present application relates to the field of integrated circuit testing technologies, and in particular, to a method and an apparatus for measuring a path delay, an electronic apparatus, and a storage medium.
Background
In the production of semiconductor chips, the chips need to be tested by a digital test system of a digital tester. Therefore, the digital test system needs to guarantee a high time accuracy, which is typically below 200 ps. The digital test system is provided with a time parameter calibration system, so that the time precision output by the digital test system can meet the requirement, but the calibration system can only calibrate the digital test system, cannot calibrate a carrier Board (Load Board) path where a chip to be tested is located, and can only be manually calibrated, so that the calibration cost is long, and the efficiency is low.
At present, no effective solution is provided for the problems of long time consumption and low efficiency caused by the calibration of a test path through a calibration system of a digital test machine in the related art.
Disclosure of Invention
The embodiment of the application provides a method and a device for measuring path delay, an electronic device and a storage medium, which are used for at least solving the problems of long time consumption and low efficiency caused by the fact that a calibration system of a digital testing machine is used for calibrating a test path in the related art.
In a first aspect, an embodiment of the present application provides a method for measuring a path delay, including:
acquiring waveform data of a source end of a digital test channel, wherein the digital test channel is used for testing an electronic element, and the waveform data is acquired under the condition that the tail end of the digital test channel is open;
acquiring an inflection point of a slope rise in a waveform according to the waveform data, wherein the waveform is determined by the waveform data;
and determining the delay of the test path according to the time corresponding to the inflection point.
In some of these embodiments, said obtaining an inflection point of a slope rise in a waveform from said waveform data comprises:
acquiring a plateau period of the waveform according to the waveform data;
and after the time corresponding to the plateau period, acquiring a point of the waveform at which the ordinate starts to increase as the inflection point.
In some of these embodiments, obtaining the plateau of the waveform from the waveform data comprises:
and performing derivation on a preset number of data in the waveform data, and judging whether the waveform corresponding to the data is the plateau period or not according to a derivation result.
In some embodiments, the obtaining, as the inflection point, a point in the waveform at which the ordinate starts to increase after the time corresponding to the plateau includes:
obtaining a derivative of the waveform data after the plateau;
and under the condition that the derivatives are all larger than a preset threshold value in a preset time period and the level in the waveform data is larger than a preset level value, acquiring a corresponding point when the derivative is larger than the preset threshold value at the beginning as the inflection point.
In some embodiments, the obtaining the waveform data of the source end of the digital test channel includes:
obtaining a comparison result of the test system states of the two adjacent digital test channels according to a preset comparison level and a comparison edge, and obtaining a jump edge according to the comparison result, wherein the test system states comprise a passing state and a failing state, and the jump edge is determined according to a passing boundary and a failing boundary in the test system states;
under the condition that a jump edge is not obtained, obtaining a test point position and updating the comparison edge;
and under the condition of acquiring the jump edge, acquiring all waveform data corresponding to the jump edge.
In some embodiments, the obtaining test sites comprises:
determining a comparison edge range according to the two comparison edges;
and obtaining the test point location by a dichotomy according to the comparison edge range.
In some embodiments, the determining the delay of the test path according to the time corresponding to the inflection point includes:
calculating a time difference according to the time corresponding to the inflection point and the time corresponding to the starting point of the waveform;
determining a delay of the test path from half of the time difference.
In a second aspect, an embodiment of the present application provides a path delay measuring apparatus, including a digital test system and a processor:
the processor acquires waveform data of a source end of a digital test channel in the digital test system, wherein the digital test channel is used for correcting an electronic element, and the waveform data is acquired under the condition that the tail end of the digital test channel is open;
the processor obtaining an inflection point of a slope rise in a waveform according to the waveform data, wherein the waveform is determined by the waveform data;
and the processor determines the delay of the test path according to the time corresponding to the inflection point.
In a third aspect, an embodiment of the present application provides an electronic apparatus, which includes a memory, a processor, and a computer program stored on the memory and executable on the processor, and the processor executes the computer program to implement the method for measuring a path delay according to the first aspect.
In a fourth aspect, the present application provides a storage medium, on which a computer program is stored, where the program is executed by a processor to implement the method for measuring path delay according to the first aspect.
Compared with the related art, the method for measuring the path delay provided by the embodiment of the application obtains the waveform data of the source end of the digital test channel, wherein the digital test channel is used for testing the electronic element, and the waveform data is obtained in the state that the tail end of the digital test channel is open; acquiring an inflection point of a slope rise in a waveform according to waveform data, wherein the waveform is determined by the waveform data; the delay of the test path is determined according to the time corresponding to the inflection point, so that the problems of long time consumption and low efficiency caused by the fact that the test path is calibrated by a calibration system of a digital testing machine in the related art are solved, and the efficiency and the precision of calibrating the test path are improved.
The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the application.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a flow chart of a method of measuring path delay according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a digital test channel according to an embodiment of the present application;
FIG. 3 is a schematic diagram of impedance as a function of line width according to an embodiment of the present application;
FIG. 4 is a flow chart of a method of obtaining inflection points in accordance with an embodiment of the present application;
FIG. 5 is a flow chart of a method of acquiring waveform data according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a waveform scan according to an embodiment of the present application;
FIG. 7 is a schematic diagram comparing a source waveform and a tail waveform according to an embodiment of the application;
FIG. 8 is a waveform diagram of delay calculations according to an embodiment of the present application;
fig. 9 is a block diagram of a hardware structure of a method for measuring a path delay according to an embodiment of the present application;
fig. 10 is a block diagram of a path delay measuring apparatus according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided in the present application without any inventive step are within the scope of protection of the present application. Moreover, it should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another.
Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the specification. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of ordinary skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments without conflict.
Unless defined otherwise, technical or scientific terms referred to herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which this application belongs. Reference to "a," "an," "the," and similar words throughout this application are not to be construed as limiting in number, and may refer to the singular or the plural. The present application is directed to the use of the terms "including," "comprising," "having," and any variations thereof, which are intended to cover non-exclusive inclusions; for example, a process, method, system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to the listed steps or elements, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. Reference to "connected," "coupled," and the like in this application is not intended to be limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Reference herein to "a plurality" means greater than or equal to two. "and/or" describes an association relationship of associated objects, meaning that three relationships may exist, for example, "A and/or B" may mean: a exists alone, A and B exist simultaneously, and B exists alone. Reference herein to the terms "first," "second," "third," and the like, are merely to distinguish similar objects and do not denote a particular ordering for the objects.
The method can be applied to a digital test system, the digital test system is provided with a plurality of digital test channels, the digital test channels are connected to different pins of the electronic element to be tested on a test product board, and due to the fact that different channels have different paths on the test product board and pass different components, even if the channel output point meets the time precision requirement, when the channel output point reaches the pins of the electronic element to be tested, the time precision can also deviate.
The present embodiment provides a method for measuring a path delay, and fig. 1 is a flowchart of a method for measuring a path delay according to an embodiment of the present application, and as shown in fig. 1, the method includes the following steps:
step S110, obtaining waveform data of a source end of a digital test channel, where the digital test channel is used to test an electronic component, and the waveform data is obtained in a state where a tail end of the digital test channel is open.
Among them, electronic components are basic elements in electronic circuits, usually packaged individually, and have two or more leads or metal contacts, for example: an amplifier, a radio receiver, an oscillator or a chip, etc.
In this embodiment, when testing the digital test channel, the waveform data of the source end of the digital test channel is recorded, and the waveform data is data including time and level, for example, may be [ T [ ]1，V1]、[T2，V2]、[T3，V3]、……、[Tn，Vn]And representing waveform data of different point locations in the source-end waveform, wherein T represents the edge of one point location in the waveform, and V represents the level of the corresponding point location. The source end is one end of the test path close to the digital test system, the tail end is one end of the test path close to the electronic element, and the impedance of the test path of the digital test channel is determined according to the output impedance of the source end, for example, the impedance of the test path of the digital test channel is consistent with the output impedance of the source end.
Further, in this embodiment, the impedance of the test path of the digital test channel corresponds to the output impedance of the source end. For example, if the source output impedance of the digital test channel is 50 ohms, then the impedance of the test path is also designed to follow the 50 ohm characteristic impedance.
Step S120, obtaining an inflection point of a slope rise in a waveform according to the waveform data, wherein the waveform is determined by the waveform data.
The waveform data in this embodiment is level data acquired at different times in the test process, and for these data, the waveform data is plotted in a coordinate system with time as a horizontal axis and level as a vertical axis to form a waveform. The inflection point in this embodiment represents a discontinuity of a slope when a vertical coordinate value of a point location in a waveform changes from low to high.
The specific way of acquiring the inflection point may be to draw the waveform according to the waveform data so as to directly read the inflection point in the waveform, or may be to perform mathematical calculation only on the waveform data without drawing the waveform, and acquire the inflection point according to the result of the mathematical calculation.
Step S130, determining the delay of the test path according to the time corresponding to the inflection point.
In general, the delay of the test path may be obtained using a method of generating a trigger point by a level. Specifically, a trigger test is performed through the level of a rising edge, and after a waveform trigger point is acquired, the delay of a test path is determined according to the delay between different trigger points. Where these trigger points appear as inflection points in the waveform.
In this embodiment, the delay of the test path may be calculated according to the time corresponding to the inflection point, and the specific principle is as follows.
Fig. 2 is a schematic diagram of a digital test channel according to an embodiment of the present application, and as shown in fig. 2, since the source-side output impedance of the digital test channel is 50 ohms, the impedance of the test path is designed to follow the characteristic impedance of 50 ohms.
During testing, the drive of the digital testing channel generates a step signal, and because the path impedance is basically stable, reflection cannot occur, and if the electronic element to be tested is open-circuited, total reflection can occur in the digital testing channel. The reflected waveform and the incident waveform are superposed, the step waveform can be changed specifically, and the delay of the test path can be obtained by comparing the waveform of the source end with the waveform of the tail end. According to the reflection formula, the following formula 1:
In the formula 1, the first and second groups of the compound,ρin order to be the reflection coefficient of the light,Z DUT is the impedance of the electronic component to be tested,V in in order to be at the level of the incident signal,V r is the reflected signal level.
Setting the signal level measured at the interface of the electronic element to be measured asV means Then, the following equation 2 is given:
In equation 2, the output impedance of the source terminal, the impedance of the test path, and the amplitude of the step signal output by the digital test channel are all determined, so that the incident signal level can be obtainedV in As long as the signal level at the interface of the electronic element to be measured is measuredV means Can be calculated according to the above formula 2Z DUT 。
Fig. 3 is a schematic diagram of impedance varying with line width according to an embodiment of the present application, as shown in fig. 3, a horizontal axis is Time, a vertical axis is impedance Z, and line widths at different positions in a test path are different, so that impedances at different positions are also different. Due to reflection at different positions caused by impedance variationsV means The time axis of the transmission noise is different, so that the space position of the impedance discontinuity point can be calculated according to the position of the time axis of the transmission noise, and the length of the test path corresponding to the discontinuity point is further obtained.
Through the steps S110 to S130, the present embodiment is based on impedance design of the test path, so that delay of the test path can be obtained according to waveform data of the source end, the whole measurement process can be implemented by a program, and in the related art, the test path calibration is performed by a calibration system of a digital test machine, and manual debugging is required, which results in long time consumption and low efficiency in the test process, and further, because the precision of manual debugging is unstable, the stability of product testing is also affected by manual debugging, therefore, the method in the present embodiment solves the problems of low efficiency and low stability caused by manual debugging, and improves the efficiency and precision of calibrating the test path.
Furthermore, the method in this embodiment can automatically analyze the waveforms for different waveforms, improve the stability of the delay measurement, realize the parallel processing of hardware, and improve the efficiency of the delay measurement, and since no external instrument is needed, the cost of the delay measurement is reduced.
In some embodiments, fig. 4 is a flowchart of a method for obtaining an inflection point according to an embodiment of the present application, and as shown in fig. 4, the method includes the following steps:
step S410, acquiring a plateau period of the waveform according to the waveform data.
The method comprises the following steps that a platform period is that longitudinal coordinate values of point positions in a waveform are kept unchanged within preset time or fluctuate within a preset range, and the preset time and the preset range can be set in a user-defined mode according to requirements. Therefore, after the waveform data is obtained, the waveform data can be analyzed to obtain a plateau in the waveform.
In step S420, after the time corresponding to the plateau period, a point in the waveform at which the ordinate starts to increase is acquired as an inflection point.
Specifically, the increase of the ordinate value in this embodiment means that the value of the ordinate significantly and steadily increases within a preset time period, that is, the ordinate is in a steady rise period.
Through the above steps S410 and S420, the inflection point in the waveform in this embodiment is represented as a catastrophe point of the waveform from the plateau period to the steady rise period, and the inflection point is obtained and determined through the change of the ordinate in the waveform data, so that the calculation accuracy of the inflection point can be improved.
In some of these embodiments, acquiring the plateau of the waveform from the waveform data comprises: and carrying out derivation on a preset amount of data in the waveform data, and judging whether the waveform corresponding to the data is a plateau period or not according to a derivation result. Since the derivative can represent the change condition of the data, in this embodiment, the plateau in the waveform is determined by deriving the waveform data, and the derivation calculation is as shown in formula 3:
In the formula 3, [ Tn-2，Vn-2]、[Tn-1，Vn-1]、[Tn，Vn]、[Tn+1，Vn+1]、[Tn+2，Vn+2]、[Tn+3，Vn+3]The method includes the steps that continuous different point locations in waveform data are respectively represented, in this embodiment, 6 continuous point location data are selected for derivation calculation, and in other embodiments, the preset number can also be selected according to scene requirements or requirements of calculation accuracy. Further, the derivation calculation in equation 3 does not depend on data of a single point, so that the influence of noise can be reduced to some extent.
After derivation, it may be determined whether a waveform corresponding to a point location used for derivation calculation is a plateau period according to a derivation result, specifically, by calculating derivatives at multiple point locations in the waveform, if the derivatives at the multiple point locations are all smaller than a preset change threshold within a preset time period, it is determined that the waveform determined by the multiple point locations is the plateau period, otherwise, the point locations are reselected for derivative calculation until the plateau period is obtained, for example, when 3 consecutive derivatives are obtained as 0, since a calculation result of the derivative is 0 indicates that a longitudinal coordinate of the point location involved in calculation is substantially unchanged, it may be determined that the waveform corresponding to the point location involved in derivation calculation is the plateau period. When the calculation result of the derivative is not 0 or does not continue to be 0 for a period of time, a preset number of point locations may be reselected for derivative calculation until a plateau period of the waveform is obtained according to the waveform data.
In this embodiment, the accuracy of determining the plateau phase can be improved by obtaining the plateau phase of the waveform through derivation calculation.
In some embodiments, the inflection point in the waveform may also be obtained through derivation calculation, specifically, after the plateau period in the waveform is obtained, waveform data after the plateau period is obtained again, the derivation calculation is performed on the waveform data, and then the inflection point is obtained according to the derivative. Since the derivative can characterize the data change, the derivative of the waveform data can be compared with a preset threshold value to judge the waveform change. Since the derivative is greater than 0, which indicates that the ordinate value is increasing, the preset threshold in this embodiment is preferably 0, and when the derivatives are all greater than 0 in the preset time period, a point corresponding to which the derivative starts to be greater than 0 is obtained as an inflection point. Because the influence of the total reflection of the test path on the source end before the formal waveform enables the waveform of the source end to generate a plateau period only once, the inflection point after the plateau period can be used for calculating the delay of the test path. The preset time period in this embodiment can be set and adjusted according to the requirements of engineers, and it should be avoided that the preset time period is too short, which causes the calculation result to be affected by noise, and the error is large.
In the embodiment, the characteristics of the derivative are fully utilized, and the change condition of the waveform is judged according to the change of the derivative, so that the point position of the derivative, which changes from the plateau stage to the point position larger than the preset threshold value, is used as the inflection point, and the calculation accuracy of the inflection point is improved. The method in the embodiment can perform calculation inside a Field Programmable Gate Array (Field Programmable Gate Array, abbreviated as FPGA), acquire acquired data, process the data, realize simultaneous calibration of all channels, and greatly improve calibration efficiency.
In some embodiments, fig. 5 is a flowchart of a method for acquiring waveform data according to an embodiment of the present application, and as shown in fig. 5, the method includes the following steps:
step S510, obtaining a comparison result of the test system states of the two adjacent digital test channels according to a preset comparison level and a comparison edge, and obtaining a jump edge according to the comparison result, wherein the test system states include pass and fail, and the jump edge is determined according to a pass and fail boundary in the test system states.
When the waveform of the test channel is scanned, a comparison level range and a comparison edge range required by scanning need to be preset, for example, the preset comparison level range may be set to 0-3V, the preset comparison edge range may be set to 0-20 ns, and then the comparison level and the comparison edge during testing may be determined according to the preset comparison level range and the comparison edge range, optionally, the comparison level during initial testing may be 0V, and the comparison edge may be 0ns, in addition, in order to accelerate the scanning speed, the comparison level may also be set to 0.5V, and the comparison edge may be 5ns, that is, not from a zero point, and after the comparison level and the comparison edge during initial testing, the comparison level and the comparison edge for next scanning may be obtained according to the preset.
After the compare level and compare edge are set, the test channel can be controlled to output a step waveform and then begin testing. Further, in this embodiment, the test system status including pass and fail may be directly obtained through the digital test system, where pass means that the electronic component to be tested meets the requirement under the current comparison level and the comparison edge, and correspondingly, fail means that the electronic component to be tested does not meet the requirement under the current comparison level and the comparison edge.
After obtaining the two test system states, the two test system states are compared through a comparator, wherein the comparator is used for comparing two or more data items to determine whether the two or more data items are equal or determine the size relationship between the two or more data items.
In this embodiment, the process of obtaining the transition edge is to obtain a system test state of a next comparison edge after determining an initial test system state, and then compare the two system test states until the system test states corresponding to two comparison edges whose values are adjacent are respectively pass and fail, so that the transition edge can be determined, where the transition edge in this application corresponds to one transition level. The method for determining two comparison edges with adjacent values includes the steps of presetting an edge comparison threshold, and considering the two comparison edges as the two comparison edges with adjacent values under the condition that the difference value of the two comparison edges is smaller than or equal to the edge comparison threshold. For example, if the edge comparison threshold is 1ns, 4ns and 5ns are two comparison edges whose numerical values are adjacent to each other, when the system test states corresponding to 4ns and 5ns pass and fail, respectively, it may be determined that the transition edge is 4ns or 5ns, and if the system test states corresponding to 4ns and 6ns pass and fail, respectively, the system test state corresponding to 5ns needs to be obtained again, and then determination is performed.
And step S520, under the condition that the jump edge is not obtained, obtaining the test point position and updating the comparison edge.
Fig. 6 is a schematic diagram of waveform scanning according to an embodiment of the present application, as shown in fig. 6, a horizontal axis represents Time (Time), that is, a comparison edge, a vertical axis represents a level, a region at a lower right side of a curve in the diagram represents that a test system state corresponding to each point location is a pass state, and a region at an upper left side represents that the test system state corresponding to the point location is a fail state, and is a fail state.
Under the condition that the jump edge is not obtained, the point position to be tested needs to be obtained again, correspondingly, the preset comparison edge is updated, then the test is carried out again under the same comparison level, wherein the updating of the preset comparison edge specifically includes that the comparison edge is selected again in the preset comparison edge range. For example, the initial comparison edge 0ns is updated to 5ns, and the test is performed again.
In step S530, under the condition that the jump edge is obtained, all waveform data corresponding to the jump edge are obtained.
Specifically, under the comparison edge which is the same as the jump edge, all waveform data corresponding to the jump edge are obtained according to the position relationship between other comparison levels and the jump level. Assuming that the transition edge is 2ns, waveform data of all levels with edge positions of 2ns may be directly obtained when the transition edge is obtained, for example, when the transition edge is obtained in a point a in fig. 6, it may be determined that the states of the test system are both fail due to the transition edge being 2ns at an upper side of the point a, and pass due to the transition edge being 2ns at a lower side of the point a.
Further, after obtaining the scanning results of other points under the transition edge, if the level scanning is not finished, it is necessary to add a step to the level, for example, in a case that the step is 50mV, the initial comparison level 0 may be updated to 50mV, and the initial comparison edge 0 is updated to the transition edge 2ns, and the feedback result of the test system continues to be obtained by the comparator until the level scanning is finished, and the scanning data is recorded and stored.
Through the above steps S510 to S530, based on the variation of the comparison level range and the comparison edge range, the test time can be greatly reduced according to whether the transition edge obtaining test result is obtained, which is specifically described as follows.
The digital test channel has the functions of driving and comparing, after the test channel outputs a step waveform, the source end is tested by comparing levels, in the related technology, each step of the comparison levels and the step of the comparison edges need to be scanned, and if the levels start to be 0V, 2V at the maximum, the step is 50mV, the edge starts to be 0ns, 20ns at the maximum and the step is 20ps, 2V/50mV 20ns/20ps =40000 times needs to be scanned, and if each scanning consumes 1ms, one channel needs to be tested for 40s, so that the efficiency is low. In the embodiment, the waveform scanning method is optimized, and because the waveform of the signal is continuous, the point location to be tested next time can be optimally selected according to the last jumping edge without testing all the point locations, so that the scanning time is saved, and the scanning efficiency is improved.
In some embodiments, the method for obtaining test point locations includes: and determining a comparison edge range according to the two comparison edges, and acquiring the test point location by a dichotomy according to the comparison edge range. For example, 10ns and 22ns are both two tested comparison edges, and when 10-22 ns is taken as the comparison edge range, 16ns can be used as a new test potential to be tested through the dichotomy. Further, under the condition that 16ns is not a jump edge, determining a next comparison edge range according to the states of the test systems corresponding to 10ns, 16ns and 22ns, for example, if the state corresponding to 10ns is fail and the state corresponding to 16ns is pass, the jump edge is located in the range of 10-16 ns, and selecting 13ns for testing according to the bisection method again. By the method in the embodiment, the test potential is calculated according to the dichotomy, the number of scanning at the edge of each level can be reduced from 1000 to about 10, the number of scanning can be optimized to about 400, and a relatively complete waveform of each channel can be obtained while time is saved and efficiency is improved.
In some of these embodiments, determining the delay of the test path according to the time corresponding to the inflection point includes: and calculating a time difference according to the time corresponding to the inflection point and the time corresponding to the starting point of the waveform, and determining the delay of the test path according to half of the time difference. In this embodiment, the change of the source end waveform is generated due to total reflection of the test channel, so that the inflection point of the source end waveform corresponds to twice the path delay. After the time corresponding to the inflection point is obtained, a difference value calculation is performed on the time corresponding to the waveform starting point to obtain a time difference, half of the time difference is the path delay, and optionally, under the condition that the time corresponding to the waveform starting point is 0, the time corresponding to the inflection point can be directly divided by 2 to obtain the delay of the final test path, so that the method is convenient and fast. In the related art, a level trigger method is used to obtain the delay of a test path, and the test accuracy depends on the accuracy of a trigger point, so that the delay is affected by waveform quality problems such as jitter and attenuation of a comparison waveform, the accuracy of a driving waveform and the like, and is also affected by factors such as the accuracy of a trigger level, and the result is poor. In the embodiment, the delay is calculated through the time difference between the inflection point and the starting point of the same waveform, so that the influence of other factors can be avoided, and the calculation accuracy is improved.
The following are the results of simulations performed according to the embodiments of the present application.
Fig. 7 is a schematic diagram comparing a source end waveform and an end waveform according to an embodiment of the present application, where as shown in fig. 7, an input step excitation high level is 3.3V, a rising edge is 1ns, and a solid line in the diagram is the source end waveform and a dotted line is the end waveform. The starting point P of the end waveform is near 1.8ns, after the end waveform is reflected to the source end, the change of the source end waveform is about near a point Q, and the corresponding time is 3.6ns, so that the delay of the test path can be calculated at the point influenced by the reflection in the source end test.
Further, fig. 8 is a waveform diagram of delay calculation according to an embodiment of the present application, as shown in fig. 8, in which a solid line is a source-side waveform and a dotted line is a tail-side waveform. In the actual testing process, the rising edge of the source end waveform is slow, so that the rising edge of the source end can generate a plateau period due to the reflection waveform, and the source end waveform can only generate the plateau period once due to the influence of the total reflection of the testing path on the source end before the formal waveform. As can be seen from fig. 8, the delay of the solid line waveform and the dotted line waveform can be obtained from the time difference between the start point M of the solid line waveform and the start point K of the dotted line waveform, which is about 3.341ns, and the delay between the point M and the inflection point N where the solid line waveform is gentle is about 6.773 ns. Therefore, it can be seen that the delay time between point M and point N is about twice the delay of the source waveform and the tail waveform, and further, it can be found that the delay from the source to the tail is about 6.773ns/2 ≈ 3.386ns, which is similar to the actual path delay.
It should be noted that the steps illustrated in the above-described flow diagrams or in the flow diagrams of the figures may be performed in a computer system, such as a set of computer-executable instructions, and that, although a logical order is illustrated in the flow diagrams, in some cases, the steps illustrated or described may be performed in an order different than here.
The method embodiments provided in the present application may be executed in a terminal, a computer or a similar computing device. Taking the operation on the terminal as an example, fig. 9 is a hardware structure block diagram of the path delay measurement method according to the embodiment of the present application. As shown in fig. 9, the terminal 90 may include one or more (only one shown in fig. 9) processors 902 (the processors 902 may include, but are not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 904 for storing data, and optionally, a transmission device 906 for communication functions and an input-output device 908. It will be understood by those skilled in the art that the structure shown in fig. 9 is only an illustration and is not intended to limit the structure of the terminal. For example, the terminal 90 may also include more or fewer components than shown in FIG. 9, or have a different configuration than shown in FIG. 9.
The memory 904 may be used for storing computer programs, for example, software programs and modules of application software, such as a computer program corresponding to the method for measuring a path delay in the embodiment of the present application, and the processor 902 executes various functional applications and data processing by running the computer programs stored in the memory 904, so as to implement the method described above. The memory 904 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 904 may further include memory located remotely from the processor 902, which may be connected to the terminal 90 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmitting device 906 is used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the terminal 90. In one example, the transmission device 906 includes a Network adapter (NIC) that can be connected to other Network devices via a base station to communicate with the internet. In one example, the transmitting device 906 can be a Radio Frequency (RF) module configured to communicate with the internet via wireless.
The present embodiment further provides a device for measuring a path delay, where the device is used to implement the foregoing embodiments and preferred embodiments, and the description of the device that has been already made is omitted. As used hereinafter, the terms "module," "unit," "subunit," and the like may implement a combination of software and/or hardware for a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.
Fig. 10 is a block diagram of a device for measuring a path delay according to an embodiment of the present application, and as shown in fig. 10, the device includes a digital test system 1002 and a processor 1004: the processor 1004 obtains waveform data of a source end of a digital test channel in the digital test system 1002, wherein the digital test channel is used for correcting an electronic element, the waveform data is obtained in a state that a tail end of the digital test channel is open, and impedance of a test path of the digital test channel is determined according to output impedance of the source end; the processor 1004 obtains an inflection point of a slope rise in a waveform from the waveform data, wherein the waveform is determined by the waveform data; the processor 1004 determines the delay of the test path according to the time corresponding to the inflection point.
In this embodiment, the impedance design is performed on the test path in the digital test system 1002, so that the delay of the test path can be obtained according to the waveform data of the source end through the processor 1004, the whole measurement process can be implemented by a program, and the test path calibration is performed through the calibration system of the digital test machine in the related art, which requires manual debugging, so that the test process takes long time and is inefficient, and further, the manual debugging also affects the stability of product testing because the precision of the manual debugging is unstable, therefore, the method in this embodiment solves the problems of inefficiency and low stability caused by the manual debugging, and improves the efficiency and precision of calibrating the test path. The problem that the time calibration of the digital test system 1004 cannot guarantee the time precision of the waveform obtained by the electronic element of the product carrier Board (Load Board) can be solved.
Furthermore, the device in the embodiment can automatically analyze the waveforms for different waveforms, improves the stability of delay measurement, can realize hardware parallel processing, improves the efficiency of delay measurement, and reduces the cost of delay measurement due to no need of an external instrument.
The above modules may be functional modules or program modules, and may be implemented by software or hardware. For a module implemented by hardware, the modules may be located in the same processor; or the modules can be respectively positioned in different processors in any combination.
The present embodiment also provides an electronic device comprising a memory having a computer program stored therein and a processor configured to execute the computer program to perform the steps of any of the above method embodiments.
Optionally, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.
Optionally, in this embodiment, the processor may be configured to execute the following steps by a computer program:
and S1, acquiring waveform data of the source end of the digital test channel, wherein the digital test channel is used for testing the electronic element, and the waveform data is obtained in the state that the tail end of the digital test channel is open.
S2, an inflection point of a slope rise in a waveform determined from the waveform data is acquired from the waveform data.
And S3, determining the delay of the test path according to the time corresponding to the inflection point.
It should be noted that, for specific examples in this embodiment, reference may be made to examples described in the foregoing embodiments and optional implementations, and details of this embodiment are not described herein again.
In addition, in combination with the method for measuring the path delay in the foregoing embodiments, the embodiments of the present application may be implemented by providing a storage medium. The storage medium having stored thereon a computer program; the computer program, when executed by a processor, implements any of the method of path delay measurement in the above embodiments.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for measuring path delay, comprising:
acquiring waveform data of a source end of a digital test channel, wherein the digital test channel is used for testing an electronic element, and the waveform data is acquired under the condition that the tail end of the digital test channel is open;
acquiring an inflection point of a slope rise in a waveform according to the waveform data, wherein the waveform is determined by the waveform data;
and determining the delay of the test path according to the time corresponding to the inflection point.
2. The method of measuring a path delay according to claim 1, wherein the obtaining an inflection point of a slope rise in a waveform from the waveform data includes:
acquiring a plateau period of the waveform according to the waveform data;
and after the time corresponding to the plateau period, acquiring a point of the waveform at which the ordinate starts to increase as the inflection point.
3. The method of claim 2, wherein the obtaining the plateau of the waveform from the waveform data comprises:
and performing derivation on a preset number of data in the waveform data, and judging whether the waveform corresponding to the data is the plateau period or not according to a derivation result.
4. The method according to claim 2, wherein the acquiring, as the inflection point, a point in the waveform at which the ordinate starts to increase after the time corresponding to the plateau includes:
obtaining a derivative of the waveform data after the plateau;
and under the condition that the derivatives are all larger than a preset threshold value in a preset time period and the level in the waveform data is larger than a preset level value, acquiring a corresponding point when the derivative is larger than the preset threshold value at the beginning as the inflection point.
5. The method of claim 1, wherein the obtaining waveform data of a source end of the digital test channel comprises:
obtaining a comparison result of the test system states of the two adjacent digital test channels according to a preset comparison level and a comparison edge, and obtaining a jump edge according to the comparison result, wherein the test system states comprise a passing state and a failing state, and the jump edge is determined according to a passing boundary and a failing boundary in the test system states;
under the condition that a jump edge is not obtained, obtaining a test point position and updating the comparison edge;
and under the condition of acquiring the jump edge, acquiring all waveform data corresponding to the jump edge.
6. The method according to claim 5, wherein the obtaining the test point location comprises:
determining a comparison edge range according to the two comparison edges;
and obtaining the test point location by a dichotomy according to the comparison edge range.
7. The method of any one of claims 1 to 6, wherein the determining the delay of the test path according to the time corresponding to the inflection point comprises:
calculating a time difference according to the time corresponding to the inflection point and the time corresponding to the starting point of the waveform;
determining a delay of the test path from half of the time difference.
8. A path delay measuring apparatus, comprising a digital test system and a processor:
the processor acquires waveform data of a source end of a digital test channel in the digital test system, wherein the digital test channel is used for correcting an electronic element, and the waveform data is acquired under the condition that the tail end of the digital test channel is open;
the processor obtaining an inflection point of a slope rise in a waveform according to the waveform data, wherein the waveform is determined by the waveform data;
and the processor determines the delay of the test path according to the time corresponding to the inflection point.
9. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and the processor is configured to execute the computer program to perform the method of measuring a path delay according to any one of claims 1 to 7.
10. A storage medium having stored thereon a computer program, wherein the computer program is arranged to perform the method of measuring path delay according to any of claims 1 to 7 when executed.
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