CN112945152A - Wafer flatness detection device based on bilateral grazing incidence common path self-interference technology - Google Patents
Wafer flatness detection device based on bilateral grazing incidence common path self-interference technology Download PDFInfo
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Abstract
The invention discloses a wafer flatness detection device based on a bilateral grazing incidence common path self-interference technology. The invention comprises two parts of a detection device and a detection method. In the structure of the device, the invention adopts a bilateral grazing incidence detection light path, solves the problem that the reflectivity of the unpolished surface of the wafer is too low when the unpolished surface is in normal incidence, can complete detection without turning over the wafer, and realizes the accurate correspondence of the detection results of the two surfaces; the invention introduces a beam shaping system, and eliminates the interference pattern mapping error caused by grazing incidence; the invention combines the four-wave front transverse shearing interference technology with the characteristics of common optical path and self-interference, simplifies the system structure and improves the capability of resisting environmental interference. In the detection method, the invention provides a method for calculating the wafer surface type by measuring the phase by an interferometry and then calculating the wafer flatness parameter by the wafer surface type, wherein the wafer flatness parameter which can be calculated comprises the following steps: warp, amount of deformation with respect to the fitting surface, and maximum thickness deviation.
Description
Technical Field
The invention belongs to the field of semiconductor manufacturing, and particularly relates to a wafer flatness detection device based on a bilateral grazing incidence common path self-interference technology.
Background
In the modern semiconductor industry, wafer processing is an extremely important front-end process, and the increasing level of the process also puts higher demands on the detection technology.
During the process of grinding and polishing the wafer, the stress causes unexpected changes in the properties of the wafer, such as the morphology, the thickness and the like, and even leads to rejection of the wafer, so that the wafer needs to be detected in time. Various parameters for characterizing the wafer morphology, thickness and other attributes are collectively referred to as the flatness of the wafer, and specifically include: warp (BOW), deformation (Warp), deformation with respect to a fitting Surface (SORI), maximum thickness variation (TTV), and the like.
The flatness of the wafer can be calculated from any two of three sets of data, i.e., the surface profile and the thickness variation of the two surfaces of the wafer, and the most suitable method for accurately measuring the data is an optical interference method.
Therefore, for detecting the wafer flatness, there are two main routes in the prior art:
first, a flatness parameter is calculated by detecting a profile and a thickness profile of one surface (usually a polished surface) of a wafer. One specific embodiment of this route (see prior art 1: A.W.Kulawiec. interferometer for measuring the thickness variations of semiconductor wafers: US,97/45698[ P/OL ].1997-12-04) utilizes the property of the wafer material that it is opaque in the visible band and partially transparent in the near infrared band to construct a Taeman-Green (Twyman-Green) interference system using a laser with a central wavelength of 633nm as the light source, and detects the surface type distribution of the polished surface of the wafer; and meanwhile, constructing a Fizeau interference system taking a laser with the central wavelength of 1550nm as a light source, and detecting the thickness distribution between two surfaces of the wafer to be detected.
Secondly, the flatness parameters are calculated by detecting the surface profile distribution of the two surfaces of the wafer. One specific embodiment of the method of the route (see prior art 2: J.M.Cobb, T.J.Dunn, J.W.Frankovich.Grazing-incidence interferometer with dual-side measurement capability: US, 2015/00493337A 1[ P/OL ].2015-02-19) utilizes a grazing incidence interference technique to enable the unpolished surface of the wafer to have high reflectivity so as to realize interference detection on two surface type distributions.
The problem of the prior art 1 is that the fizeau system therein is difficult to implement conventional phase-shifting interference, so that the demodulation of an interferogram is difficult, and the thickness measurement is affected by the wafer material, so that the error is large; compared with the prior art, the prior art 2 is more feasible, is the mainstream technology in the field of wafer flatness detection, and is applied to the FlatMaster series equipment of Corning Tropel corporation.
However, the "diffractive beam splitting-combining system", "phase shifting system", "relay optical system" and "folded optical system" introduced in the prior art 2 for eliminating the Mapping Error (Mapping Error) introduced by the grazing incidence make the flatness detector of the FlatMaster series based on the prior art very complicated in structure and large in volume, and the actual precision of the flatness detector can only reach about 1 μm due to a large number of system Error sources; meanwhile, although the prior art 2 skillfully utilizes a double-grating light path structure to realize common-path interference, the phase shift technology is still required to be introduced to demodulate the arrangement mode of an interferogram/phase shift mechanism, which is a challenge to ensure that both surfaces of a wafer can be completely measured without being shielded.
In summary, the field of wafer flatness detection is not yet fully developed. Even though the current mainstream wafer flatness detection equipment, the FlatMaster series, still has some problems in technical means, and limits further improvement of detection precision. Therefore, in order to improve the detection accuracy of the wafer flatness parameter to adapt to a new process level and to realize the localization of the detection equipment in the field, a new technical solution is needed.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a wafer flatness detection system based on a double-side grazing incidence common path self-interference technology.
The technical solution of the invention is as follows:
a wafer flatness detection device based on a bilateral grazing incidence common path self-interference technology has a light path structure as follows:
emergent light of the laser (S1) is split into two paths by the first beam splitter (S3) after being expanded by the collimation beam expander (S2), wherein one path is reflected by the second reflector (S5) after being turned by 90 degrees by the first reflector (S4) and then is incident to the lower surface (S7a) of the wafer to be measured (S7) at a grazing incidence angle theta, and the other path is directly reflected by the third reflector (S6) and is incident to the upper surface (S7b) of the wafer to be measured (S7) at the same incidence angle theta; the light reflected by the lower surface (S7a) is reflected by the fourth reflecting mirror (S8) and then enters the second beam splitter (S11), the light reflected by the upper surface (S7b) sequentially passes through the fifth reflecting mirror (S9) and the sixth reflecting mirror (S10) and then also enters the second beam splitter (S11), the two paths of light are converged at the second beam splitter (S11), then the light is shaped by the beam shaping system (S12) and then is condensed by the beam condenser (S13), and finally the interference pattern is generated and collected by the co-path self-drying system (S14).
Further, the grazing incidence angle theta is larger than or equal to 80 degrees.
Further, the light spot centers projected to the lower surface (S7a) and the upper surface (S7b) of the wafer to be tested (S7) through the second reflector (S5) and the third reflector (S6) and the center O of the corresponding surfacea、ObAnd overlapping, wherein the size of the light spot can cover the whole area to be measured.
Furthermore, the system optical axis (Z axis) direction is the light emitting direction of the collimating beam expander (S2), the acute angle between the first beam splitter (S3), the second beam splitter (S11), the first reflector (S4) and the system optical axis (S10) is 45 degrees, the acute angle between the second reflector (S5), the third reflector (S6), the fourth reflector (S8), the fifth reflector (S9) and the system optical axis is theta/2, and the placing direction of the wafer to be tested (S7) is parallel to the system optical axis.
Further, the beam shaping system (S12) comprises two parabolic cylindrical mirrors (S12a), (S12b) for reflecting P in the light path3Shaping the light beam into P in the light path4The cross-section of the location is a circular beam.
Further, the co-channel self-interference system (S14) is a four-wavefront lateral shear interference system, and includes a diffraction grating (S14a) for generating four wavefronts and a camera (S14b) for acquiring an interference pattern.
Further, the implementation method of the device comprises the following steps:
step (ii) of1. The wafer flatness detection device based on the bilateral grazing incidence common path self-interference technology is built, the device is calibrated by using a standard part, and the surface type distribution of two surfaces of the standard part is measured and recorded as
Taking it as a systematic error;
Step 3, calculating specific numerical values of all parameters according to the definitions of all parameters representing the flatness of the wafer by using the surface type distribution calculated in the step 2;
the parameters comprise warping degree, deformation amount relative to a fitting surface and maximum thickness deviation.
Further, the standard component used for calibration in step 1 is a quartz plate meeting the NIST standard or other standard components selected according to the test requirements.
Further, the step 2 is carried out by sequentially adding P1Or P2A light barrier is arranged at the position to shield the detection light path of one surface of the wafer to be detected (S7) so as to detect the other surface;
said P1A position is set between the first spectroscope (S3) and the third reflector (S6);
said P2A position disposed between the first spectroscope (S3) and the first mirror (S4);
further, the face shape calculation process in step 2 includes:
firstly, the phase distribution W is adjusted from the interference diagrama(x,y)、Wb(x,y)；
Then multiplying the phase distribution by the interference factor to obtain a surface profile F containing the system errora0(x,y)、Fb0(x,y)；
Finally distributing the surface type Fa0(x,y)、Fb0(x,y) subtracting the standard part surface profile obtained in step 1 as the systematic error
The actual measurement surface profile distribution F of the surface to be measured can be obtaineda(x,y)、Fb(x,y)。
The invention has the following beneficial effects:
firstly, a method for detecting the surface types of two surfaces of a wafer to be detected to calculate the flatness parameters is adopted, compared with the method for detecting the thickness between the polished surface type and the two surfaces adopted in the prior art 1, only a single light source is needed, and meanwhile, the system error caused by the non-uniformity of the material of the wafer to be detected and other factors during thickness detection is avoided.
Secondly, a double-side grazing incidence interference technology is adopted, the problem of poor interference pattern contrast caused by low reflectivity of an unpolished surface of the wafer to be tested under normal incidence is solved, meanwhile, the incidence angles of the test light beams on the two surfaces are the same, so that a set of light beam shaping system can be shared in a subsequent light path, and the light path structure is simplified.
Thirdly, a beam shaping system comprising two parabolic cylindrical reflectors is adopted to replace a relay optical system and a folding optical system which meet the Scheimpflug principle arrangement in the prior art 2, so that the structure of the device is greatly simplified, and the problem of mapping errors in an interference pattern is solved.
Fourthly, the four-wave front transverse shearing interference technology with the characteristics of common optical path and self-interference is adopted to replace the traditional interference technology in the prior art 1 and 2, and by virtue of the self-interference characteristic, the demodulation can be realized only by a single interference image without phase-shifting interference, so that the shielding problem possibly caused by a phase-shifting mechanism is avoided; meanwhile, by means of the characteristic of complete common light path, the disturbance of environmental factors to interference fringes can be greatly reduced.
Fifthly, a detection method corresponding to the wafer detection device is provided.
Drawings
Fig. 1 is a light path model diagram of a wafer flatness detection apparatus based on a bilateral grazing incidence common-path self-interference technique, in which local light paths or structures at different viewing angles are provided in lower dotted frames;
FIG. 2 is a model diagram of a common-path self-interference system, where a is an optical path model, b is a four-wavefront distribution map at an image plane of a camera, and c is an example of a four-wavefront transverse shear interference map;
FIG. 3 is a flow chart of a method for testing the proposed apparatus;
FIG. 4 is a schematic diagram for an interference factor (ISF);
FIG. 5 is a diagram showing flatness parameters, wherein a is BOW, b is Warp, c is SORI, and d is TTV.
Detailed Description
The invention is further illustrated by the following figures and examples.
The optical path structure of the device proposed by the invention is explained in detail as follows:
fig. 1 is a light path model diagram of a wafer flatness detection apparatus based on a double-side grazing incidence common-path self-interference technique according to the present invention. As shown in fig. 1, light emitted by a laser (S1) (which is an emitted light beam of a laser collimating head if a fiber laser is used) is split into two paths by a first beam splitter (S3) after being expanded by a collimating beam expander (S2), wherein one path is reflected by the first reflector (S4) for 90 degrees and then reflected by a second reflector (S5) to be incident on the lower surface (S7a) of a wafer to be measured (S7) at a grazing incidence angle θ, and the other path is directly reflected by a third reflector (S6) to be incident on the upper surface (S7b) of the wafer to be measured (S7) at the same incidence angle θ; the light reflected by the lower surface (S7a) is reflected by the fourth reflecting mirror (S8) and then enters the beam splitter (S11), the light reflected by the upper surface (S7b) sequentially passes through the fifth reflecting mirror (S9) and the sixth reflecting mirror (S10) and then also enters the beam splitter (S11), the two light paths are converged into one light path in the beam splitter (S11), then the light path is shaped by the beam shaping system (S12), the beam aperture is reduced by the beam reducer (S13), and finally the interference pattern is generated and collected by the co-path self-interference system (S14).
The grazing incidence angle refers to a large incidence angle of 80 ° or more, because the wafer has a polished surface and an unpolished surface, and an incidence angle closer to 90 ° can make the unpolished surface have higher reflectivity to light rays, so that the interference pattern has good contrast. In addition, light spots projected onto two surfaces of the wafer to be tested need to cover all test areas of the wafer to be tested, and simultaneously, for the purpose that subsequently calculated surface type distribution can be correspondingly subtracted, the Y coordinates of the central points of the two light spots need to be consistent, here, the centers of the two light spots are coincided with the central points Oa and Ob of the two surfaces of the wafer to be tested, and at the moment, the two light spots are consistent in Y coordinates and are also concentric with the corresponding surface to be tested.
In order to ensure that the optical axis (Z axis) of the system does not change, the poses of S3-S11 should meet the following requirements:
the system optical axis (Z axis) direction is the light emitting direction of the collimation beam expander (S2), the acute angle between the first spectroscope (S3), the second spectroscope (S11), the first reflector (S4) and the system optical axis (S10) is 45 degrees, the acute angle between the second reflector (S5), the third reflector (S6), the fourth reflector (S8), the acute angle between the fifth reflector (S9) and the system optical axis is theta/2, and the placing direction of the wafer to be measured (S7) is parallel to the system optical axis (namely the surface to be measured is in the XY plane).
Due to grazing incidence, P1The cross section of the light beam with a circular cross section at the position P3 behind the beam splitter S11 is an ellipse, and if the caliber of the wafer to be measured is D, the major axis of the ellipse is D (along the X-axis direction in FIG. 1) and the minor axis is Dcos theta (along the Y-axis direction in FIG. 1). If the interference pattern is not processed in this case, a mapping error is introduced into the finally obtained interference pattern, that is, each point in the interference pattern and each point on the surface to be measured are not in a linear mapping relationship, thereby affecting the detection accuracy. The solution provided here is to shape the elliptical spot, and the shaping system S12 includes two parabolic cylindrical mirrors, the generatrix of which forms an acute angle of 45 ° with the system optical axis, which has the effect of shaping the light beam with an elliptical cross-section at P3 into a light beam with a circular cross-section at P4, the radius of the circle being the original elliptical minor axis Dcos θ.
According to the difference of the sizes of the wafers to be detected, the width of the light beam at the position P4 is not necessarily matched with that of the co-channel self-interference system S14, so that the magnification-adjustable beam reducer S13 is arranged between the light beam and the light beam, and the diameter of the light beam is reduced to be matched with that of the entrance pupil of the co-channel self-interference system S14.
The common-path self-interference system S14 is a four-wavefront lateral shear interference (QWLLSI) system including a diffraction grating S14a for generating four wavefronts andcamera S14b, a model of which is shown in fig. 2. Wherein a in FIG. 2 is the internal optical path S14, as can be seen from the incident wave surface W0Four wave surfaces W with completely consistent shapes and only lateral deviation are generated through grating diffraction1、W2、W3、W4. As shown in fig. 2b, these four waved surfaces are superimposed on the camera image surface, and lateral shearing interference occurs in the overlapping region thereof, and an example of a lateral shearing interference pattern is shown in fig. 2 c.
The ideal model of the diffraction grating S14a is a cosine grating, whose amplitude transmittance t (x, y) is as in equation (1), where d is the period of the grating.
The Fraunhofer diffraction F (u, v) has four orders, as shown in formula (2), where the four orders correspond to the four wave surfaces participating in interference:
since the half-period transmittance of the cosine Grating is negative and cannot be made in reality, the actual Grating is an approximation to the ideal model, mainly including Cross Gratings (CG), an improved hartmann mask (MHM), a Random Encoded Hybrid Grating (REHG), and the like, and the approximation degree is gradually increased. If CG is selected as the diffraction grating, since there is an interference diffraction order with higher intensity, it is necessary to design an order selection window between the CG and the camera to select the required four orders.
The four-wavefront transverse shearing interferogram can be subjected to analysis and processing by a space frequency domain demodulation method through a Fourier spectrum of a single interferogram to obtain phase distribution, then the surface type distribution of a surface to be measured is calculated, and finally the flatness parameter of the wafer is calculated.
The method for testing the wafer flatness of the device provided by the invention is explained in detail as follows:
the test procedure comprises the following three main steps: the first step is that according to the light path structure requirement, the device is built and calibrated by using a standard component; the second step is that four-wave front transverse shearing interference is respectively carried out on the two surfaces of the wafer to be detected, and the interference pattern is demodulated to calculate the surface type distribution of the two surfaces; and thirdly, calculating each parameter representing the flatness of the wafer by using the obtained surface type distribution. The whole flow is shown in fig. 3, and the specific description of each step is as follows:
firstly, the construction and calibration work of the device are as follows:
first, the construction of the device is completed according to the general principles of optical system construction and the description of the device in the summary of the invention. The device is then calibrated using a standard, which may be a quartz disk conforming to the NIST standard or other standard selected according to the actual testing needs. The first purpose of calibration is to check whether the device works normally, and the second purpose is to calculate the system error by recording the surface profile distribution of two surfaces of the standard component as
And secondly, completing the interference detection of two surfaces of the wafer:
the device adopts common-path interference without providing reference light, so that when the surface shape of one surface of a wafer is detected, another light path needs to be blocked by a light blocking screen, and the inserted position of the light blocking screen is P in figure 11Or P2To (3). Firstly at P1A light blocking screen is inserted, and the phase distribution W introduced by the S7a surface is obtained by detection and calculation by utilizing the four-wave front transverse shear interference technologya(x, y); then at P2A light blocking screen is inserted, and the phase distribution W introduced by the S7b surface is obtained by detection and calculation by utilizing the four-wave front transverse shear interference technologyb(x, y). In interferometric detection, the phase distribution derived from the interferogram is not exactly equal to the surface distribution to be measured, but there is a conversion scaling factor called the interference factor (ISF). The calculation of the interference factor of the grazing incidence system is shown in FIG. 4, in which the surface at the reference position A on the surface to be measuredThe model actually protrudes to the position B, the protrusion amount is h, and the introduced optical path difference is AD + AC. The incidence angle is theta, and the expression of ISF is shown as formula (3):
ISF＝(AD+AC)/h＝1/(2cosθ) (3)
thus, Wa(x,y)、Wb(x, y) corresponding surface type distribution Fa0(x,y)、Fb0(x, y) is as in formula (4):
it should be noted that the profile distribution F is shown herea0(x,y)、Fb0(x, y) including systematic errors, and actual surface shapes F of two surfaces of the wafers S7a and S7b to be tested according to the surface shape calibration result of the standard component in the first stepa(x,y)、Fb(x, y) is as in formula (5):
thirdly, calculating the flatness parameters of the wafer:
the definition of each parameter characterizing the flatness of the wafer is shown in FIG. 5. Wherein BOW, WARP and SORI are parameters describing a single face and TTV is determined by the face type distribution of two faces.
The specific description of each parameter is as follows:
as shown in a of FIG. 5, BOW is the center O of a surface a (generally, a polished surface) of the wafer in the unclamped state0The point is relative to the reference plane raHeight deviation (i.e. O in the figure)0O1Length of). The non-clamping means that the wafer cannot be rigidly fixed by a certain clamp so as to prevent the surface shape of the wafer from being changed by stress. Reference plane raMay be given by the average height of the face or other criteria, and is generally a horizontal plane. Wherein BOW is positive if the O point is above the reference plane and negative otherwise.
As shown in b of FIG. 5, WARP is the highest point H of a surface a (generally a polished surface) of the wafer in the unclamped state0And the lowest point L0The height deviation between them, i.e. the PV (Peak-Valley) value of the face. Wherein H0、L0Is still the horizontal plane ra。
As shown in c of FIG. 5, the SORI is the highest point H of a surface a (generally, a polished surface) of the wafer in the unclamped state1And the lowest point L1Height deviation therebetween, here H1、L1The reference plane is an inclined fitting plane rtAnd is obtained by a least square method. Therefore, SORI is the PV value of the plane with respect to the tilted fitting plane.
TTV is the thickness Δ h at the thickest point between two surfaces of a wafer, as shown by d in FIG. 5MThickness delta h of the thinnest partmThe difference, i.e., the maximum variation range of the wafer thickness.
According to the above description, the calculation formula of the flatness parameters BOW, WARP, SORI and TTV is as follows (6):
wherein Fo、h0The height of the center position of the surface to be measured and the height of the horizontal reference surface are respectively, and the two heights need to select the same reference; f' is the inclined reference surface r rotating FtAnd obtaining the face shape according to the corresponding angle.
Claims (10)
1. Wafer flatness detection device based on bilateral grazing incidence common path self-interference technique which characterized in that: emergent light of the laser (S1) is split into two paths by the first beam splitter (S3) after being expanded by the collimation beam expander (S2), wherein one path is reflected by the second reflector (S5) after being turned by 90 degrees by the first reflector (S4) and then is incident to the lower surface (S7a) of the wafer to be measured (S7) at a grazing incidence angle theta, and the other path is directly reflected by the third reflector (S6) and is incident to the upper surface (S7b) of the wafer to be measured (S7) at the same incidence angle theta; the light reflected by the lower surface (S7a) is reflected by the fourth reflecting mirror (S8) and then enters the second beam splitter (S11), the light reflected by the upper surface (S7b) sequentially passes through the fifth reflecting mirror (S9) and the sixth reflecting mirror (S10) and then also enters the second beam splitter (S11), the two paths of light are converged into one path in the beam splitter (S11), then the beam is shaped by the beam shaping system (S12) and then condensed by the beam condenser (S13), and finally the interference pattern is generated and collected by the co-path self-interference system (S14).
2. The wafer flatness detection apparatus according to claim 1, wherein the grazing incidence angle θ is greater than or equal to 80 °.
3. The wafer flatness detection apparatus based on the double-side grazing incidence common-path self-interference technique as claimed in claim 1, wherein the center of the light spot projected onto the lower surface (S7a) and the upper surface (S7b) of the wafer to be tested (S7) through the second mirror (S5) and the third mirror (S6) and the center O of the corresponding surface are respectively projected onto the lower surface (S7a) and the upper surface (S7b) of the wafer to be testeda、ObAnd overlapping, wherein the size of the light spot can cover the whole area to be measured.
4. The wafer flatness detection apparatus based on the double-sided grazing incidence common-path self-interference technology as claimed in claim 1 or 2, wherein the system optical axis (Z-axis) direction is the light outgoing direction of the collimating beam expander (S2), the acute angles between the first beam splitter (S3), the second beam splitter (S11), the first reflector (S4), and the system optical axis (S10) are 45 °, the acute angles between the second reflector (S5), the third reflector (S6), the fourth reflector (S8), and the fifth reflector (S9) and the system optical axis are θ/2, and the placing direction of the wafer to be detected (S7) is parallel to the system optical axis.
5. The wafer flatness detection apparatus according to claim 1, wherein the beam shaping system (S12) includes two parabolic reflectors (S12a), (S12b) for reflecting P in the optical path3Shaping the light beam into P in the light path4The cross-section of the location is a circular beam.
6. The wafer flatness detection apparatus based on the double-side grazing incidence common-path self-interference technique according to claim 1, wherein the common-path self-interference system (S14) is a four-wavefront lateral shear interference system, and includes a diffraction grating (S14a) for generating four wavefronts and a camera (S14b) for collecting interferograms.
7. The wafer flatness detection apparatus based on the double-side grazing incidence common-path self-interference technique as claimed in claim 1, 2, 3, 4, 5 or 6, characterized in that the implementation method of the apparatus includes the following steps:
step 1, building a wafer flatness detection device based on a bilateral grazing incidence common path self-interference technology, calibrating the device by using a standard part, measuring the surface type distribution of two surfaces of the standard part, and recording the surface type distribution as
Taking it as a systematic error;
step 2, replacing the standard part with a wafer to be detected (S7), adjusting the pose, then respectively collecting interferograms of two surfaces of the wafer to be detected (S7), and demodulating the interferograms; and calculating the face shapes F of (S7a) and (S7b) by combining the system errors obtained by calibration in the step 1a(x,y)、Fb(x,y)；
Step 3, calculating specific numerical values of all parameters according to the definitions of all parameters representing the flatness of the wafer by using the surface type distribution calculated in the step 2;
the parameters comprise warping degree, deformation amount relative to a fitting surface and maximum thickness deviation.
8. The wafer flatness detecting apparatus according to claim 7, wherein the standard component used in the calibration in step 1 is a quartz plate meeting NIST standards or other standard components selected according to test requirements.
9. The wafer flatness detection apparatus according to claim 7, wherein the step 2 is performed by sequentially performing P on the wafer flatness detection apparatus1Or P2A light barrier is arranged at the position to shield the detection light path of one surface of the wafer (S7) to be detected so as to detectThe other side;
said P1A position is set between the first spectroscope (S3) and the third reflector (S6);
said P2The position is set between the first spectroscope (S3) and the first mirror (S4).
10. The wafer flatness detection apparatus based on the double-sided grazing incidence common-path self-interference technique as claimed in claim 7, wherein the face shape calculation process in step 2 includes:
firstly, the phase distribution W is adjusted from the interference diagrama(x,y)、Wb(x,y)；
Then multiplying the phase distribution by the interference factor to obtain a surface profile F containing the system errora0(x,y)、Fb0(x,y)；
Finally distributing the surface type Fa0(x,y)、Fb0(x, y) subtracting the standard part surface profile obtained in step 1 as the systematic error
The actual measurement surface profile distribution F of the surface to be measured can be obtaineda(x,y)、Fb(x,y)。
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